JPH117766A - Semiconductor memory apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent decrease of an operation speed because of a voltage drop and restrict consumption power by setting an output voltage high in anticipation of the voltage drop, and combining and driving optionally a plurality of drop voltage source circuits. SOLUTION: Comparison reference voltages VREF1 , VREF2 to maintain an output voltage of a drop voltage source circuit with a current control function in a constant range are set so that a source voltage VDD to a semiconductor memory apparatus and a peripheral circuit voltage VPER1 are increased by the amount of a voltage drop consequent to a memory operation. A decrease in operation speed by the voltage drop is prevented. Moreover, a chip activation signal ΦCS, a bank activation signal ΦOP are inputted respectively to gates of NMOS transistors TN3, TN6 of a pair of differential amplifiers of a comparison circuit of a current control circuit 72 outputting the VPER1 . Current feed performance is enhanced when a bank is activated, thereby preventing the decrease in speed of the memory operation. Electricity consumed by the internal voltage drop source circuit itself is restricted when the bank is not activated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a highly integrated semiconductor memory device, and more particularly to a technology effective when applied to a semiconductor memory device in consideration of an operation speed and power consumption due to a decrease in output voltage of an internal step-down power supply circuit.

[0002]

2. Description of the Related Art For example, as a technique studied by the present inventor, an internal step-down power supply circuit of a highly integrated semiconductor memory device is required to reduce power consumption, ensure the reliability of a fine device, and maintain the power supply voltage from the system construction side. It has been widely used for compatibility. In a general voltage supply method, a power supply voltage supplied from the outside is stepped down by an internal step-down power supply circuit, and the stepped down two kinds of voltages (VDL, VPERI) are supplied to a memory cell array of the internal circuit and its peripheral circuits, respectively. Then, the internal circuit in the semiconductor memory device is operated by two types of reduced voltages.

As a technique relating to a semiconductor memory device having such an internal step-down power supply circuit, for example, on November 5, 1994, Baifukan Co., Ltd., "Advanced Electronics I-9 Ultra LSI Memory", P239-P
324 and the like.

[0004]

The present inventors have studied the operation speed and power consumption of a semiconductor memory device having an internal step-down power supply circuit as described above due to a decrease in the output voltage of the internal step-down power supply circuit. The contents studied by the inventor will be described below with reference to FIGS.

FIGS. 7 and 8 are diagrams showing an internal voltage step-down system in a general high-integration semiconductor memory device. For example, as shown in FIG. 7, an external power supply voltage VDD of 3.3 V is stepped down, and a voltage VPERI of 2.5 V is supplied to peripheral circuits and a voltage VDL of 2.0 V is supplied to a memory cell array. In order to secure a wide operation area for this voltage VDD,
As shown in FIG. 8 showing the external power supply voltage dependency of the output voltage of the internal step-down power supply circuit, the voltage VDD (3.3 V ±
10%), the internal step-down voltage is a circuit that outputs a constant value.

In particular, a large number of circuits are connected to an internal step-down power supply circuit for supplying power to peripheral circuits, and high power supply capability is required. Further, as the operating frequency of the highly integrated semiconductor memory device increases, more supply capacity is required.

However, when a large load starts to operate due to the memory operation, the peripheral circuit that operates at the voltage VPERI as described above is greatly reduced in voltage from the set voltage due to insufficient supply capacity, and the operating speed of the memory is reduced accordingly. There is. Further, it is conceivable that increasing the set voltage may increase the power consumption of the internal step-down power supply circuit.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device capable of suppressing a reduction in operating speed due to a drop in output voltage of an internal step-down power supply circuit during a memory operation and at the same time suppressing power consumption of the internal step-down power supply circuit. Is what you do.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, in the semiconductor memory device according to the present invention, since the output voltage of the internal step-down power supply greatly decreases from the set value due to the memory operation, the chip activation signal and the bank for determining the memory operation in consideration of the voltage decrease The output voltage is set high by the activation signal.

Further, in order to minimize the output voltage drop of the internal step-down power supply circuit due to insufficient supply capability of the internal step-down power supply circuit and to suppress the power consumption of the internal step-down power supply circuit itself, a bank activation signal and a chip activation signal are used. Internal step-down power supply circuit that operates with both signals, internal step-down power supply circuit that operates only with chip activation signal, and internal step-down power supply circuit that keeps operating at all times. A power supply circuit is provided in a highly integrated semiconductor memory device, and all output nodes are connected.

According to this method, it is possible to suppress a decrease in operation speed due to a drop in the output voltage of the internal step-down power supply circuit during memory operation, and at the same time, to suppress the power consumption of the internal step-down power supply circuit itself.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, the same members are denoted by the same reference numerals, and the description thereof will not be repeated.

1A and 1B are a layout diagram and a partially enlarged view showing a semiconductor memory device according to an embodiment of the present invention, and FIG. 2 is a diagram showing a memory cell array in the semiconductor memory device according to the present embodiment. FIG. 3 is a characteristic diagram showing the dependency of the output voltage of the internal step-down power supply circuit on the external power supply voltage, FIG. 4 is a circuit diagram showing a step-down power supply circuit with a current control function, and FIG. FIG. 6 is a characteristic diagram showing the load current dependency of the output voltage of the power supply circuit, and FIG. 6 is an explanatory diagram showing a semiconductor memory device having various types and a plurality of internal step-down power supply circuits.

First, the configuration of the semiconductor memory device according to the present embodiment will be described with reference to FIG.

The semiconductor memory device of the present embodiment employs, for example, a hierarchical word line configuration and a multi-divided bit line configuration.
The memory chip 10 includes a 4M-bit or 256M-bit DRAM.
1, a main word driver region 12, a column decoder region 13, a peripheral circuit / bonding pad region 14, a memory cell array 15, a sense amplifier region 16, a sub-word driver region 17, an intersection region 18, etc. It is formed on a semiconductor chip. In FIG. 1, the horizontal direction is the row direction (word line direction), and the vertical direction is the column direction (bit line direction).

In this DRAM, for example, as shown in FIG. 1, a memory cell array 1 is provided on the left and right sides of a memory chip 10 in a row direction and on the upper and lower sides in a column direction.
5 are divided and arranged. The memory areas arranged on the left and right sides are arranged in pairs with a main row decoder area 11 arranged in the center via a main word driver area 12 corresponding to each memory area.

At the center of the upper and lower memory areas, column decoder areas 13 corresponding to the respective memory areas are arranged. Further, a row address buffer, a column address buffer,
A predecoder, a timing generation circuit, a data input / output circuit, an internal step-down power supply circuit which is a feature of the present invention, and the like are arranged, and further, a bonding pad for external connection is provided.

In the memory area, a sense amplifier area 16 is arranged in the column direction of the memory cell array 15 and a sub-word driver area 17 is arranged in the row direction. An intersection area 18 between the sense amplifier area 16 and the sub-word driver area 17 is provided. , An FX driver and a control circuit (such as a switch MOS transistor) for a sense amplifier group are also arranged. In this memory cell array 15, the word lines are in the row direction and the bit lines are in the column direction. Obviously, the present invention can be used in an arrangement opposite to this.

FIG. 2 is a simplified circuit diagram of the memory cell array 15 and its peripheral circuits. The main row decoder area 11, main word driver area 12, column decoder area 13, memory cell array 15, sense amplifier Region 16, sub-word driver region 17, intersection region 18
Circuits included in each area such as the input circuit 51, a predecoder 52, a main amplifier 61, an output circuit 62, and the like are illustrated.

The memory cell array 15 is composed of a plurality of two-dimensionally arrayed memory cells, for example, 64 Kbit memory cells of 256 subword lines × 256 bit line pairs. The same applies to the signal lines), the sub word line SW is in the horizontal direction, the bit lines BL and B are
LB and column selection signal lines YS are arranged in the vertical direction.
Word line configuration is hierarchical word line system, sense amplifier is 2
In the sub-array sharing method and the overdrive method, that is, the sense amplifier drive line CSP is initially set to the VDD voltage level and later to the VDL voltage level for speeding up.
The system is driven in stages. These are known (IEEE Journ
al of Solid-State Circuit, Vol. 31, No. 9, Sep. 1996, "A
29-ns 64-Mb DRAM with Hierarchical Array Architect
ure ") technology.

A sub-word driver area 17 is disposed adjacent to the left and right of the memory cell array 15, the inputs of the sub-word driver are a main word line MWB and a predecoder line FX, and the output is a sub-word line SW. As shown, a sense amplifier driver (three NMOS transistors in the figure, but a PMOS transistor may be used on the charging side) and a local I / O are provided in an intersection region 18 between the sense amplifier region 16 and the sub-word driver region 17 as shown.
O line LIO, LIOB and main IO line MIO, MIOB
Are provided.

Although not shown in the figure, sense amplifier drive lines CSP and CSN, local IO lines LIO and LIOB, and main IO lines MIO and MI are provided to further improve the performance.
A precharge circuit such as an OB or an FX driver may be provided. In addition to these, there are an input circuit 51, a predecoder 52, a main word driver, a column decoder, a main amplifier 61, an output circuit 62, and the like. In FIG. 2, SHR1 and SHR2 are shared sense amplifier separation signal lines,
SAP1 and SAP2 are sense amplifier charge signal lines, and SAN is a sense amplifier discharge signal line.

Further, an internal step-down system is used for low power and high reliability of a fine device, and a peripheral circuit is a voltage VPE.
RI (3.0 V), the memory cell storage voltage is the voltage VDL (2.
0V) and a voltage lower than the power supply voltage VDD (3.3V). Note that the input / output circuit uses the voltage VDD for interfacing with the outside. As is well known, in order to write the voltage VDL into the memory cell, the voltage VPP boosted by the charge pumping operation is required as the selection voltage of the sub-word line SW. Therefore, the voltage VPP is supplied to the operating voltage of the main word driver and the sub word driver. Plate voltage VPLT and bit line precharge voltage VBL
R supplies 1.0 V, which is 1/2 of the voltage VDL. The substrate voltage VBB is -1.0V.

In this hierarchical word line configuration, a word line is configured in a hierarchical configuration of a main word line and a sub-word line SW, and one main row decoder and a main word driver are shared by a plurality of sub-word lines SW. Line (MW, MWB), predecoder line (FX, FXB)
Metal wiring pitch can be relaxed from the pitch of the memory cells, and the production yield of metal wiring can be increased.

In this hierarchical word line configuration, the sub-word lines SW arranged in the row direction are the outputs of the sub-word driver. The sub-word driver includes a main row decoder, main word lines MW and MWB output from the main word driver. , FX drivers FX and FXB output from the FX driver are input to perform logical operations. When a main word line MW or MWB which is an input thereof is selected and a predecoder line FX and FXB in the column direction is selected, a high-level voltage is output to the sub word line SW. The read operation and the write operation of all the memory cells connected to the sub-word line SW are started.

In a read operation, an arbitrary memory cell in the memory cell array 15 is designated by selecting a sub-word line SW by a sub-word driver and selecting bit lines BL and BLB by a column decoder. Are amplified by a sense amplifier and then the local IO lines LIO and LIOB, the main IO lines MIO and MI
The data is read out to the OB and output from the output circuit 62 via the main amplifier 61. Similarly, at the time of the write operation, an arbitrary memory cell is designated by the sub-word line SW and the bit lines BL and BLB, and the write circuit (installed in parallel with the main amplifier 61, but omitted in FIG. 2) from the main IO
Lines MIO, MIOB, local IO lines LIO, LIO
B, Write to the memory cell via the sense amplifier.

FIG. 3 is a characteristic diagram showing in detail the dependence of the output voltage of the internal step-down power supply circuit on the external power supply voltage in the embodiment of the present invention and the technique of the comparative example (FIG. 8). This is when the load current is almost 0, that is, when the load circuit does not perform a pulse operation or operates at a slow frequency.

The solid line represents the output voltage VPERI for the peripheral circuit with respect to the external power supply voltage VDD according to the present invention, and the broken line represents the output voltage VPERI for the peripheral circuit with respect to the external power supply voltage VDD according to the technique of the comparative example. As is apparent from the figure, the standard range of the external power supply voltage VDD (3.3 V ± 10%
It can be seen that the output voltage is set higher (高 め 3.0 V to 3.6 V) than that of the comparative example.

That is, when the external power supply voltage VDD is 3.3 V, while the comparative example is set to 2.5 V,
In the present invention, the output voltage VPE for the peripheral circuit is set to 3.0 V.
RI has been set. The difference of 0.5 V is a voltage value corresponding to a voltage drop due to a memory operation in order to prevent the chip from operating at the highest frequency and to reduce a circuit operation speed caused by a voltage drop due to current consumption. In the present invention, the output voltage is set high in anticipation of this voltage drop. It should be noted that the voltage drop amount is set in the same manner in the standard range of the other external power supply voltage VDD.

Further, in order to set the output voltage of the internal step-down power supply circuit higher, the reference voltage VL, which is the reference of the output voltage VPERI, is set higher from 1.25 V in the comparative example to 1.5 V. In this embodiment, the output voltage VPERI is a voltage value of 3.0 V which is twice the reference voltage VL of 1.5 V, but this is for the purpose of simplifying the circuit configuration, and is limited to this relationship. It is not something that can be done.

The output voltage VPE of the internal step-down power supply circuit
RI falls gradually within the standard range of the external power supply voltage VDD (3.0 V to 3.6 V) kept constant at 3.0 V, especially at the lower limit of the external power supply voltage VDD, around 3.0 V. In the vicinity of the upper limit of the standard of the power supply voltage VDD, that is, 3.6 V, a constant set voltage of 3.0 V is output irrespective of the external power supply voltage VDD. Therefore, the lowering of the speed is suppressed as much as possible at the lower limit of the standard range, and the increase of power consumption and the withstand voltage failure of the device are suppressed at the upper limit.

FIG. 4 shows an internal step-down power supply circuit operated by both the bank activating signal and the chip activating signal according to the present embodiment.

This internal step-down power supply circuit has a reference voltage VRE
F1, VREF2, 1/5 voltage of external power supply voltage (VDD
/ 5) as an input to generate a reference voltage VL, and a reference voltage VL output from the reference voltage generation circuit 71 as an input, and a peripheral circuit voltage VPER.
A current control circuit 72 for generating I. For example, in the case of the present embodiment, the reference voltage VREF1 is 1.5 V,
The reference voltage VREF2 is 0.8V.

In particular, the voltage value of the reference voltage VREF1 determines the VPERI value in a region where the voltage VPERI becomes a constant value, and is set so as to be constant from the external power supply voltage VDD of 3.0 V, and the voltage of the reference voltage VREF2. The value determines the voltage to enter the burn-in mode, and is 4 times the external power supply voltage VDD.
V is set to enter the burn-in mode. The voltage value of this reference voltage is 1.5 V and 0.5 V as an easily obtainable voltage.
Although 8 V is set, it is not limited to this.

The reference voltage generation circuit 71 generates the reference voltage VRE
F2 and an external power supply voltage VDD / 5 as inputs, and a comparison circuit at the subsequent stage which receives the reference voltage VREF1 and the divided voltage of the reference voltage VL as inputs. Comparison with a reference voltage VREF2 of 1.8V, a reference voltage VREF1 of 1.5V by a comparison circuit in a subsequent stage
As a result, a reference voltage VL of 1.5 V stabilized within the standard range of the external power supply voltage VDD is generated.

The comparison circuit preceding the reference voltage generation circuit 71 includes an amplifier AMP1 for comparing the reference voltage VREF2 with the external power supply voltage VDD / 5, and PMOS transistors TP1, P gate-controlled by the output of the amplifier AMP1.
The variable resistor VR1 is controlled by a MOS transistor TP1. The comparison circuit at the subsequent stage is OR
The reference voltage VREF1 input through the gate OR1,
An amplifier AMP2 for comparing a voltage by a variable resistor VR1 with a voltage by a variable resistor VR2 to be described later;
It comprises a PMOS transistor TP2 whose gate is controlled by the output of P2, and a variable resistor VR2 whose current is controlled by the PMOS transistor TP2.

The current control circuit 72 includes a comparison circuit for detecting a potential difference between the reference voltage VL and the output voltage VPERI, and a feedback circuit for controlling a PMOS transistor according to the comparison result. VPERI
When the transient current tries to flow due to
The drain voltage fluctuates to the negative side due to the S-transistor acting as impedance, and when the drain voltage starts to drop below the reference voltage VL, the gate voltage becomes lower and the PMO becomes lower.
The S-transistor is turned on, starts charging while supplying current to the load, and when charging to a certain level starts to become larger than the reference voltage VL, the gate voltage rises, the PMOS transistor turns off, and charging stops. However, such an operation suppresses the fluctuation of the output voltage VPERI. When R1 = R2, VPERI = 2
× VL.

The comparison circuit of the current control circuit 72 includes a pair of two PMOS transistors TP3 to TP6 and 3
NMOS transistors TN1 to TN6,
The circuit configuration includes a pair of current mirror differential amplifiers each having a PMOS transistor TP7 as a load. In this pair of differential amplifiers, the reference voltage VL is input to the gate of one NMOS transistor TN2, and the voltage obtained by dividing the feedback output voltage VPERI by the resistors R1 and R2 is input to the gate of the other NMOS transistor TN5. As described above, the divided voltage of the output voltage VPERI is fed back, and the fluctuation of the reference voltage VL is suppressed.

Further, in the pair of differential amplifiers of the comparison circuit according to the present embodiment, the
The structure of the S transistors TN3, 6 is such that one NMOS transistor TN3 has a small gate width W and a large gate length L (W / L: small), and a chip activation signal ΦCS is input to this gate. The other NMOS transistor TN6 has a large gate width W and a small gate length L (W / L: large), and receives a bank activation signal ΦOP at its gate.

In particular, the chip activation signal .PHI.CS becomes High when a chip is selected to operate the NMOS transistor TN3 having a small gate width W / gate length L in the figure, and the bank activation signal .PHI. Is activated, the NMOS transistor TN6 having a large gate width W / gate length L is operated. As a result, when the bank is activated, the current supply capability of the internal step-down power supply circuit is increased, and a decrease in the memory operation speed is prevented. When the bank is not activated, the power consumption of the internal step-down power supply circuit itself can be suppressed.

FIG. 5 is an experimental result of the output voltage value of the internal step-down power supply circuit with respect to the output current in the case where the output voltage of the internal step-down power supply circuit is set higher and the case of the technique of the comparative example.

In this experiment, the gate width pattern WP of the NMOS transistor was set to 2500 μm and the gate length pattern L
Under the conditions that P is 0.8 μm, the temperature is 27 ° C., and the reference voltage VL is 1.5 V, the external power supply voltage VDD is 2.5 V and 3.0 V.
Output current IPER when set to V, 3.3V, 3.6V
It is a measurement of the characteristics of the output voltage VPERI with respect to I.

As can be seen from this figure, the output voltage VPERI with respect to the output current IPERI according to the technique of the present invention.
It can be seen that the decrease in the value is suppressed. That is, in the case of the external power supply voltage VDD of 2.5 V according to the technology of the comparative example, when the output current IPERI exceeds about 50 mA, the output voltage VPERI drops sharply, affecting the signal transmission speed. On the other hand, in the technology of the present invention,
For example, at an external power supply voltage VDD of 3.3 V, the output current IP
Output voltage VPERI even when ERI is about 150 mA
Can be maintained at about 2.5 V, and a decrease in signal transmission speed caused by a voltage drop can be suppressed.

FIG. 6 is an explanatory view showing that a plurality of types and a plurality of internal step-down power supply circuits according to the present invention are provided in a highly integrated semiconductor memory device and all output nodes thereof are connected.

In this figure, banks Bank0-B
4 shows a semiconductor memory device having a four-bank configuration based on ank3, and incorporates three types of internal step-down power supply circuits. Each of the banks Bank0 to Bank3 includes a memory cell array 15 and a direct peripheral circuit including a sense amplifier region 16, a sub-word driver region 17, and an intersection region 18.

In this highly integrated semiconductor memory device, both the bank activation signal ΦOPB and the chip activation signal ΦCS are used in order to minimize the output voltage drop of the internal step-down power supply circuit due to insufficient supply capability of the internal step-down power supply circuit. , And internal step-down power supply circuits 106 and 1 operating only with chip activation signal ΦCS.
07, and a voltage holding internal step-down power supply circuit 108 that operates at all times (Stby).

The internal step-down power supply circuits 100 to 105 are respectively operated by the bank activating signals ΦOPB0 to ΦOPB3 corresponding to the banks Bank0 to Bank3, and the adjacent bank Bank0 with the word driver interposed therebetween. It is divided into internal step-down power supply circuits 104 and 105 operated by bank activation signals ΦOPB02 and ΦOPB13 corresponding to the banks Bank2 and Bank1 and Bank3.

For example, bank Bank0 and bank Ba
When the memory operation of nk2 is performed, the internal step-down power supply circuit 108 which always operates but consumes low current, the internal step-down power supply circuit 106 which operates by the chip activation signal ΦCS,
107, furthermore, bank activation signals ΦOPB0, ΦOPB2, Φ for controlling the banks Bank0 and Bank2.
By operating the internal step-down power supply circuits 100, 102, and 104 that operate in combination with the OPB02, a voltage drop due to chip current consumption is suppressed.

As described above, the internal step-down power supply circuit 108 which always operates even during standby, the internal step-down power supply circuits 106 and 107 which operate according to the chip activation signal ΦCS, and the internal circuit which operates in combination with the bank activation signal ΦOPB By operating the step-down power supply circuits 100 to 105 arbitrarily in combination, it is possible to suppress a decrease in signal transmission speed, suppress an increase in power consumption, and selectively activate a plurality of power supply circuits in accordance with memory operation. In addition, the supply capability of the internal step-down power supply circuit can be optimally controlled.

Therefore, according to the semiconductor memory device of the present embodiment, by setting the output voltage of the internal step-down power supply circuit high in anticipation of the voltage drop accompanying the memory operation, the internal step-down power supply circuit during the memory operation is set. It is possible to suppress a reduction in operation speed due to a drop in output voltage, and at the same time, to suppress power consumption of the internal step-down power supply circuit. In particular, when a plurality of types and a plurality of internal step-down power supply circuits are incorporated, the supply capability can be optimized according to the memory operation.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment, and various modifications may be made without departing from the gist of the invention. It goes without saying that it is possible.

For example, in the above embodiment, 6
Although the description has been made with reference to the example of a 4 Mbit or 256 Mbit DRAM, or a synchronous DRAM, the present invention is not limited to this, and a more highly integrated DRA of another bit number is used.
M, SRAM, RAM, ROM, PROM, EPRO
The present invention is widely applicable to other semiconductor memory devices such as M and EEPROM.

[0055]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1) By setting the output voltage high in anticipation of the voltage drop due to the memory operation, the supply capacity can be increased and a stable voltage supply can be performed, and the memory can be operated without lowering the operation speed. be able to.

(2) By connecting all the output nodes of a plurality of types and a plurality of step-down power supply circuits and operating them arbitrarily in combination, it is possible to suppress a decrease in signal transmission speed, suppress an increase in power consumption, and The supply capability of the power supply circuit can be optimized according to the memory operation.

(3) According to the above (1) and (2), in a highly integrated semiconductor memory device, a step-down power supply capable of suppressing a decrease in operation speed due to a drop in output voltage during memory operation and at the same time, suppressing power consumption. A semiconductor memory device having a built-in circuit can be obtained.

[Brief description of the drawings]

FIGS. 1A and 1B are a layout diagram and a partially enlarged view showing a semiconductor memory device according to an embodiment of the present invention;

FIG. 2 is a circuit diagram showing a memory cell array and its peripheral circuits in the semiconductor memory device according to one embodiment of the present invention;

FIG. 3 is a characteristic diagram showing an external power supply voltage dependency of an output voltage of an internal step-down power supply circuit in one embodiment of the present invention.

FIG. 4 is a circuit diagram showing a step-down power supply circuit with a current control function in one embodiment of the present invention.

FIG. 5 is a characteristic diagram showing a load current dependency of an output voltage of an internal step-down power supply circuit in one embodiment of the present invention.

FIG. 6 is an explanatory diagram showing a semiconductor memory device including a plurality of types and a plurality of internal step-down power supply circuits according to an embodiment of the present invention;

FIG. 7 is an explanatory diagram showing an internal voltage step-down method in a semiconductor memory device as a premise of the present invention.

FIG. 8 is a characteristic diagram showing the dependence of the output voltage of the internal step-down power supply circuit on the external power supply voltage in the semiconductor memory device on which the present invention is based;

[Explanation of symbols]

 Reference Signs List 10 memory chip 11 main row decoder area 12 main word driver area 13 column decoder area 14 peripheral circuit / bonding pad area 15 memory cell array 16 sense amplifier area 17 sub word driver area 18 intersection area 51 input circuit 52 predecoder 61 main amplifier 62 output Circuit 71 Reference voltage generation circuit 72 Current control circuit 100 to 108 Internal step-down power supply circuit MW, MWB Main word line FX, FXB Predecoder line SW Sub word line BL, BLB Bit line YS Column select signal line LIO, LIOB Local IO line MIO, MIOB Main IO line SHR1, Shared sense amplifier separation signal line PCB Bit line precharge signal line CSP, CSN Sense amplifier drive line SAP1, Sense amplifier charge signal line AN sense amplifier discharge signal line AMP1, AMP2 amplifier TP1～TP7 PMOS transistor VR1, VR2 variable resistance OR1 OR gate TN1～TN6 NMOS transistors R1, R2 resistor Bank0~Bank3 Bank

Claims (6)

[Claims] 1. A semiconductor memory device having a step-down power supply circuit for generating an internal power supply voltage by stepping down an external power supply voltage, wherein the step-down power supply circuit clamps an output voltage to a predetermined value or less within an operation standard range. A semiconductor memory device having a function of adding a voltage drop due to current consumption accompanying a memory operation to an internal power supply voltage in advance. 2. The semiconductor memory device according to claim 1, wherein a voltage output from said step-down power supply circuit gradually drops near a lower limit of an operation standard of said external power supply voltage, and falls at a upper limit of said external power supply voltage standard. A semiconductor memory device which outputs a constant set voltage irrespective of the external power supply voltage. 3. The semiconductor memory device according to claim 1, wherein a part of the plurality of step-down power supply circuits to which outputs are connected includes an NMOS transistor operated by a chip activation signal and having a small gate width / gate length. A semiconductor memory device having a current control function of an NMOS transistor operated by a bank activation signal and having a large gate width / gate length. 4. The semiconductor memory device according to claim 1, wherein a plurality of types and a plurality of said step-down power supply circuits are built in, and all output lines of said various types and a plurality of step-down power supply circuits are connected. A semiconductor memory device characterized in that a current supply capability of a step-down power supply circuit itself is changed by increasing or decreasing a consumed current to achieve a stable voltage supply in accordance with an operation state of a load circuit. 5. The semiconductor memory device according to claim 4, wherein said plurality of and a plurality of step-down power supply circuits are operated by both a bank activation signal and a chip activation signal, and a chip. 1. A semiconductor memory device comprising: a step-down power supply circuit that operates only by an activation signal; and a step-down power supply circuit that constantly operates to hold a voltage. 6. The semiconductor memory device according to claim 1, wherein said semiconductor memory device is a highly integrated DRAM.