JPH1166853A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a boosted voltage generating circuit whose constitution is simple and whose reliability is high by making a boosted voltage to be transmitted to the input side of the output MOSFET of a double boost type pumping circuit to be double a power source voltage and making a boosted voltage as a switch control signal to be supplied to the gate of the FET a boosted voltage in which the power source voltage and a double internal lowered voltage is combined. SOLUTION: When an oscillation pulse OSC is changed to a high level, the boosted voltage of VDD+2VDL is formed by a capacitor C2 to turn an MOSFET Q17 on. At the same time, the boosted voltage of 2VDD is formed by a capacitor C4 and a charge sharing is generated in between the capacitor C4 and a boosted voltage VPP through the MOSFET Q17 and a current supply such as the boosted voltage VPP is not lowered by a load current is performed. Thus, the maximum voltage is suppressed at VDD+2VDL and the reliability can be secured even with respect to the thinning of gate insulating films of MOSFETs Q17, Q14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and, more particularly, to a technology effective for use in a dynamic RAM (random access memory) having a built-in boost voltage generating circuit.

[0002]

2. Description of the Related Art A dynamic RAM having a pumping circuit for forming a substrate back bias voltage and a boosted voltage.
For example, Japanese Patent Application Laid-Open No. 3-214669 is disclosed. The pumping circuit (charge pump circuit) for generating a substrate back bias voltage and a boosted voltage according to this publication is composed of a main circuit and a sub-circuit, and the sub-circuit has only a small current supply capability to compensate for a leak current or the like. You.

[0003]

When writing a high level of a bit line to a dynamic memory cell comprising a storage capacitor and an address selection MOSFET, the word line selection level is set with respect to the bit line high level. It is necessary to use a high voltage that is boosted by the threshold voltage of the MOSFET. That is, the word line selection level is determined based on the high level of the bit line. With the miniaturization of elements due to the increase in storage capacity, the gate oxide film of the above-mentioned address selection MOSFET is also reduced in thickness, and the electric field strength of the gate oxide film becomes a problem. Therefore, it is conceivable that the power supply voltage supplied from the external terminal is reduced to form a constant-voltage internal reduced voltage to lower the word line selection level.

For example, the power supply voltage VDD supplied from an external terminal is reduced to about 3.3 V, and the operating voltage of the sense amplifier is reduced to about 2.2 V. Thus, the selection level of the word line can be suppressed as low as about 3.8V. In this case, the power supply voltage VD
For D, a relatively large fluctuation range is allowed. For example, a double-boost pumping circuit is used so that a boosted voltage VPP such as 3.8 V is obtained even if the voltage drops to around 2.2 V. It is good. However, when the power supply voltage VDD fluctuates in the direction of the high voltage, a high voltage reaching 10 volts is generated inside the double boost type pumping circuit, and as described above, the gate insulating film becomes thin due to the miniaturization of the element. It has been found that there is a problem that the possibility of the gate insulating film destruction increases.

An object of the present invention is to provide a semiconductor integrated circuit device provided with a boosted voltage generating circuit which achieves high reliability with a simple configuration. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0006]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, in the double boost type pumping circuit, the boost voltage transmitted to the input side of the output MOSFET is a boost voltage that is twice the power supply voltage, and the boost voltage as the switch control signal supplied to the gate of the output MOSFET is The boosted voltage is a combination of the power supply voltage and the double internal step-down voltage.

[0007]

FIG. 1 is a schematic layout diagram showing one embodiment of a dynamic RAM on which an internal boosted voltage circuit according to the present invention is mounted. In the figure, of the circuit blocks constituting the dynamic RAM, a portion related to the present invention is shown so as to be understood. It is formed on one semiconductor substrate.

In this embodiment, although not particularly limited, the memory array is divided into four as a whole. Two memory arrays are divided into two on the left and right sides in the longitudinal direction of the semiconductor chip, and an address input circuit, a data input / output circuit, an input / output interface circuit including a bonding pad row, and the like are provided in the central portion 14. Column decoder regions 13 are arranged in portions of both sides of the central portion 14 in contact with the memory array.

As described above, in each of the four memory arrays divided into two on the left and right and two on the upper and lower sides with respect to the longitudinal direction of the semiconductor chip, the main row decoder is disposed at the upper and lower central parts in the longitudinal direction. An area 11 is provided. Main word driver regions 12 are formed above and below the main row decoder, and drive the main word lines of the vertically divided memory array. An internal voltage generating circuit 19 is provided at a central portion of the semiconductor chip that divides the longitudinal direction into two. The internal voltage generation circuit 19 includes the boosted voltage circuit and the substrate voltage generation circuit.

The above-mentioned memory cell array (sub-array) 15
Are formed so as to be surrounded by the sense amplifier region 16 and the sub-word driver region 17 with the memory cell array 15 interposed therebetween, as shown in the enlarged view. An intersection between the sense amplifier region and the sub-word driver region is an intersection region (cross area) 18. The sense amplifiers provided in the sense amplifier region 16 are configured by a shared sense method, and except for the sense amplifiers arranged at both ends of the memory cell array, complementary bit lines are provided on the left and right around the sense amplifier. Selectively connected to the complementary bit lines of the memory cell array.

As described above, the memory arrays divided into four on the left and right sides in the longitudinal direction of the semiconductor chip are arranged in groups of two. The two memory arrays thus arranged in groups of two each have a main row decoder region 11 and a main word driver 1 in the center thereof.
2 are arranged. This main row decoder area 11
It is provided in common corresponding to the two memory arrays which are divided up and down around the center. The main word driver 11 generates a selection signal of a main word line extended so as to penetrate the one memory array. Also,
The main word driver 11 is also provided with a driver for selecting a sub-word, and extends in parallel with the main word line to form a selection signal for a sub-word selection line, as described later.

Although not shown, one memory cell array (sub-array) 15 shown as an enlarged view has 256 sub-word lines and 256 pairs of complementary bit lines (or data lines) orthogonal thereto. In the one memory array, 16 memory cell arrays (sub arrays) 15 are provided in the word bit line direction. Therefore, the sub word lines as a whole are provided for about 4K, and 8 sub word lines are provided in the word line direction. The bit line is about 2
K are provided. Since eight such memory arrays are provided in total, a large storage capacity such as 8 × 2K × 4K = 64 Mbits is provided.

The one memory array is divided into eight in the main word line direction. A sub-word driver (sub-word line driving circuit) 17 is provided for each of the divided memory cell arrays 15. The sub-word driver 17 is divided into の 長 of the length of the main word line, and forms a sub-word line selection signal extending in parallel with the length. In this embodiment, in order to reduce the number of main word lines, in other words, to reduce the wiring pitch of the main word lines, there is no particular limitation. Are arranged four sub-word lines. In order to select one sub-word line from among the sub-word lines divided into eight in the main word line direction and four in the complementary bit line direction, a sub-word selection driver is used. Be placed. This sub-word selection driver is extended in the arrangement direction of the sub-word drivers.
A selection signal for selecting one of the sub-word selection lines is formed.

Focusing on the one memory array, 1
One sub-word selection line is selected in a sub-word driver corresponding to one memory cell array including a memory cell to be selected among eight memory cell arrays allocated to one main word line, resulting in one main word One sub-word line is selected from 8 × 4 = 32 sub-word lines belonging to the line. As described above, 2K (2048) memory cells are provided in the main word line direction.
/ 8 = 256 memory cells are connected.
Although not particularly limited, in a refresh operation (for example, a self-refresh mode), eight sub-word lines corresponding to one main word line are set to a selected state.

As described above, one memory array has a storage capacity of 4K bits in the complementary bit line direction. However, if as many as 4K memory cells are connected to one complementary bit line, the parasitic capacitance of the complementary bit line increases, and a signal level that is read out cannot be obtained due to the capacitance ratio with a fine information storage capacitor. To
It is also divided into 16 in the complementary bit line direction. That is,
The complementary bit line is divided into 16 by the sense amplifier 16 indicated by a thick black line. Although not particularly limited, the sense amplifiers 16 are configured by a shared sense system, and are provided at both ends of the memory array.
Except for the above, complementary bit lines are provided on the left and right with respect to the sense amplifier 16, and are selectively connected to one of the left and right complementary bit lines.

FIG. 2 is a schematic layout diagram for explaining a dynamic RAM according to the present invention. The figure shows a schematic layout of the entire memory chip,
The layout of one memory array divided into eight is shown. This figure illustrates the embodiment of FIG. 7 from another point of view. That is, as in FIG. 7, the memory chip is located at right and left and up and down with respect to the longitudinal direction (word line direction).
Each memory array is divided into four parts, and a plurality of bonding pads and peripheral circuits (Bonding Pad & peripheral Circuit) are provided in the central part in the longitudinal direction.

Each of the two memory arrays has a storage capacity of about 8 Mbits, and one of them is divided into eight in the word line direction as shown in an enlarged manner. A sub-array divided into 16 in the bit line direction is provided. On both sides of the sub-array in the bit line direction, sense amplifiers (Sence Amplifiers) are arranged in the bit line direction. A sub-word driver (Sub-Wo) is provided on both sides of the sub-array in the word line direction.
rd Driver) is placed.

The one array is provided with a total of 4096 word lines and 2048 pairs of complementary bit lines.
As a result, the storage capacity is about 8 Mbits in total. As described above, 4096 word lines are divided into 16 sub-arrays and arranged, so that one sub-array is provided with 256 word lines (sub-word lines). In addition, since 2048 pairs of complementary bit lines are divided into eight sub-arrays as described above, one sub-array is provided with 256 pairs of complementary bit lines.

At the center of the two arrays, a main row decoder is provided. In other words, on the left side of the array shown in the figure, an array control circuit and a main word driver correspond to the main row decoder provided in common with the array provided on the right side. Is provided. The array control circuit includes a driver for driving the first sub-word selection line. A main word line extending so as to penetrate the eight divided sub-arrays is arranged in the array. The main word driver drives the main word line. Like the main word line, the first sub-word selection line is extended so as to pass through the eight divided sub-arrays. Above the array, a Y decoder (YDecoder) and a Y select line driver (YS
driver).

FIG. 3 is a schematic layout diagram showing one embodiment of a sub-array and its peripheral circuits in a dynamic RAM according to the present invention. FIG. 2 exemplarily shows four subarrays SBARY arranged at hatched positions in the memory array shown in FIG. In the drawing, the region where the sub-array SBARY is formed is shaded to distinguish the sub-word driver region, the sense amplifier region and the cross area provided around the region.

The subarray SBARY is divided into the following four types. That is, when the extending direction of the word line is the horizontal direction, the first sub-array SBA
RY has 256 sub-word lines SWL and 256 complementary bit line pairs. Therefore, the above 2
The 256 sub-word drivers SWD corresponding to the 56 sub-word lines SWL are connected to the left and right of the sub-array by one.
It is divided into 28 pieces and arranged. The 256 sense amplifiers SA provided corresponding to the 256 pairs of complementary bit lines BL are of a shared sense amplifier type as described above, and are divided into 128 units above and below the sub-array.

As described above, the second sub-array SBARY arranged on the upper right has 256 sub-word lines SWL.
In addition to the book, eight spare word lines are provided. Therefore, the 264 sub-word drivers SWD corresponding to the above-mentioned 256 + 8 sub-word lines SWL are divided and arranged on the left and right of the sub-array in units of 132. As described above, the lower right sub-array has 256 pairs of complementary bit lines B
L, and 128 sense amplifiers are arranged vertically as described above. The 128 pairs of complementary bit lines formed in the upper and lower sub-arrays SBARY on the right side are commonly connected to the sense amplifier SA interposed therebetween via a shared switch MOSFET.

The third sub-array SBARY arranged at the lower left as described above is composed of 256 sub-word lines SWL, like the sub-array SBARY adjacent to the right.
As described above, 128 sub-word drivers are divided and arranged. The subarrays SBA arranged on the lower left and right sides
The 128 sub-word lines SWL of RY correspond to the 128 sub-word drivers SW formed in the region sandwiched between them.
D is commonly connected. The subarray SBARY arranged at the lower left as described above has four pairs of spare bit lines 4RE in addition to 256 pairs of normal complementary bit lines BL.
D is provided. Therefore, the 260 sense amplifiers SA corresponding to the 260 pairs of complementary bit lines BL are:
130 sub-arrays are divided and arranged above and below the sub-array.

As described above, the fourth sub-array SBARY arranged at the upper left has 256 regular sub-word lines SWL and eight spare sub-word lines R similarly to the right adjacent sub-array SBARY. Similarly, since four spare bit lines are provided in addition to the 256 normal complementary bit line pairs, the sub-word driver can
132 parts are arranged on the left and right sides, respectively.
A is arranged by dividing 130 vertically.

The main word lines MWL are extended as one of them is exemplarily shown as a representative. Also,
The column selection line YS is extended in the vertical direction in the figure as one of them is exemplarily shown as a representative. A sub-word line SWL is arranged in parallel with the main word line MWL, and a complementary bit line BL (not shown) is arranged in parallel with the column selection line YS. In this embodiment, although not particularly limited, in the memory array of 8 Mbits as shown in FIG. 2, eight sets of subarrays are formed in the bit line direction and the word line direction is formed using the above four subarrays as a basic unit. Four sets of sub-arrays are configured. Since one set of sub-arrays is composed of four sub-arrays, 8 × 4 × 4 = 128 sub-arrays are provided in the 8-Mbit memory array. Since eight 8M-bit memory arrays are provided for the entire chip, 128 ×
As many as 8 = 1024 subarrays are formed.

For the above four sub-arrays, 8
The sub-word select lines FX0B to FX7B are extended so as to penetrate four sets (eight) of sub-arrays, similarly to the main word line MWL. Then, the sub word select line FX
Four lines consisting of 0B to FX3B and four lines consisting of FX4B to FX7B are separately extended on the upper and lower sub-arrays. The reason why one set of sub-word selection lines FX0B to FX7B are allocated to the two sub-arrays and they are extended on the sub-arrays is to reduce the memory chip size.

When the above eight sub-word select lines FX0B to FX7B are allocated to each sub-array and are formed in wiring channels on the sense amplifier area, as many as 16 sub-arrays as in the memory array of FIG. Since 32 memory arrays are arranged in total, 8 × 32 = 256 wiring channels are required. On the other hand, in the above-described embodiment, the wiring itself is connected to the two
Allocate sub word select lines FX0B to FX7B
Moreover, by arranging it so as to pass over the sub-array, it can be formed without providing a special wiring channel.

In the first place, one main word line is provided for eight sub-word lines on the sub-array, and a sub-word selection line is used to select one of the eight sub-word lines. Is necessary. Since one main word line is formed for every eight sub word lines formed in accordance with the pitch of the memory cells, the wiring pitch of the main word lines is gentle. Therefore, it is relatively easy to form the sub-word selection line between the main word lines using the same wiring layer as the main word line.

The sub-word driver of this embodiment selects one sub-word line SWL by using a selection signal supplied through the sub-word selection line FX0B and the like and a selection signal obtained by inverting the selection signal as described later. take.
The sub-word driver employs a configuration in which the sub-word lines SWL of the sub-arrays arranged on the left and right of the sub-word driver are simultaneously selected. Therefore, as described above, for two sub-arrays, 128 × 2 = 2
The four sub-word selection lines are allocated and supplied to as many as 56 sub-word drivers. That is, focusing on the sub-word selection line FX0B, it is necessary to supply a selection signal to as many as 256 ÷ 4 = 64 sub-word drivers.

If the one extending in parallel with the main word line MWL is a first sub-word selection line FX0B,
The six sub-word selection line driving circuits FXD which are provided in the upper left cross area and receive the selection signal from the first sub-word selection line FX0B are arranged in the above-mentioned vertical direction.
A second sub-word line FX0 that supplies a selection signal to the four sub-word drivers is provided. The first sub-word selection line FX0B extends in parallel with the main word line MWL and the sub-word line SWL, while the second sub-word selection line FX0B extends in parallel with the second sub-word selection line FX0B.
Of the sub-word selection line is orthogonal to the column selection line Y
S and the parallel bit line BL. For the eight first sub-word selection lines FX0B to FX7B, the second sub-word selection lines FX0 to FX7 are divided into even numbers FX0, 2, 4, 6 and odd numbers FX1, 3, 5, 7 Then, they are distributed to sub-word drivers SWD provided on the left and right of the sub-array SBARY.

The sub word select line driving circuit FXD is
In the same drawing, as shown by a triangle, two pieces are distributed above and below one cross area. That is, as described above, in the upper left cross area, the sub-word selection line driving circuit arranged on the lower side operates the first sub-word selection line F
Two sub-word selection line driving circuits FXD corresponding to X0B and provided in the cross area of the left middle part correspond to the first sub-word selection lines FX2B and FX4B, and are provided on the upper side provided in the lower left cross area. The arranged sub-word selection line driving circuit operates the first sub-word selection line FX.
6B.

In the upper central cross area, a lower sub word select line driving circuit corresponding to the first sub word select line FX1B is provided, and two sub word select line drivers provided in the central middle cross area are driven. Circuit FXD
Correspond to the first sub-word selection lines FX3B and FX5B, and the upper sub-word selection line drive circuit provided in the cross area at the lower center corresponds to the first sub-word selection line FX7B. In the upper right cross area, the lower sub word select line drive circuit corresponds to the first sub word select line FX0B, and two sub word select line drive circuits provided in the right middle cross area. FXD corresponds to the first sub-word selection lines FX2B and FX4B, and the upper sub-word selection line driving circuit provided in the lower right cross area corresponds to the first sub-word selection line FX6B. As described above, the sub-word driver provided at the end of the memory array drives the sub-word line SWL only on the left side since there is no sub-array on the right side.

In the configuration in which the sub-word selection lines are arranged between the pitches of the main word lines on the sub-array as in this embodiment, a special wiring channel can be made unnecessary.
Even if eight sub-word selection lines are arranged in one sub-array, the memory chip does not become large. However, the sub-word selection line driving circuit F
The area is increased to form the XD, which hinders high integration. That is, in the cross area, a switch circuit IOS provided corresponding to the main input / output line MIO and the sub input / output line LIO as shown by the dotted line in FIG.
This is because there is no area allowance because peripheral circuits such as W, a power MOSFET for driving the sense amplifier, a drive circuit for driving the shared switch MOSFET, and a drive circuit for driving the precharge MOSFET are formed.

In the sub-word driver, the second word
Are provided in parallel with the sub-word selection lines FX0 to FX6, etc., for passing selection signals corresponding to the first sub-word selection lines FX0B to FX6B. However, since the load is small as described later, 2 sub-word select line F
X0 to X6 are provided by wiring directly connected to the first sub-word selection lines FX0B to FX6B without providing a special driver FXD. However, the same wiring layer as the second sub-word selection lines FX0 to FX6 is used.

Among the cross areas, those arranged in the extension direction A of the second sub-word selection lines FX0 to FX6 corresponding to the even numbers are provided with a constant voltage with respect to the sense amplifier as indicated by P in FIG. N for supplying the internal voltage VDL
A channel-type power MOSFET, a P-channel type power MOSFET that supplies a clamp voltage VDDCLP for overdrive to the sense amplifier as described later with respect to the sense amplifier as indicated by O, and an N as indicated by O. An N-channel power MOSFET for supplying the circuit ground potential VSS to the sense amplifier is provided.

Among the cross areas, those arranged in the extending direction B of the second sub-word selection lines FX0 to FX6 corresponding to the odd numbers include the precharge and equalization of the bit lines as shown by B in FIG. An N-channel drive MOSFET for turning off the MOSFET,
The circuit ground potential V with respect to the sense amplifier
N-channel type power MOSF for supplying SS
An ET is provided. This N-channel type power MOS
FET is an amplifying MOSFET of an N-channel type MOSFET constituting a sense amplifier from both sides of a sense amplifier row.
Are supplied with a ground potential. That is, for the 128 or 130 sense amplifiers provided in the sense amplifier area, the N-channel type power MOSFET provided in the cross area on the A side and the N-channel power MOSFET provided in the cross area on the B side are provided. The ground potential is supplied by both of the channel type power MOSFETs.

As described above, the sub-word line drive circuit SWD
Selects the sub-word lines of the sub-arrays on both sides with respect to the center. On the other hand, two sense amplifiers are activated corresponding to the selected sub-word lines of the two sub-arrays. That is, when the sub-word line is set to the selected state, the address selection MOSFET is turned on and the charge of the storage capacitor is combined with the bit line charge, so that the sense amplifier is activated to return to the original charge state. This is because a write operation needs to be performed.
For this reason, except for those corresponding to the subarrays at the ends, the power MOSFETs denoted by P, O and N
Is used to activate the sense amplifiers on both sides of it.

On the other hand, a sub-word line drive circuit SW provided on the right side of the sub-array provided at the end of the array
In D, only the sub-word lines of the sub-array are selected.
ET activates only the sense amplifier corresponding to the sub-array.

The sense amplifier is of a shared sense type, and among the subarrays arranged on both sides of the shared amplifier, the shared switch MOSFET corresponding to the complementary bit line on the side on which the subword line is not selected is turned off. As a result, the read signal of the complementary bit line corresponding to the selected sub-word line is amplified to perform a rewrite operation of returning the storage capacitor of the memory cell to the original charge state.

FIG. 4 is a schematic layout diagram showing one embodiment of a well region for forming a sub-array and its peripheral circuits in a dynamic RAM according to the present invention. FIG. 8 exemplarily shows eight representative examples including four sub-arrays SBARY arranged at the hatched positions as surrounded by a dotted line in the memory array shown in FIG. ing.

In the figure, the white portion is a P-type substrate (P
SUB). The ground potential VSS of the circuit is applied to the P-type substrate PSUB. The above P-type substrate PSU
B has two types of N-type well regions N as indicated by hatching.
WELL (VDL) and NWELL (VDDCLP) are formed. That is, the N-type well region in which the P-channel type amplification MOSFET forming the sense amplifier SA is formed and the N-type well region in which the power switch MOSFETs arranged in the cross area of the column A are formed are boosted voltages. A clamp voltage VDDCLP formed using VPP is supplied.

In the cross area of the column B, a P-channel MOSFET constituting a switch circuit IOSW provided corresponding to the sub-input / output line LIO, and a P-channel MOSFET for precharging and equalizing provided on the main input / output line are provided. An N-type well region in which a channel type MOSFET is formed is formed, and an internal voltage VDL formed by stepping down is supplied.

Sub-array and sub-word line drive circuit SW
An N-type well region DWELL formed at a deep depth is formed over the entire region where D is formed. The N-type well region having the deep depth is supplied with the boosted voltage VPP corresponding to the word line selection level. The sub-word line drive circuit SWD is provided in the N-type well region DWELL having the deep depth.
Forming a P-channel MOSFET that forms
The well region NWWLL is formed, and the deep N region is formed.
A boost voltage VPP is applied in the same manner as in the case of the mold well region DWELL.

The deep N-type well region DWELL
A P-type well region PWELL for forming an N-channel address selection MOSFET constituting a memory cell and an N-channel MOSFET of a sub-word drive circuit SWD is formed in the memory cell. These P-type well regions P
WELL is supplied with a substrate back bias voltage VBB which is set to a negative voltage. The triple well structure as described above is useful for forming a boosted voltage generation circuit as described later.

Referring to one of the eight divided arrays shown in FIG. 2, the above-described deep N-type well region DWELL
Is formed by using a total of 16 subarrays arranged in the bit line direction, with eight subarrays arranged in the word line direction as one unit. The cross area corresponding to the sub-word driver (Sub-Word Driver) arranged at both ends of the main word line extended on the array is the A area.
And arranged alternately like row B as described above.
Therefore, except for the end portion, the N-type well region N for forming the P-channel MOSFETs of the row A and two sense amplifiers (Sence Amplifiers) arranged on both sides thereof is described.
WELL (VDDCLP) is provided in common.

FIG. 5 is a main part circuit diagram of one embodiment of the sense amplifier section of the dynamic RAM according to the present invention and its peripheral circuits. FIG. 1 exemplarily shows a sense amplifier arranged between two sub-arrays and a circuit related thereto. The well region where each element is formed is shown by a dotted line, and the bias voltage applied thereto is also shown.

In the dynamic memory cell, one provided between the sub-word line SWL provided in the one sub-array and one of the complementary bit lines BL and / BL is exemplarily shown as a representative. ing. The dynamic memory cell includes an address selection MOSFET Qm and a storage capacitor Cs. Address selection MOS
The gate of the FET Qm is connected to the sub-word line SWL, the drain of the MOSFET Qm is connected to the bit line BL, and the storage capacitor Cs is connected to the source.
The other electrode of the storage capacitor Cs is shared and receives a plate voltage. The selection level of the sub-word line SWL is a high voltage VPP higher than the high level of the bit line by the threshold voltage of the address selection MOSFET Qm.

When the sense amplifier is operated at the internal step-down voltage VDL, the high level amplified by the sense amplifier and applied to the bit line is set to a level corresponding to the internal voltage VDL. Therefore, the high voltage VPP corresponding to the word line selection level is VDL +
Vth. The pair of complementary bit lines BL and / BL of the subarray provided on the left side of the sense amplifier are arranged in parallel as shown in FIG. Can be The complementary bit lines BL and / BL are connected to a shared switch MOS.
The FETs Q1 and Q2 are connected to input / output nodes of a unit circuit of the sense amplifier.

The unit circuit of the sense amplifier is composed of N-channel type amplifying MOSFETs Q5, Q6 and P-channel type amplifying MOSFETs Q7, Q8, whose gates and drains are cross-connected to form a latch. The sources of the N-channel MOSFETs Q5 and Q6 are connected to a common source line CSN. The sources of the P-channel MOSFETs Q7 and Q8 are connected to a common source line CS.
Connected to P. Each of the common source lines CSN and CSP is provided with a power switch MOSFET. Although not particularly limited, an N-channel type amplification MOS
Common source line C to which the sources of FETs Q5 and Q6 are connected
SN is the N provided in the cross area between the A and B sides.
Channel type power switch MOSFETs Q12 and Q
13 provides an operating voltage corresponding to the ground potential.

Although not particularly limited, the common source line CSP to which the sources of the P-channel type amplification MOSFETs Q7 and Q8 are connected is connected to the overdrive P-channel type power M provided in the A-side cross area.
OSFET Q15 and N for supplying the internal voltage VDL
A channel type power MOSFET Q16 is provided. The overdrive voltage is a boosted voltage VPP
Is supplied to the gate of the N-channel MOSFET Q1
4 is used. The power supply voltage VDD supplied from an external terminal is supplied to the drain of the MOSFET Q14,
The SFET Q14 is operated as a source follower output circuit, and the MOSFET Q1
Clamp voltage VDDC lowered by the threshold voltage of 4.
Form LP.

The boosted voltage VPP is a stabilized high voltage such as 3.8 V by controlling the operation of the charge pump circuit using a reference voltage as described later. The threshold voltage of the MOSFET Q14 is formed at a low threshold voltage lower than that of the address selection MOSFET Qm of the memory cell.
CLP is brought to a stabilized constant voltage such as about 2.9V. The MOSFET Q26 is a MOSFET forming a leak current path, and does not flow a minute current of about 1 μA. This prevents the VDDCLP from excessively rising due to the standby state (non-operating state) for a long period of time or the bump of the power supply voltage VDD, and the amplifying MOS to which the voltage VDDCLP at the time of such excessive increase is applied.
The operation delay due to the back bias effect of the FETs Q7 and Q8 is prevented.

In this embodiment, noting that the overdrive voltage of the sense amplifier is formed by the clamp voltage VDDCLP as described above, a P-channel type power MOSFET Q15 for supplying the voltage,
P channel type amplification MOSFET Q of sense amplifier
7, Q8 are formed in the same N-type well region NWELL as shown by the dotted line in the same figure, and the clamp voltage VDDCLP is supplied as the bias voltage. Then, a P-channel type amplifier M of the sense amplifier
The power MOSFET Q16 for applying the original operating voltage VDL to the common source line CSP of the OSFETs Q7 and Q8 has N
MOSF for overdrive as the channel type
It is formed electrically separated from the ETQ 14.

The N-channel type power MOSFET
Sense amplifier activation signal S supplied to the gate of Q15
AP2 is an overdrive activation signal / S supplied to the gate of the P-channel MOSFET Q15.
The signal has a phase opposite to that of AP1, and although not particularly limited, a high level thereof is a signal corresponding to the power supply voltage VDD. As described above, VDDCLP is about +2.9 V, and the minimum allowable voltage VDDmin of the power supply voltage VDD is about 2.9 V, for example.
The OSFET Q15 can be turned off, and a voltage corresponding to the internal voltage VDL can be output from the source side by using the N-channel MOSFET Q16 having a low threshold voltage.

An equalizing MOSF for short-circuiting a complementary bit line is connected to the input / output node of the unit circuit of the sense amplifier.
A precharge circuit including ETQ11 and switch MOSFETs Q9 and Q10 for supplying a half precharge voltage to a complementary bit line is provided. These MOSFETs
The gates of Q9 to Q11 share the precharge signal BL
EQ is supplied. The driver circuit for forming the precharge signal BLEQ provides an N-channel MOSFET Q18 in the cross area on the B side to make the falling speed faster. That is, in order to advance the timing of selecting a word line by starting memory access, the N-channel MOSFET Q18
In the ON state to constitute the precharge circuit.
This is to switch the SFETs Q9 to Q11 to the off state at high speed.

On the other hand, a P-channel MOSFET Q17 for forming a signal for starting a precharge operation
Are provided not in the cross area as described above, but in the Y decoder & YS driver section.
That is, the precharge operation is started by the end of the memory access, but since the operation has time margin, it is not necessary to make the rising of the signal BLEQ fast. As a result, the only P-channel MOSFET provided in the A-side cross area is the power MOSFET Q15 for overdrive.
P-channel type MOS provided in the cross area on the B side
The FET is an input / output line switch circuit IOS described below.
MOSFETs constituting a precharge circuit for precharging the MOSFETs Q24, Q25 constituting the W and the common input line MIO to the internal voltage VDL can be provided. And
Since these N-type well regions are supplied with a bias voltage such as the above-mentioned VDDCLP and VDL, they become one type of N-type well region, and no parasitic thyristor element is formed.

The unit circuit of the sense amplifier is connected to similar complementary bit lines BL and / BL of the right sub-array via shared switch MOSFETs Q3 and Q4. The switch MOSFETs Q12 and Q13 constitute a column switch circuit, and upon receiving the selection signal YS, connect the input / output node of the unit circuit of the sense amplifier to the sub-common input / output line LIO. For example, when the sub word line SWL of the left sub array is selected, the right shared switch MOSFETs Q3 and Q4 of the sense amplifier are selected.
Are turned off. As a result, the input / output node of the sense amplifier is connected to the left-side complementary bit lines BL and / BL, amplifies the minute signal of the memory cell connected to the selected sub-word line SWL, and passes through the column switch circuit. It is transmitted to the sub common input / output line LIO. The sub common input / output line is connected to the N side provided in the cross area on the B side.
It is connected to an input / output line MIO connected to the input terminal of the main amplifier via a switch circuit IOSW composed of channel type MOSFETs Q19 and Q20 and the P-channel type MOSFETs Q24 and Q25.

The sub-word line drive circuit SWD includes a P-channel MOSFET Q21 formed in the deep N-type well region DWELL (VPP), one of which is exemplarily shown as a representative. D
The P-type well region PWELL (V
N-channel MOSFET Q22 formed in BB)
And Q23. Inverter circuit N1
Although it is not particularly limited, it constitutes the sub-word select line driving circuit FXD as shown in FIG. 3 and is provided in the cross area as described above. The sub-array address selection MOSFET Qm is also
LL formed in the P-type well region PWELL (VB
B).

FIG. 6 is a schematic block diagram showing one embodiment of a peripheral circuit portion of a dynamic RAM according to the present invention. The timing control circuit TG receives a row address strobe signal / RAS, a column address strobe signal / CAS, a write enable signal / WE, and an output enable signal / OE supplied from external terminals, and determines an operation mode and responds to it. Thus, various timing signals necessary for the operation of the internal circuit are formed. In this specification and the drawings, the symbol / is used to mean that the low level is the active level.

Signals R1 and R3 are row-related internal timing signals, and are used for row-related selection operations.
The timing signal φXL is a signal for taking in and holding a row-related address, and is supplied to the row address buffer RAB. That is, the row address buffer RAB
Is controlled by the address signal A0 by the timing signal φXL.
ＡAi are fetched and held in the latch circuit. The timing signal φYL is a signal for taking in and holding the column address, and is supplied to the column address buffer CAB. That is, the column address buffer RAB fetches an address input from the address terminals A0 to Ai in response to the timing signal φYL and causes the latch circuit to hold the address.

The signal φREF is a signal generated in the refresh mode, and is supplied to the multiplexer AMX provided at the input of the row address buffer.
In the refresh mode, control is performed so as to switch to the refresh address signal formed by the refresh address counter circuit RFC. The refresh address counter circuit RFC counts a refresh step pulse φRC formed by the timing control circuit TG to generate a refresh address signal. In this embodiment, an auto refresh and a self refresh as described later are provided. The timing signal φX is a word line selection timing signal, and is supplied to the decoder XIB, and based on the decoded signal of the lower 2 bits of the address signal, there are four types of word line selection timing signals Xi.
B is formed. The timing signal φY is a column selection timing signal, and is supplied to the column predecoder YPD to output the column selection signals AYix, AYjx, AYkx.

The timing signal φW is a control signal for instructing a write operation, and the timing signal φR is a control signal for instructing a read operation. These timing signals φW and φR are supplied to the input / output circuit I / O to activate an input buffer included in the input / output circuit I / O at the time of a write operation, thereby bringing the output buffer into an output high impedance state. On the other hand, at the time of the read operation, the output buffer is activated, and the input buffer is set to the output high impedance state. Timing signal φM
S is a signal that instructs, but is not limited to, a memory array selection operation, is supplied to a row address buffer RAB, and a selection signal MSi is output in synchronization with this timing. Timing signal φSA is a signal for instructing the operation of the sense amplifier. An activation pulse for the sense amplifier is formed based on the timing signal φSA.

In this embodiment, the row-related redundant circuit XR
ED is illustratively shown as a representative. That is, the circuit X-RED includes a storage circuit for storing a defective address and an address comparison circuit. The stored defective address is compared with the internal address signal BXi output from the row address buffer RAB, and when they do not match, the signal XE is set to the high level, and the signal XEB is set to the low level to enable the operation of the normal circuit. When the input internal address signal BXi matches the stored defective address, the signal XE is set to low level to inhibit the operation of selecting the defective main word line of the normal circuit, and the signal XEB is set to high level to set one signal. A selection signal XRiB for selecting a spare main word line is output.

The internal voltage generating circuit VG receives the power supply voltage VDD such as 3.3 V supplied from an external terminal and the ground potential VSS of 0 V, and receives the boosted voltage VPP (+3.8
V), an internal step-down voltage VDL (+2.2 V), a plate voltage (precharge voltage) VPL (1.1 V) and a substrate voltage VBB (-1.0 V). Although not particularly limited, the boosted voltage VPP and the substrate voltage VBB stably form the voltages VPP and VBB using a charge pump circuit and its control circuit. The internal voltage VDL is formed by an internal step-down power supply circuit using the reference voltage VLR. The plate voltage VPL and the half precharge voltage are formed by dividing the internal step-down voltage VDL by half.

FIG. 7 is a circuit diagram showing one embodiment of a double boost type pumping circuit used in the boosted voltage circuit according to the present invention. MOSFE shown in FIG.
T is an N-channel MOSFET except for the MOSFET Q10 having a gate with an arrow, and only the MOSFET Q10 is a P-channel MOSFET. Also, the circuit symbols given to the respective circuit elements in FIG.
Although some overlap with those shown in FIG. 5 to avoid complicating the drawing, it should be understood that each has a separate circuit function.

The oscillating pulse OSC is equal to C
It is input to the MOS inverter circuit IN1. The above CMO
Between the output terminal of the S inverter circuit IN1 and the power supply voltage VDD, a capacitor C1 and a MOS as a switch element
An FET Q13 is provided. The above MOSFET Q13
Is connected to the gate and the drain to form a diode. That is, the MOSFET Q13 is turned on when the output signal of the inverter circuit IN1 is at a low level, and charges up the capacitor C1 to a voltage such as VDD-Vth (Vth is the threshold voltage of the MOSFET Q13). The oscillation pulse OSC is inverted by an inverter circuit IN2 to form a driving circuit M
It is supplied to the gate of OSFET Q12. This MOSF
The MOSFET Q12 is connected to the drain side of the ETQ12.
A MOSFET Q11 and a P-channel MOSFET Q10 constituting a drive circuit are connected in series, and a power supply voltage VDD is constantly applied to the gates of these MOSFETs Q10 and Q11. The above MOSFET
The operating voltage supplied to the sources of the 10 is a boosted voltage formed by the capacitor C3 as described later.

A capacitor C2 and a MOSFET Q1 as a switching element are provided between the output terminal of the drive circuit comprising the MOSFETs Q10 to Q12 and the internal step-down voltage VDL.
4 are provided. Although not limited, the MOSFET Q14 is switch-controlled by a boosted voltage formed by the capacitor C1. That is, the oscillation pulse O
When SC is at a low level, the output signal of the inverter circuit IN2 is set to a high level.
TQ12 is turned on, and the power supply voltage VD is applied to the gate.
MOSFE which is turned on when D is supplied
A low level output signal is supplied to the capacitor C2 by TQ11. At this time, the oscillation pulse OSC
, The output signal of the inverter circuit IN1 is turned to a high level, and the MOSFET Q14 is turned on by the boost voltage of the capacitor C1.
The capacitor C2 is charged up by the internal step-down voltage VDL.

The output signal of the inverter circuit IN2 is
It is supplied to the input of a CMOS inverter circuit IN3 as a drive circuit. A capacitor C3 and a MOSFET Q15 as a switch element are provided between the output terminal of the inverter circuit IN3 and the internal step-down voltage VDL. Although not limited, the MOSFET Q15 is switch-controlled by a boosted voltage formed by the capacitor C1. That is, when the oscillation pulse OSC is at a low level, the MOSFET Q 15
The output signal of N3 is set to a low level, and the output signal of the inverter circuit IN1 is turned on by a boosted voltage formed by the capacitor C1 according to the high level of the output signal,
The capacitor C3 is charged up to a voltage such as VDL.

The output signal of the inverter circuit IN3 is
It is supplied to an input of a CMOS inverter circuit IN5 as a drive circuit through a CMOS inverter circuit IN4 constituting a delay circuit. A capacitor C4 and a MOSFET Q16 as a switch element are provided between the output terminal of the inverter circuit IN5 and the power supply voltage VDD. The switch of the MOSFET Q16 is controlled by a boosted voltage formed by the capacitor C1. That is, M
When the oscillation pulse OSC is at a low level, the output signal of the inverter circuit IN5 is at a low level, and the OSFET Q16 is turned on by a boosted voltage formed by the capacitor C1 due to the high level of the output signal of the inverter circuit IN1. Then, the capacitor C4 is charged up to a voltage such as VDD. The boosted voltage formed by the capacitor C4 is the output MOSFE
It is output as boosted voltage VPP through TQ14. The gate of the MOSFET Q14 has the capacitor C
2 is supplied as a control signal.

During the period in which the immediately preceding oscillation pulse OSC is at the high level, the capacitor C1 is connected to VDD-Vth
The oscillation pulse OS
When C changes to low level, the inverter circuit IN
1 rises to the high level (VDD) of the output signal of 1, so that a boosted voltage such as 2VDD-Vth is formed by the capacitor C1, and the MOSFETs Q14, Q15 and Q16 are turned on. During the low level period of the oscillation pulse OSC, the output signal of the inverter circuit IN2 is at the high level, and the ground potential is supplied to the capacitor C2 by the on-state of the MOSFETs Q12 and Q11.

Therefore, when the MOSFET Q14 is turned on, the internal step-down voltage V
Charge-up is performed by DL. As described above, the low level of the oscillation pulse OSC causes the inverter circuit I
The output signal of N3 is also at the low level.
Also, charge-up is performed by the internal voltage VDL.
The output signal of the inverter circuit IN5 is also set to the low level due to the low level of the oscillation pulse OSC.
Due to the ON state of the switch MOSFET Q16, the capacitor C4 is charged up by the power supply voltage VDD.

Next, when the oscillation pulse OSC changes to high level, the capacitor C1 is charged up as described above, the output signal of the inverter circuit IN3 is set to high level (VDD), and VDD + VDDL is output by the capacitor C3. Is formed. Therefore, the above-mentioned voltage VDD + VDL is applied as the operating voltage to the source of the MOSFET Q10 of the drive circuit, and the gate voltage is set to a lower potential such as VDD with respect to the source voltage.
Is turned on to supply VDD + VDL to the capacitor C2.

Therefore, the boosted voltage formed by the capacitor C2 is a high voltage such as VDD + 2VDL, and turns on the output MOSFET Q17. In response to the change of the oscillation pulse OSC to the high level, the output signal of the inverter circuit IN5 is also set to the high level like the power supply voltage VDD.
A boosted voltage such as DD is formed, and a charge share occurs between the capacitor C4 and the output capacitance (parasitic capacitance) of the boosted voltage VPP through the output MOSFET Q17 which is turned on, and the VPP is switched to the sub-word line selecting operation. In addition, a current is supplied so as not to be reduced by a load current generated by the switching operation of the shared switch MOSFET.

The capacitors C1 to C4 are not particularly limited, but are N-channel MOSFETs formed in the N-type well, ie, depletion MOSFETs.
ET, which is composed of a MOS capacitance between the gate and the substrate (source, drain). On the other hand, each MOSFET except the P-channel MOSFET Q10
Represents an N-channel MOSF formed in a P-type well.
ET. In the above configuration, the maximum voltage is VDD + 2V
DL, so that VDD + 2VDL is applied to the gate of the output MOSFET Q17 and the switch M
The reliability can be ensured even when the gate insulating film of the OSFET Q14 is made thinner. For example, if the power supply voltage is 3.
Even if the voltage is increased to 3V or more and about 4V, 2VDL =
Since it is 4.4 V, the maximum voltage can be suppressed to about 8 V at most, and does not exceed 10 V unlike the conventional case.

The operating voltages of the above pumping circuits are all VD
If it is set to L, the boosted voltage output through the output MOSFET Q17 becomes 2VDL = 4.4V, and theoretically a boosted voltage VPP like the above 3.8V can be formed. However, the difference is only 0.6 V, and when the load current increases, the current supply capacity becomes insufficient. That is, C4 × 0.
Since only the charge amount of 6 can be supplied, it is necessary to increase the capacitance value of the capacitor C4 in order to obtain the necessary current supply capability, and the occupation area of the pumping circuit increases. On the other hand, as in the present invention, VDD and V
By combining with DL, the maximum voltage inside the double boost type pumping circuit is suppressed to VDD + 2VDL, thereby ensuring the necessary current supply capability.
Output MOSFET Q17, switch MOSFET Q14
The required reliability can be ensured even when the gate insulating film is made thinner.

The drive circuit including the MOSFETs Q10 to Q12 may be simply constituted by a CMOS inverter circuit. However, in the case of the configuration as in this embodiment,
When the boosted voltage VDD + VDL formed by the capacitor C3 is applied to the source of the MOSFET Q10 and transmitted to the capacitor C2 through the P-channel MOSFET Q10, the voltage is divided by the MOSFET Q11, and the drain of the MOSFET Q12 in the off state
Only a low voltage such as DD-Vth is applied. As a result, sufficient reliability can be ensured even when the thickness of the gate insulating film of the MOSFET Q12 is reduced. Also, MO
When the SFET Q12 is turned on to charge up the capacitor C2, the MOSFET Q10 can be turned off because the source potential of the MOSFET Q10 is lowered with respect to the gate voltage VDD like VDL. Thereby, MOSF
Since ETQ10 and Q12 can be switched complementarily, DC current can be prevented from flowing.

The above-described sub-word line is driven by the sub-word line driving circuit, and its substantial operating voltage is
The selection level of the sub-word line is set as the boosted voltage VPP as PP.
Or a shared switch MO
In a configuration where the boosted voltage is used also for the switch control of the SFET and VPP is used for controlling the overdrive of the sense amplifier SA, the boosted voltage VP
The load current of P becomes relatively large, and the pumping circuit needs to have a relatively large current supply capability.
The double boost type pumping circuit according to the present invention can sufficiently cope with this.

In the configuration in which the boosted voltage VPP is supplied to the well region DWELL having a deep depth as described above, a relatively large parasitic capacitance exists between the DWELL and the P-type substrate. Therefore, as a capacitor provided on the output side of the pumping circuit and holding the boosted voltage VPP,
The parasitic capacitance of the DWELL can be utilized, and VP
It is possible to stabilize P and reduce the area occupied by the pumping circuit.

FIG. 8 is a block diagram showing one embodiment of the internal voltage generating circuit according to the present invention. The internal voltage generating circuit of this embodiment has a dynamic R
It is mounted on the AM and includes an internal step-down circuit and a step-up voltage circuit. The reference voltage generation circuit forms a reference constant voltage VREF using a silicon band gap. The step-down circuit uses the reference voltage VREF to step down the power supply voltage VDD and reduce the internal voltage VDL such as 2.2V.
To form The voltage VDL is used as the operating voltage of the sense amplifier as described above, the high level of the bit line is determined, and is also used as the operating voltage of a part of the pumping circuit.

The selection level of the word line (sub-word line) may be a boosted voltage corresponding to the threshold voltage of the address selection MOSFET with respect to the high level VDL of the bit line. Receiving
A voltage obtained by adding a threshold voltage to the reference voltage is used as a reference voltage.
In the PP level sensor, the voltage is compared with the boosted voltage VPP. In the VPP level sensor, when the difference VPP-VDL between VPP and VDL is equal to or greater than a set value (threshold voltage Vth of MOSFET), a high-level output signal is formed, and the difference VPP-VDL is generated. Is lower than the set value, a low-level output signal is formed. This sensor output is supplied to the oscillator through the AND gate circuit G1.

The oscillator stops the oscillating operation when the output VEN of the AND gate circuit G1 is at a high level, and performs the oscillating operation when the output VEN is at a low level. Therefore, when the boosted voltage VPP is a desired boosted voltage, the oscillation operation is stopped and no further boosting operation is performed. When the boosted voltage VPP falls below the desired boosted voltage, the oscillator starts oscillating. The above boosted voltage VP
P is raised to the desired high voltage. The high-voltage detection circuit forms a high-level output signal when the power supply voltage VDD is a normal voltage. Therefore, the output VEN
Is changed according to the output of the VPP level sensor to stabilize the boosted voltage VPP.

The high-voltage detection circuit forms a low-level output signal in an aging mode in which the power supply voltage VDD is higher than a standard operating voltage (for example, 3.3 V ± 10%). As a result, the output of the VPP level sensor is invalidated, and the oscillator steadily oscillates, and the VPP generation circuit sets the upper limit of the boosted voltage corresponding to twice the power supply voltage VDD accordingly. It operates so that the boosting operation is performed constantly. Thereby, aging (burn-in) can be performed efficiently in a short time.

FIG. 9 is a schematic block diagram showing another embodiment of a dynamic RAM to which the present invention is applied. This embodiment is directed to a large storage capacity such as 256 Mbits. That is, one memory array (Array) has a storage capacity such as 16 Mbits, and the memory array (Array) has a set of four such that a main word driver (Main Word) and a Y driver (Ydec) are sandwiched therebetween. As four sets. One memory array is one
Since it has a storage capacity of 6 Mbits, 4 × 4 × 16 = 25
It has a large storage capacity such as 6M bits. The one memory array (Array) has the same configuration as the one array in FIG. However, since the sub-array is composed of 512 pairs of complementary bit lines, a storage capacity such as 16 Mbits can be obtained by the same sub-array configuration.

The operational effects obtained from the above embodiment are as follows. That is, (1) In a double boost type pumping circuit,
The boost voltage transmitted to the input side of the output MOSFET is a boost voltage that is twice the power supply voltage.
The boost voltage as a switch control signal supplied to the gate of the OSFET is a boosted voltage obtained by combining the above-mentioned power supply voltage and twice the internal step-down voltage.
Even when the gate insulating film of the OSFET is thinned, an extremely high voltage is not supplied with an increase in the power supply voltage, so that the required reliability can be secured.

(2) The first switch element is a diode-type MOSFET, and the second and third switch elements are switch MOSFETs that are turned on by a boosted voltage formed by the first capacitor. Thus, an effect is obtained that an efficient boosting operation can be performed.

(3) As the second drive circuit, a P-channel type MO whose gate is constantly connected to the power supply voltage is used.
An SFET, a first N-channel MOSFET, and a second N-channel provided between the source of the first N-channel MOSFET and the ground potential of the circuit, the gate of which the periodic pulse signal is supplied. Type MOSFET, the second output terminal is the P-channel type MOS
By obtaining the voltage from the connection point between the FET and the first N-channel MOSFET, it is possible to prevent a through current in the drive circuit and to suppress the voltage applied to the second N-channel MOSFET to a low level, thereby achieving high reliability. The effect that the property can be ensured is obtained.

(4) Addresses of a plurality of dynamic memory cells which are divided in the length direction of the main word line and are arranged in a plurality of bit line directions intersecting the main word line. A sub-word line to which a selection terminal is connected and a selection signal extending to be parallel to the main word line and selecting one of a plurality of sub-word lines assigned to the one main word line are transmitted. A first sub-word selection line, a second sub-word selection line connected to a corresponding one of the first sub-word selection lines, and extended so as to be orthogonal to the main word line; and a selection signal for the main word line. And a selection signal transmitted through the second sub-word selection line to form a selection signal for the sub-word line. And a plurality of complementary bit line pairs arranged so as to be orthogonal to the plurality of sub-word lines and having the input / output terminal of the dynamic memory cell connected to one of the sub-word lines, and the plurality of complementary bit lines. By applying the present invention to a booster circuit of a dynamic RAM having a plurality of sense amplifiers each having an input / output terminal connected to a pair, a thin film of a gate insulating film accompanying a large storage capacity or high integration of such a dynamic RAM. As a result, it is possible to obtain a boosted voltage having a current supply capability necessary for its stable operation while ensuring the reliability required for the operation.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention of the present application is not limited to the embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say. The booster circuit is
A booster circuit having no current supply capability enough to compensate for the leakage current may be separately provided so that it operates constantly. The configuration of the sub-array constituting the dynamic RAM to which the present invention is applied or the arrangement of a plurality of memory arrays mounted on a semiconductor chip can employ various embodiments according to the storage capacity and the like.
In addition, the configuration of the sub-word driver can employ various embodiments. The input / output interface part is
A synchronous dynamic RAM which operates in synchronization with a clock signal may be used. The present invention can be widely used for a semiconductor integrated circuit device provided with a boosted voltage raised to a power supply voltage supplied from an external terminal, in addition to the dynamic RAM.

[0088]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in the double boost type pumping circuit, the boost voltage transmitted to the input side of the output MOSFET is a boost voltage that is twice the power supply voltage, and the boost voltage as the switch control signal supplied to the gate of the output MOSFET is By increasing the boost voltage by combining the power supply voltage and the double internal step-down voltage, the output MOS can be secured while maintaining the necessary current supply capability.
Even when the gate insulating film of the FET or the switch MOSFET is made thinner, an extremely high voltage is not supplied with an increase in the power supply voltage, so that necessary reliability can be secured.

[Brief description of the drawings]

FIG. 1 is a layout diagram showing one embodiment of a dynamic RAM including a boosted voltage circuit according to the present invention.

FIG. 2 is a schematic layout diagram for explaining the dynamic RAM of FIG. 1;

FIG. 3 is a schematic layout diagram showing one embodiment of a sub-array and its peripheral circuits in the dynamic RAM of FIG. 1;

FIG. 4 is a schematic layout diagram showing one embodiment of a well region for forming a sub-array and its peripheral circuits in the dynamic RAM of FIG. 1;

FIG. 5 is a main part circuit diagram showing one embodiment of a sense amplifier section and peripheral circuits of the dynamic RAM of FIG. 1;

FIG. 6 is a schematic block diagram showing one embodiment of a peripheral circuit portion of the dynamic RAM of FIG. 1;

FIG. 7 is a circuit diagram showing one embodiment of a double boost type pumping circuit according to the present invention.

FIG. 8 is a block diagram showing one embodiment of an internal voltage generation circuit according to the present invention.

FIG. 9 is a schematic block diagram showing another embodiment of a dynamic RAM to which the present invention is applied.

[Explanation of symbols]

10: memory chip, 11: main row decoder area,
12: Main word driver area, 13: Column decoder area, 14: Peripheral circuit, bonding pad area, 1
5 ... Meseri cell array (sub array), 16 ... Sense amplifier area, 17 ... Sub word driver area, 18 ... Intersection area (cross area), 19 ... Internal voltage generation circuit, SA
... sense amplifier, SWD ... sub-word driver, MWD
... Main word driver, CTRL ... Memory array control circuit, MWL0 to MWLn ... Main word line, SW
L, SWL0: sub word line, YS: column select line, S
BARY: sub-array, TG: timing control circuit, I
/ O: input / output circuit, RAB: row address buffer, C
AB: column address buffer, AMX: multiplexer, RFC: refresh address counter circuit, XP
D, YPD: Pretecoder circuit, X-DEC: Row system redundant circuit, XIB: Decoder circuit, Q1 to Q25: MOS
FET, CSP, CSN: common source line, YS: column select signal, LIO: sub common input / output line, MIO: common input / output line, IN1 to IN5: CMOS inverter circuit, C
1 to C4: capacitors.

 ──────────────────────────────────────────────────の Continued on the front page (72) Inventor Akimitsu Mimura 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. In company

Claims (4)

[Claims] A first driving circuit configured to receive a periodic pulse signal and operate on a power supply voltage; and a first driving circuit having one end connected to an output terminal of the first driving circuit.
And between the other end of the first capacitor and the power supply voltage, and from the power supply voltage to the other end of the first capacitor when the output signal of the first drive circuit is at a low level. A first switch element configured to allow current to flow therethrough, a second drive circuit receiving a periodic pulse, and a second drive circuit having one end connected to an output terminal of the second drive circuit.
And an internal step-down voltage formed by stepping down the power supply voltage, and the second drive circuit is turned on when the output signal of the second drive circuit is at a low level. A second switch element configured to charge up the second capacitor by the internal step-down voltage; a third drive circuit configured to receive a periodic pulse signal and to operate at the power supply voltage; The third terminal having one end connected to the output terminal of the third driving circuit
And an internal step-down voltage that is formed by stepping down the power supply voltage, and is turned on when the output signal of the third drive circuit is at a low level. A third switch element for charging up the third capacitor with the internal step-down voltage, a fourth drive circuit receiving a periodic pulse signal and operating with the power supply voltage, The fourth terminal having one end connected to the output terminal of the fourth driving circuit
And a second capacitor provided between the other end of the fourth capacitor and the power supply voltage, and turned on by a boosted voltage formed by the first capacitor. A fourth switch element for charging up, and an output MOSFET for outputting a boosted voltage formed by the fourth capacitor through a switch MOSFET that is switch-controlled by the boosted voltage formed by the second capacitor, The second drive circuit uses a boosted voltage formed by the third capacitor as an operation voltage, the first drive circuit forms an output signal corresponding to the periodic pulse, and And the third drive circuit form an output signal corresponding to the periodic pulse and having a phase opposite to that of the output signal of the first drive circuit, and The fourth drive circuit corresponds to the periodic pulse, forms an output signal at the same phase as the output signals of the second and third drive circuits and at a delayed timing, and supplies the power supply voltage through the output MOSFET. 1. A semiconductor integrated circuit device comprising a boosted voltage generation circuit for generating a boosted voltage with respect to a semiconductor integrated circuit. 2. The first switch element is a MOSFET in the form of a diode, and the second and third switch elements are switch MOSFETs that are turned on by a boosted voltage formed by the first capacitor. 2. The semiconductor integrated circuit device according to claim 1, wherein 3. The second drive circuit includes a P-channel MOSFET and a first N-channel MOSFET whose gates are constantly connected to a power supply voltage, and a source and a circuit of the first N-channel MOSFET. And a second N-channel MOSFET whose periodic pulse signal is supplied to the gate thereof. The second output terminal is connected to the P-channel MOSFET and the first N-channel MOSFET. 3. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is obtained from a connection point of a type MOSFET. 4. A plurality of dynamic word lines each having a length divided in a direction in which the main word line extends and a plurality of dynamic word lines arranged in a bit line direction intersecting the main word line. A sub-word line connected to an address selection terminal of the type memory cell; and a sub-word line extending in parallel with the main word line.
A first sub-word selection line to which a selection signal for selecting one of a plurality of sub-word lines assigned to one main word line is transmitted; and a first sub-word selection line corresponding to the first sub-word selection line, A second sub-word select line extending orthogonal to the word line; a main word line select signal and a select signal transmitted through the second sub-word select line; A plurality of sub-word line driving circuits, and a plurality of complementary bit line pairs arranged so as to be orthogonal to the plurality of sub-word lines and having the input / output terminal of the dynamic memory cell connected to one of them. And a plurality of sense amplifiers each having an input / output terminal connected to the plurality of complementary bit line pairs. 4. The sub-word line driving circuit according to claim 1, wherein the sub-word line driving circuit sets the sub-word line to a selection level corresponding to the boosted voltage. Semiconductor integrated circuit device.