JPH1174467A - Capacitance element and manufacturing thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent characteristic deterioration caused by titanium and others, which constitute electrode wiring contacting to the upper electrode of a capacitance element, invade capacitor insulation film and react. SOLUTION: On a substrate 1, a lower electrode 2, a capacitor insulation film 3, an insulation film 5 for coating, and the first partial film 7a on an upper electrode 7 which fills the second opening 6 (an opening for regulating capacitance) which is formed in the insulation film 5. A capacitor element is composed of the lower electrode 2, the capacitor insulation film 3, and the first partial film 7a. The upper electrode 7 includes the first partial film 7a which contacts a capacitor insulation film 5, and the second partial film 7b which does not contact the film 5. The second electrode wiring 11, having a lower film 11a of titanium and an upper film 11b of aluminum alloy, contacts the second partial film 7b away from the first partial film 7a of the upper electrode 7. The diffusion of the titanium and others which invade from the second electrode wiring 11 to the capacity insulation film 5 can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a capacitive element using a dielectric or ferroelectric having a high dielectric constant as a capacitive insulating film, and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, as the speed of microcomputers and the like and the power consumption have been reduced, the performance of consumer electronic devices has further increased, and the miniaturization of semiconductor elements of semiconductor devices used therein has been rapidly advanced. Is coming. At the same time, unnecessary radiation, which is electromagnetic noise generated by electronic equipment, is a major problem. As a measure to reduce this unnecessary radiation, a dielectric having a high dielectric constant (hereinafter simply referred to as a high dielectric) is used as a capacitive insulating film. Attention has been paid to a technology for incorporating a capacitive element into a semiconductor integrated circuit device or the like. Also, with the high integration of the dynamic RAM, a technique of using a high dielectric film instead of a silicon oxide film or a silicon nitride film conventionally used as a capacitor insulating film has been widely studied. Further, research and development on ferroelectric films having spontaneous polarization characteristics have been actively conducted in order to realize a non-volatile RAM capable of low operating voltage and high speed writing / high speed reading.

In order to realize a semiconductor device having the above performance, it is necessary to develop a structure of a capacitive element for realizing high integration without deteriorating the characteristics of the capacitive element and a method of manufacturing the same. It is important.

Hereinafter, a conventional capacitor and a method for manufacturing the same will be described with reference to the drawings. FIG. 9 is a cross-sectional view showing a main part of a conventional capacitive element. Reference numeral 21 denotes a substrate such as a silicon substrate on which an integrated circuit is formed. 2
Numeral 2 denotes a lower electrode of a capacitive element formed of a platinum film or the like; 23, a capacitive insulating film of the capacitive element formed of a ferroelectric thin film;
Is an upper electrode of a capacitive element formed of a platinum film or the like, and the lower electrode 22, the upper electrode 24, and the capacitive insulating film 23 constitute a capacitive element. 25 is a capacitive insulating film 24
26 is an interlayer insulating film covering the capacitive element,
Reference numeral 27 denotes a first contact hole that penetrates through the interlayer insulating film 26 and reaches the lower electrode 22, 28 denotes a second contact hole that penetrates the interlayer insulating film 26 and reaches the upper electrode 24, and 29 denotes a connection with the lower electrode 22. A first electrode wiring 30 is a second electrode wiring connected to the upper electrode 24.

Recently, these electrode wirings 29, 30
Is a two-layer laminated film in which the lower layer is composed of a titanium film and the upper layer is composed of an aluminum alloy film containing aluminum as a main component, or the lower layer is composed of a titanium film, the intermediate layer is composed of a titanium nitride film, and the upper layer is mainly composed of aluminum. It is composed of a three-layer laminated film made of an aluminum alloy film as a component.
In particular, when such a capacitive element is incorporated in an integrated circuit, the first and second electrode wirings 29 and 30 are directly connected to the diffusion region of the integrated circuit. In order to lower the contact resistance, a titanium film is generally used for the lowermost layer of the laminated film.

Next, a conventional method for manufacturing a capacitive element will be described. 10 (a) to 10 (e) are cross-sectional views showing the steps of manufacturing a conventional capacitive element.

First, in the step shown in FIG.
A first platinum film 22a, a ferroelectric film 23a, and a second platinum film 24a are sequentially formed on 1. Next, FIG.
In the process shown in (1), the upper electrode 24 is formed by patterning the second platinum film 24a using a photoresist mask. Next, in a step shown in FIG. 10C, the dielectric film 23a is patterned using a photoresist mask covering a region including the upper electrode 24 to form the capacitor insulating film 23 having the opening 25. Further, the upper electrode 24, the capacitor insulating film 2
The lower electrode 22 is formed by selectively etching the first platinum film 22a using a photoresist mask covering the openings 3 and the openings 25 thereof.

Next, in a step shown in FIG. 10D, after an interlayer insulating film 26 is formed on the substrate, a first contact hole 27 penetrating through the interlayer insulating film 26 and reaching the lower electrode 22;
A second contact hole 28 penetrating through the interlayer insulating film 26 and reaching the upper electrode 24 is formed.

Next, in a step shown in FIG. 10E, after a titanium film and an aluminum alloy film are deposited on the entire surface of the substrate, the titanium film is formed using a photoresist mask covering the contact holes 27 and 28 and the periphery thereof. The film and the aluminum alloy film are patterned to form a first electrode wiring 29 connected to the lower electrode 22 and a second electrode wiring 30 connected to the upper electrode 24.

In FIG. 10E, the first electrode wiring 29 and the second electrode wiring 30 are illustrated as if they were a single layer for simplicity. In general, it is composed of a two-layer laminated film composed of a titanium film and an aluminum alloy film, or a three-layer laminated film composed of a titanium film, a titanium nitride film and an aluminum alloy film.

[0011]

By the way, in the above-mentioned conventional capacitance element, the second electrode wiring 30 and the upper electrode 2
4 is required to have good adhesion. Since a metal oxide-based ferroelectric is generally used as the capacitor insulating film 23, a platinum film is used as the lower electrode 22 and the upper electrode 24 as a material that does not react with the metal oxide during heat treatment and withstands high temperatures. Can be In addition, since the adhesion between the aluminum layer and the platinum film layer is not very good as the electrode wirings 29 and 30, a titanium layer is interposed between them to strengthen the connection between the electrode wiring and the electrode of the capacitor. I have.

Here, in order to improve the performance of the capacitive element, a heat treatment or the like after forming the electrode wirings 29 and 30 in the manufacturing process is indispensable. Is performed, the performance of the ferroelectric film constituting the capacitive insulating film 23 is reduced.

Then, as a result of investigating the cause, it was presumed that the cause was as follows. That is, since the platinum films constituting the upper electrode 24 and the lower electrode 22 of the capacitor are usually formed by sputtering, they have a columnar crystal structure. Then, during the heat treatment of the electrode wirings 29 and 30, the second
Forming the lower layer of the electrode wiring 30 of the upper electrode 24
Is diffused into the capacitor insulating film 23 through the crystal grain boundaries of the platinum film of the columnar crystal constituting the columnar crystal, and reacts with the ferroelectric film forming the capacitor insulating film 23.

The above-mentioned problem may occur not only when each electrode of the capacitive element is made of a platinum film but also when it is made of iridium, palladium, ruthenium, or the like. Further, like the storage node of a memory cell transistor of a DRAM, even if the lower electrode is made of a polysilicon film, the same problem occurs when the upper electrode is made of platinum or the like.

The present invention has been made in view of the above point, and an object of the present invention is to realize a structure in which a metal constituting an electrode is not diffused to a capacitor insulating film, thereby providing a structure between an upper electrode and an electrode wiring. It is an object of the present invention to provide a capacitive element capable of reliably preventing the deterioration of the characteristics of a capacitive insulating film while maintaining a strong adhesiveness, and a method for manufacturing the same.

[0016]

Means for Solving the Problems In order to achieve the above object, a means taken by the present invention is to form an upper electrode so that a part of the upper electrode does not contact a capacitive insulating film, and to form an upper electrode on a part thereof. The electrode and the electrode wiring are connected.

The capacitive element of the present invention comprises a substrate, a lower electrode made of a conductive film formed on the substrate, a capacitive insulating film formed on the lower electrode, and a metal material. An upper electrode having a first partial film in contact with the upper surface of the capacitive insulating film and a second partial film not in contact with the capacitive insulating film, an interlayer insulating film covering at least the upper electrode, and penetrating the interlayer insulating film And a contact hole reaching the second partial film in the upper electrode, and an electrode wiring which fills at least the contact hole and is connected to the upper electrode.

Thus, since the upper electrode and the electrode wiring are connected in the second partial film not in contact with the capacitive insulating film, the material constituting the electrode wiring during the heat treatment in the manufacturing process is changed to the first material in the upper electrode. Invasion of the capacitor insulating film from the partial film is prevented as much as possible.

In the capacitive element, a region which does not overlap with the capacitive insulating film when viewed in plan is provided in the second partial film of the upper electrode, and the electrode wiring is formed in the second partial film.
In the partial film, a region not overlapping with the capacitive insulating film can be connected to the upper electrode.

As a result, the distance between the second partial film and the capacitive insulating film is increased, so that the material forming the electrode wiring during the heat treatment in the manufacturing process is changed from the first partial film in the upper electrode to the capacitive insulating film. Will be more reliably prevented from entering.

In the above-mentioned capacitive element, the upper electrode is formed so as to be in contact with only a part of the capacitive insulating film, and at least one region of the capacitive insulating film which is not in contact with the upper electrode is formed. An underlay insulating film that covers a portion of the upper electrode, wherein the second partial film of the upper electrode is provided with a region that overlaps with the capacitive insulating film when viewed in plan on the underlay insulating film; Wiring the second
Of the partial film may overlap with the upper electrode in a region overlapping with the capacitor insulating film when viewed in plan.

As a result, the area occupied by the entire capacitor can be reduced, and the capacitor can be miniaturized.

In the above capacitive element, the capacitive insulating film is formed so as to have substantially the same outer peripheral shape as the lower electrode, and an insulator formed on the side surface of the outer peripheral portion of the capacitive insulating film and the lower electrode is formed. Side walls may be further provided.

Thus, the first partial film and the second partial film of the upper electrode are continuously formed in the longitudinal section while drawing a smooth curve from the portion over the capacitor insulating film to the portion over the insulator sidewall. Therefore, occurrence of defects due to disconnection of the metal film forming the upper electrode at the end of the capacitor insulating film is suppressed.

In the above capacitive element, a capacitance value defining insulating film covering a region along the outer periphery of the capacitive insulating film; and a main part of the capacitance value defining insulating film excluding a region along the outer periphery of the capacitive insulating film. An opening for defining a capacitance value formed in a region located above the region may be further provided, and the first partial film of the upper electrode may be formed in the opening for defining a capacitance value.

Thus, the region near the outer periphery of the capacitive insulating film, which is easily affected by peripheral members, does not function as a part of the capacitive element, so that the characteristics of the capacitive element can be maintained particularly well and an accurate capacitance value can be obtained. Can be

It is preferable that the metal material forming the upper electrode contains at least one of platinum, iridium, palladium and ruthenium.

Further, it is preferable that the upper electrode is formed by laminating at least any two of a platinum film, an iridium film, a palladium film and a ruthenium film.

It is preferable that the upper electrode has a columnar crystal structure perpendicular to the underlying surface.

Since there is no crystal grain boundary extending in the direction parallel to the film surface in the metal film forming the upper electrode, the material forming the electrode wiring diffuses from the first partial film through the metal film. As a result, it is possible to reliably prevent the second partial film from reaching the second partial film and further penetrating into the capacitive insulating film.

The capacitor insulating film is composed of a first oxide mainly containing one of strontium, bismuth and tantalum and a second oxide mainly containing one of lead, zircon and titanium. And the composite of the first and second oxides described above.

This suppresses the generation of unnecessary radiation from the electronic equipment on which the capacitive element is mounted, and has a large area with a small area even when the capacitive element is disposed in a memory cell of a DRAM or a nonvolatile RAM. Thus, a capacitive element having a capacity can be obtained.

A first method of manufacturing a capacitive element according to the present invention comprises a first step of sequentially forming a conductor film and a dielectric film on a substrate, and patterning the conductor film and the dielectric film to form a lower electrode and a lower electrode. A second step of forming a capacitance insulating film, a third step of forming a metal film for an upper electrode on a substrate, and a step of patterning the metal film for an upper electrode to contact an upper surface of the capacitance insulating film. A fourth electrode forming an upper electrode having a first partial film and a second partial film not in contact with the capacitive insulating film;
A fifth step of forming an interlayer insulating film on the substrate, a sixth step of forming a contact hole penetrating through the interlayer insulating film and reaching the second partial film of the upper electrode, After a metal film for wiring is deposited thereon, it is patterned to fill the contact hole and fill the second electrode of the upper electrode.
Forming an electrode wiring connected to the partial film.

In the first method of manufacturing a capacitive element,
In the second step, the conductor film and the dielectric film are etched using a common mask member to form a lower electrode and a capacitor insulating film having substantially the same outer peripheral shape, and a sidewall insulating film is formed on the substrate. After depositing the film, the method further comprises a step of performing anisotropic etching to form an insulator sidewall on an end face of an outer peripheral portion of the capacitive insulating film and the lower electrode. A second partial film can be formed in a region on the substrate including over the insulator sidewall.

According to a second method of manufacturing a capacitive element of the present invention, a first step of sequentially forming a conductor film and a dielectric film on a substrate, and patterning the conductor film and the dielectric film to form a lower electrode and A second step of forming a capacitive insulating film, a third step of forming an underlying insulating film on a substrate, and partially removing the underlying insulating film to expose a portion of the capacitive insulating film A fourth step of forming, a fifth step of forming a metal film for an upper electrode on a substrate, and patterning the metal film for an upper electrode to form a capacitor insulating film on an exposed region of the capacitor insulating film. A sixth step of forming an upper electrode having a first partial film in contact with the upper surface of the film and a second partial film on the underlying insulating film, and forming an interlayer insulating film on the substrate A seventh step, a second portion of the upper electrode penetrating the interlayer insulating film; An eighth step of forming a contact hole reaching the contact hole, and depositing a wiring metal film on the substrate and then patterning the metal film to fill the contact hole and connect to the second partial film of the upper electrode. A ninth step of forming an electrode wiring.

In the second method of manufacturing a capacitive element,
In the fourth step, a capacity defining opening is formed by removing a region located above a main region excluding a region near the outer periphery of the capacitor insulating film in the underlaying insulating film, thereby forming a capacitor defining opening. Then, the second partial film of the upper electrode can be formed in the capacitance defining opening.

In the method of manufacturing a capacitive element, in the sixth step, the second partial film of the upper electrode can be formed on a region of the substrate that does not overlap with the capacitive insulating film.

In the second method of manufacturing a capacitive element,
In the sixth step, the second partial film of the upper electrode is formed by:
It can be formed on the underlying insulating film in a region overlapping with the capacitive insulating film.

By the above-described first and second manufacturing methods of the capacitive element, a capacitive element having a capacitive insulating film not in contact with the second partial film of the upper electrode in contact with the electrode wiring is formed. Therefore, it is possible to provide a method for manufacturing a capacitor having a function of preventing a material constituting a metal film for electrode wiring from entering a capacitor insulating film.

In the first and second methods of manufacturing a capacitive element, the step of forming the upper electrode metal film is preferably performed by sputtering.

According to this method, the first partial film and the second partial film of the upper electrode are formed of a metal film having a columnar crystal structure extending in a direction perpendicular to the film surface. There is no crystal grain boundary extending in a direction parallel to the film surface in the film, and a capacitance element capable of reliably preventing the material constituting the metal film for electrode wiring from invading into the capacitance insulating film is easily formed. be able to.

[0042]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) FIGS. 1 and 2 are a sectional view and a plan view, respectively, showing a main part of a capacitive element according to a first embodiment of the present invention. However, in FIG. 2, it is assumed that there is no interlayer insulating film and no electrode wiring. A lower electrode 2 is formed on a substrate 1 (such as a silicon substrate), and a capacitance insulating film 3 is formed on the lower electrode 2. A first opening 4 reaching the lower electrode 2 is formed in the capacitor insulating film 3. Further, a covering insulating film 5 is formed on the capacitive insulating film 3, and a second opening 6 (capacitance value defining opening) reaching the capacitive insulating film 3 is formed in the covering insulating film 5. Have been. Then, a first partial film 7a of the upper electrode 7 filling the inside of the second opening 6 is formed. The lower electrode 2, the capacitor insulating film 3, and the first
The partial film 7a constitutes an MIM-type capacitive element. The insulating film 5 for covering in the present embodiment functions as a capacitance value defining insulating film that defines the capacitance of the capacitive element.

On the insulating film 5 for coating, the first partial film 7a in the second opening 6 is connected to and extends.
A second partial film 7b of the upper electrode 7 formed in a region not in contact with the capacitance insulating film 3 is provided. In particular, in the present embodiment, the second partial film 7b has a region which does not overlap with the capacitance insulating film when viewed in plan. On the first partial film 7a and the second partial film 7b, an interlayer insulating film 8 covering the entire substrate is formed, and the interlayer insulating film 8 and the coating in the first opening 4 are formed. Contact hole 9 that reaches lower electrode 2 through insulating film 5 for use
a and a second contact hole 9b penetrating through the interlayer insulating film 8 and reaching a region of the second partial film 7b that does not overlap with the capacitive insulating film when viewed in plan. Further, a first electrode wiring 10 is provided in the first contact hole 9a and on the interlayer insulating film 8 around the first contact hole 9a, and is provided on the interlayer insulating film 8 in the second contact hole 9b and around the same. The second electrode wiring 11 is provided. The first and second electrode wirings 10 and 11 are respectively composed of lower films 10a and 11a made of titanium and upper films 10b and 11b made of an aluminum alloy film. I have.

Therefore, in the capacitive element of this embodiment, the second electrode wiring 11 is connected to a region of the second partial film 7b of the upper electrode 7 which does not overlap with the capacitive insulating film when viewed in plan. It will be.

Next, the steps of manufacturing the capacitor having the structure shown in FIGS. 1 and 2 will be described. FIG.
FIG. 3F is a cross-sectional view illustrating a step of manufacturing the capacitor in the first embodiment.

First, in the step shown in FIG. 3A, a first metal film 2a and a dielectric film 3a are formed on the main surface of the substrate 1.

Next, in a step shown in FIG. 3B, the dielectric film 3a is selectively etched to form the first metal film 2a.
A first opening 4 reaching a is formed. Next, the first metal film 2a and the dielectric film 3a are patterned by etching using a photoresist mask (not shown) covering the capacitive element formation region including the first opening 4, and the lower electrode 2 and the The capacitance insulating film 3 is formed.

Next, in the step shown in FIG. 3C, after depositing the covering insulating film 5 on the substrate, the covering insulating film 5 exposes the region of the capacitive insulating film 3 excluding the region near the outer periphery. A second opening 6 to be formed is formed.

Next, in the step shown in FIG. 3D, after depositing a second metal film (metal film for an upper electrode, not shown) on the substrate by sputtering, the second metal film is patterned. Then, the first partial film 7 filling the second opening 6
a and a second partial film which is connected to the first partial film 7a and extends to a region not in contact with the capacitive insulating film 3 and not overlapping with the capacitive insulating film 3 when viewed planarly on the substrate 1. 7b.

Next, in a step shown in FIG. 3E, after depositing an interlayer insulating film 8 on the substrate, a first electrode reaching the lower electrode 2 through the interlayer insulating film 8 and the covering insulating film 5 is formed. A contact hole 9a and a second contact hole 9b penetrating through the interlayer insulating film 8 and reaching the second partial film 7b are formed.

Next, in a step shown in FIG. 3F, after a titanium film and an aluminum alloy film are sequentially deposited on the substrate, both are patterned to form a first electrode for filling the first contact hole 9a. A wiring 10 and a second electrode wiring 11 filling the second contact hole 9b are formed.
That is, the lower films 10a and 11a made of a titanium film and the first and second electrode wirings 10 and 11 made of the upper films 10b and 11b made of an aluminum alloy film are formed.

In this embodiment, FIG.
In the step shown in FIG. 3, the first opening 4 is formed in the capacitive insulating film 3, but here, only the patterning of the outer periphery of the capacitive insulating film 3 and the lower electrode 2 is performed, and in the step shown in FIG. A first contact hole 9a penetrating the insulating film 8, the covering insulating film 5, and the capacitive insulating film 3 may be formed.

When this capacitor is formed in an integrated circuit, the first electrode wiring 10 and the second electrode wiring 11 constitute a part of a wiring layer of the integrated circuit.
It is formed in the same process as the wiring layer.

According to the present embodiment, the upper electrode 7 includes the first partial film 7 a in contact with the capacitor insulating film 3 and the capacitor insulating film 3.
And the second partial film 7b which is not in contact with the second electrode film 11b.
Is in contact. Therefore, the second electrode wiring 1
1 constituting the second partial film 7b of the upper electrode 7
However, it is difficult for titanium or the like to diffuse into the upper electrode 7 from the second partial film 7b to the first partial film 7a and reach the capacitive insulating film 3 during the heat treatment. It is possible to prevent the performance of the capacitive insulating film 3 from deteriorating due to the reaction between the ferroelectric material and the like.

In particular, in the case of the structure shown in FIGS. 1 and 2 of this embodiment, the second partial film 7b has a region which does not overlap with the capacitance insulating film 3 in plan view. 2
Of the second partial film 7b is in contact with a region of the second partial film 7b that does not overlap with the capacitive insulating film 3 when viewed in plan. Therefore, the second in the upper electrode 7
It is easy to make the distance between the contact portion with the electrode wiring 11 and the contact portion with the capacitive insulating film 3 sufficiently long, and the function of preventing entry into the capacitive insulating film 3 of titanium or the like as described above is large. There is an advantage that the upper electrode 7 can be obtained.

Further, as in the present embodiment, the first partial film 7a is formed in the second opening 6, which is the opening for defining the capacitance value, so that the peripheral member of the capacitive insulating film 3 is affected. Since the region near the outer periphery which does not easily function as a capacitance film, the characteristics of the capacitance element are favorably maintained, and it is easy to obtain an accurate capacitance value as designed.

In the present embodiment, the metal film constituting the lower electrode 2 and the upper electrode 7 can be constituted by a single layer film of platinum, iridium, palladium or ruthenium or an alloy film composed of two or more of them. Alternatively, a stacked film of two or more of a platinum film, an iridium film, a palladium film, and a ruthenium film may be used. However,
As described later, the first metal film 2a does not necessarily have to be a metal film such as platinum, but may be a polysilicon film.

In particular, when the second metal film 7 is a metal film such as platinum formed by sputtering, the second metal film 7 has a columnar crystal structure extending in the vertical direction. There will be almost no grain boundaries. However, since the diffusion of titanium is mainly performed through the crystal grain boundaries, titanium or the like that has entered the second partial film 7b from the second electrode wiring 11 diffuses in the lateral direction to the first partial film 7a. Thus, it hardly reaches, so that deterioration of the characteristics of the capacitive element due to intrusion of titanium or the like into the capacitive insulating film 3 can be reliably prevented.

The capacitance insulating film 3 is made of strontium,
A ferroelectric composed of a first oxide containing bismuth and tantalum as a main component, a ferroelectric composed of a second oxide containing lead, zircon and titanium as a main component, or a first oxide and a second oxide It can be composed of a composite dielectric made of an oxide. These oxides are ferroelectric and can provide a large capacity even in a small area, so they are suitable for high integration and, when used for memory, have a low operating voltage, high-speed writing, and high-speed reading. Such excellent characteristics can be realized.

The interlayer insulating film 8 is preferably formed of one of a silicon oxide film, a silicon oxide film containing boron and phosphorus, and a silicon oxide film containing phosphorus. As a result, an interlayer insulating film with good flatness can be obtained, and the stabilization and long life of the capacitor can be realized.

(Second Embodiment) FIG. 3 is a sectional view showing an essential part of a capacitive element according to a second embodiment.

As shown in the figure, a lower electrode 2 is formed on a substrate 1 (such as a silicon substrate), and a capacitive insulating film 3 having substantially the same outer peripheral shape as the lower electrode 2 is formed on the lower electrode 2. Are formed. Insulating sidewalls 12 are formed on the side surfaces of the lower electrode 2 and the capacitive insulating film 3. It is desirable that the insulator sidewall 12 does not rise above the capacitive insulating film 3. A first opening 4 reaching the lower electrode 2 is formed in the capacitor insulating film 3. Further, an upper electrode 7 extending from above the capacitor insulating film 3 to above the substrate 1 through the insulator sidewall 12.
Is provided. The upper electrode 7 includes a first partial film 7 a that contacts about half of the capacitive insulating film 3 and a capacitive insulating film 3.
And the second partial film 7b which is not in contact with. The first partial film 7 a of the upper electrode 7, the lower electrode 2, and the capacitance insulating film 3 constitute an MIM-type capacitance element. Also in the present embodiment, the second partial film 7b has a region which does not overlap with the capacitance insulating film when viewed in plan.

On the first partial film 7 a and the second partial film 7 b, an interlayer insulating film 8 covering the entire substrate is formed, and the interlayer insulating film 8 and the inside of the first opening 4 are formed. A first contact hole 9a penetrating through the interlayer insulating film 8 and reaching the lower electrode 2, and a second partial film 7 penetrating through the interlayer insulating film 8
A second contact hole 9b reaching a region which does not overlap with the capacitive insulating film when viewed in a plan view is formed. Further, a first electrode wiring 10 is provided in the first contact hole 9a and on the interlayer insulating film 8 around the first contact hole 9a, and is provided on the interlayer insulating film 8 in the second contact hole 9b and around the same. The second electrode wiring 11 is provided. The first and second electrode wirings 10 and 11 are respectively composed of lower films 10a and 11a made of titanium and upper films 10b and 11b made of an aluminum alloy film. I have.

Therefore, also in the capacitive element of this embodiment, the second electrode wiring 11 is connected to a region of the second partial film 7b of the upper electrode 7 which does not overlap with the capacitive insulating film when viewed in plan. It will be.

Next, a description will be given of a manufacturing process of the capacitive element according to the present embodiment. 5A to 5D are cross-sectional views showing the first half of the manufacturing process of the capacitive element according to the present embodiment, and FIGS. 6A to 6D show the latter half. It is sectional drawing.

First, in the step shown in FIG. 5A, a first metal film 2a and a dielectric film 3a are formed on the main surface of the substrate 1.

Next, in the step shown in FIG. 5B, the first metal film 2a and the dielectric film 3a are patterned by etching using a photoresist mask (not shown) covering the capacitive element formation region. Thus, the lower electrode 2 and the capacitor insulating film 3 having the same outer peripheral shape are formed. here,
Unlike the first embodiment, no opening is formed in the capacitance insulating film 3.

Next, in a step shown in FIG. 5C, an insulating film 12a such as a silicon oxide film is deposited on the substrate.

Next, in the step shown in FIG. 5D, anisotropic etching is performed on the entire surface of the insulating film 12a to leave the insulator sidewalls 12 on the side surfaces of the capacitive insulating film 3 and the lower electrode 2. At this time, the insulating film 12 on the capacitive insulating film 3
It is important that a is reliably removed.

Next, in the step shown in FIG. 6A, after forming a second metal film (a metal film for an upper electrode, not shown) on the substrate, the second metal film is patterned. A first partial film 7a existing on the capacitive insulating film 3 and a capacitor connected to the first partial film 7a and not in contact with the capacitive insulating film 3 and viewed in plan on the substrate 1; A second partial film extending to a region that does not overlap with the insulating film is formed.

Next, in a step shown in FIG. 6B, an interlayer insulating film 8 is formed on the substrate. Further, in a step shown in FIG. 6C, a first contact hole 9a penetrating through the interlayer insulating film 8 and the capacitive insulating film 3 and reaching the lower electrode 2 is formed.
Then, a second contact hole 9b penetrating through the interlayer insulating film 8 and reaching a region of the second partial film 7b which does not overlap with the capacitive insulating film in plan view is formed.

Thereafter, in the step shown in FIG.
After sequentially depositing a titanium film and an aluminum alloy film on the substrate, both are patterned to form a first electrode wiring 10 filling the first contact hole 9a and a second electrode wiring 10 filling the second contact hole 9b. The electrode wiring 11 is formed. That is, the lower films 10a and 11a made of a titanium film
And upper films 10b and 11b made of an aluminum alloy film
First and second electrode wirings 10 and 11 are formed.

When this capacitive element is formed in an integrated circuit, the first electrode wiring 10 and the second electrode wiring 11 constitute a part of a wiring layer of the integrated circuit. It is formed in the same process as the layer.

Also in the present embodiment, the upper electrode 7 is constituted by the first partial film 7a contacting the capacitive insulating film 3 and the second partial film 7b not contacting the capacitive insulating film 3,
Is in contact with a region of the second partial film 7b which does not overlap with the capacitive insulating film 3 when viewed in a plan view, so that titanium and ferroelectric material are actuated in the same manner as in the first embodiment. Capacitive insulating film 3 due to reaction with the body
The performance can be reliably prevented from deteriorating.

In addition, in the present embodiment, since the insulator sidewalls 12 are formed on the side surfaces of the capacitor insulating film 3 and the lower electrode 2, the upper electrode 7 is separated from the capacitor insulating film 3 by the insulator sidewalls. Since it is formed smoothly so as to extend over the substrate 1 via the upper surface 12, disconnection between the ends of the capacitive insulating film 3 and the lower electrode 2 can be prevented.

In this embodiment, the lower electrodes 2 and
Various materials can be used for the upper electrode 7, the capacitor insulating film 3, and the interlayer insulating film 8, as in the first embodiment.

The insulator side wall is preferably formed of one of a silicon oxide film, a silicon oxide film containing boron and phosphorus, and a silicon oxide film containing phosphorus. As a result, the step formed by the capacitor insulating film and the lower electrode can be smoothly filled.

(Third Embodiment) Next, FIGS. 7 and 8
FIGS. 7A and 7B are a cross-sectional view and a plan view illustrating a main part of a capacitive element according to a third embodiment. However, in FIG. 8, it is assumed that there is no interlayer insulating film and no electrode wiring. A lower electrode 2 is formed on a substrate 1 (such as a silicon substrate), and a capacitance insulating film 3 is formed on the lower electrode 2. A first opening 4 reaching the lower electrode 2 is formed in the capacitor insulating film 3. Further, a covering insulating film 5 is formed on the capacitive insulating film 3, and a second opening 6 (capacitance value defining opening) reaching the capacitive insulating film 3 is formed in the covering insulating film 5. Have been. Then, the first partial film 7 a of the upper electrode 7 is formed so as to fill the inside of the second opening 6. The lower electrode 2, the capacitor insulating film 3, and the second
And the first partial film 7a in the opening 6 constitute an MIM-type capacitive element.

Further, on the insulating film for covering 5, the first partial film 7 a in the second opening 6 is connected and extends.
A second partial film 7b of the upper electrode 7 formed in a region not in contact with the capacitance insulating film 3 is provided. In particular, in the present embodiment, the second partial film 7b has a region located above the capacitance insulating film 3, that is, a region that overlaps with the capacitance insulating film in plan view. On the first partial film 7a and the second partial film 7b, an interlayer insulating film 8 covering the entire substrate is formed, and the interlayer insulating film 8 and the coating in the first opening 4 are formed. The first contact hole 9a penetrating through the insulating film 5 for use to reach the lower electrode 2 and the second partial film 7b penetrating through the interlayer insulating film 8 and overlapping with the capacitive insulating film 3 in plan view. A second contact hole 9b reaching the region is formed. A first electrode wiring 10 is provided in the first contact hole 9a and on the interlayer insulating film 8 around the first contact hole 9a.
A second electrode wiring 11 is provided on the inside and around the interlayer insulating film 8. The first and second electrode wirings 1
Reference numerals 0 and 11 denote lower layer films 10a and 1 made of titanium, respectively.
1a and an upper film 10b, 1 made of an aluminum alloy film.
1b, that is, each is composed of two laminated films.

Therefore, in the capacitive element of the present embodiment, the second electrode wiring 11 is connected to a region of the second partial film 7b of the upper electrode 7 that overlaps with the capacitive insulating film in a plan view. Will be. In addition, the insulating film 5 for covering in the present embodiment functions as an insulating film for defining a capacitance value that defines the capacitance of the capacitive element, and also functions as an insulating film for underlaying the second partial film 7 b of the upper electrode 7. .

Also in the present embodiment, since the upper electrode 7 is constituted by the first partial film 7a that contacts the capacitive insulating film 3 and the second partial film 7b that does not contact the capacitive insulating film 3, By the same operation as in the first embodiment, it is possible to prevent the performance of the capacitive insulating film 3 from deteriorating due to the reaction between titanium and the ferroelectric.

In addition, in the present embodiment, since the second electrode wiring 11 is in contact with a region of the second partial film 7b that overlaps with the capacitance insulating film 3 in plan view, By effectively utilizing the space above 3, the upper electrode 7 can be provided with a contact portion with the second electrode wiring 11, and the capacitor can be miniaturized.

(Other Embodiments) In each of the above embodiments, the lower electrode is made of a platinum film or the like. However, the present invention is not limited to this embodiment, and the lower electrode may be made of a polysilicon film or an aluminum alloy. It may be constituted by a film or the like. In each of the above embodiments, the region immediately below the lower electrode is a non-conductive region (semiconductor substrate).
The present invention is not limited to such an embodiment, and may be a source / drain region of a semiconductor substrate into which impurities are diffused. For example, if the storage node arranged in the memory cell transistor of the stacked DRAM is used as the lower electrode of the capacitor of the present invention and the cell plate is used as the upper electrode, the capacitor of the present invention can be used as the storage capacitor of the stacked DRAM. . In that case, the storage node is formed on the source region in the semiconductor substrate.

Further, the capacitance element may have a MIS capacitor structure. In this case, the lower electrode may be a high-concentration impurity diffusion region in the semiconductor substrate.

Also, as shown in FIGS. 1 and 7,
In the structure having the capacitance value defining opening (second opening 6) in the capacitance element of the third embodiment, the capacitance insulating film 3
Alternatively, a structure in which an insulator sidewall is formed on a side surface of an outer peripheral portion of the lower electrode 2 may be employed. In this case, the insulator sidewall is also formed on the side surface of the inner peripheral portion of the second opening 6 of the covering insulating film 5, so that the step of the upper electrode 7 at the step portion can be prevented. There are advantages that can be done.

[0086]

According to the capacitive element of the present invention, the upper electrode is constituted by the first partial film which is in contact with the capacitive insulating film and the second partial film which is not in contact with the capacitive insulating film, and the electrode wiring is formed. Since the second partial film is brought into contact with the second partial film, the material forming the electrode wiring diffuses from the second partial film to the first partial film through the crystal grain boundary in the upper electrode and enters the capacitance insulating film. , It is possible to prevent the deterioration of the characteristics of the capacitor insulating film due to the reaction with the material forming the electrode wiring.

This structure of the capacitive element can be easily realized by the method of manufacturing the first or second capacitive element of the present invention.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a structure near a capacitance element according to a first embodiment.

FIG. 2 is a plan view showing a structure near a capacitive element according to the first embodiment.

FIG. 3 is a cross-sectional view illustrating a manufacturing step of the capacitive element according to the first embodiment.

FIG. 4 is a cross-sectional view illustrating a structure near a capacitive element according to a second embodiment.

FIG. 5 is a cross-sectional view showing the first half of the manufacturing steps of the capacitive element according to the second embodiment.

FIG. 6 is a cross-sectional view showing the latter half of the manufacturing steps of the capacitive element according to the second embodiment.

FIG. 7 is a cross-sectional view illustrating a structure near a capacitive element according to a third embodiment.

FIG. 8 is a plan view illustrating a structure near a capacitive element according to a third embodiment.

FIG. 9 is a cross-sectional view showing a structure near a conventional capacitive element.

FIG. 10 is a cross-sectional view showing a manufacturing process of a conventional capacitive element.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Substrate 2 Lower electrode 2a 1st metal film 3 Capacitance insulation film 3a Dielectric film 4 1st opening 5 Insulating film for covering (insulating film for capacitance value definition, underlay insulating film) 6 2nd opening (capacitance value Opening 7) Upper electrode 7a First partial film 7b Second partial film 8 Interlayer insulating film 9a First contact hole 9b Second contact hole 10 First electrode wiring 10a Lower film 10b Upper film 11 Second Electrode wiring 11a Lower layer film 11b Upper layer film

Claims (16)

[Claims] An upper surface of a substrate, a lower electrode made of a conductive film formed on the substrate, a capacitor insulating film formed on the lower electrode, and a metal material. An upper electrode having a first partial film in contact with the first electrode and a second partial film not in contact with the capacitor insulating film; an interlayer insulating film covering at least the upper electrode; and the upper electrode penetrating the interlayer insulating film. Of the second
A capacitive element comprising: a contact hole reaching the partial film of (1); and an electrode wiring filling at least the contact hole and connected to the upper electrode. 2. The capacitive element according to claim 1, wherein the second partial film of the upper electrode has a region which does not overlap with the capacitive insulating film in plan view, and wherein the electrode wiring Is connected to the upper electrode in a region of the second partial film that does not overlap with the capacitance insulating film. 3. The capacitive element according to claim 1, wherein the upper electrode is formed so as to contact only a part of the capacitive insulating film, and is in contact with the upper electrode of the capacitive insulating film. An underlying insulating film that covers at least a part of the non-existing region, wherein the second partial film of the upper electrode overlaps the capacitive insulating film as viewed in plan on the underlying insulating film. A capacitance element having a region, wherein the electrode wiring is connected to the upper electrode in a region of the second partial film that overlaps with the capacitance insulating film when viewed in plan. . 4. The capacitive element according to claim 1, wherein the capacitive insulating film is formed to have substantially the same outer peripheral shape as the lower electrode, and an outer peripheral portion of the capacitive insulating film and the lower electrode. A capacitive element further comprising an insulator sidewall formed on a side surface of the capacitor. 5. The capacitance element according to claim 1, wherein a capacitance value defining insulating film covers a region along an outer periphery of the capacitance insulating film, and the capacitance value defining insulating film. And a capacitance value defining opening formed in a region located above the main region excluding a region along the outer periphery of the capacitance insulating film, wherein the first partial film of the upper electrode includes the capacitance A capacitive element formed in a value defining opening. 6. The capacitive element according to claim 1, wherein the metal material forming the upper electrode includes at least one of platinum, iridium, palladium, and ruthenium. A capacitive element characterized by the above-mentioned. 7. The capacitive element according to claim 1, wherein the upper electrode is formed by stacking at least two films of a platinum film, an iridium film, a palladium film, and a ruthenium film. A capacitive element characterized by being constituted by: 8. The capacitive element according to claim 6, wherein the upper electrode has a columnar crystal structure perpendicular to the surface of the base. 9. The capacitive element according to claim 1, wherein said capacitive insulating film is a first oxide mainly containing one of strontium, bismuth and tantalum. And a second oxide containing any one of lead, zircon and titanium as a main component, and a composite of the first and second oxides.
A capacitive element comprising: 10. A first step of sequentially forming a conductor film and a dielectric film on a substrate, and a second step of patterning the conductor film and the dielectric film to form a lower electrode and a capacitor insulating film. A third step of forming a metal film for an upper electrode on a substrate; patterning the metal film for an upper electrode to form a first partial film that contacts an upper surface of the capacitor insulating film; A fourth step of forming an upper electrode having a second partial film that is not in contact, a fifth step of forming an interlayer insulating film on a substrate, a second step of penetrating the interlayer insulating film, A sixth step of forming a contact hole reaching the partial film of the above; and, after depositing a metal film for wiring on the substrate, patterning the metal film for wiring and filling the contact hole to fill the contact hole with the second partial film of the upper electrode. A seventh step of forming electrode wiring to be connected; The manufacturing method of the capacitive element provided with. 11. The method for manufacturing a capacitive element according to claim 10, wherein, in the second step, the conductor film and the dielectric film are etched using a common mask member to have substantially the same outer peripheral shape. After forming a lower electrode and a capacitor insulating film, depositing a sidewall insulating film on a substrate, performing anisotropic etching to form an insulator sidewall on an end face of an outer peripheral portion of the capacitor insulating film and the lower electrode. The method further comprising: forming a second partial film of the upper electrode in a region on the substrate including a portion above the insulator sidewall in the fourth step. . 12. A first step of sequentially forming a conductor film and a dielectric film on a substrate, and a second step of patterning the conductor film and the dielectric film to form a lower electrode and a capacitor insulating film. A third step of forming an underlay insulating film on the substrate; a fourth step of partially removing the underlay insulating film to expose a portion of the capacitive insulating film; A fifth step of forming a metal film for an electrode; and a first partial film that is patterned on the metal film for an upper electrode to contact an upper surface of the capacitance insulating film on a region where the capacitance insulating film is exposed. A sixth step of forming an upper electrode having a second partial film on the underlying insulating film, a seventh step of forming an interlayer insulating film on a substrate, Forming a contact hole that penetrates to reach the second partial film of the upper electrode An eighth step of forming a wiring metal film on the substrate and then patterning the wiring metal film to fill the contact hole and form an electrode wiring connected to the second partial film of the upper electrode. 9. A method for manufacturing a capacitive element, comprising: 13. The method for manufacturing a capacitive element according to claim 12, wherein in the fourth step, a region located above a main region of the underlay insulating film excluding a region near an outer periphery of the capacitive insulating film. And forming a capacitor defining opening by removing the second electrode. In the sixth step, a second partial film of the upper electrode is formed in the capacitor defining opening. 14. The method for manufacturing a capacitive element according to claim 12, wherein, in the sixth step, a second partial film of the upper electrode is formed by:
A method for manufacturing a capacitive element, wherein the capacitive element is formed on a region of the substrate that does not overlap with the capacitive insulating film. 15. The method for manufacturing a capacitive element according to claim 12, wherein in the sixth step, a second partial film of the upper electrode is formed by:
A method of manufacturing a capacitive element, comprising: forming an insulating film on an underlying film in a region overlapping with the capacitive insulating film. 16. The method of manufacturing a capacitive element according to claim 10, wherein the step of forming the upper electrode metal film is performed by sputtering. Production method.