JPH1173781A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the reduction of the signal voltage and provide a sufficient readout margin by setting the ratio between the floating capacity of the bit line pair on the high order bit side and that of the low order side at a value less than a specified one. SOLUTION: The ratio of the floating capacity Cb1 of the bit line pair, BL 01 and BLB 01, side region corresponding to the high order bit to the floating capacity Cb2 of the bit line pair, BL 02 and BLB 02, side region corresponding to the low order bit is set at a value less than 2, for example, 5/3 by using different numbers in the word lines of each region. At rewrite operation, 0,3/8 Vcc, 5/8 Vcc, Vcc are obtained as multi-value levels to be written into the memory cell MC in correspondence to information, (0, 0), (0, 1), (1, 0), (1, 1). Even under the assumption that the coupling capacity Cc is formed by a section of, for example, nine memory cell capacities and this is fluctuated by ±25%, the margin at the time of signal readout of the low order bit can be sufficiently obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device for a multi-level memory cell.

[0002]

2. Description of the Related Art As a prior art of this type of semiconductor memory device, a device for high integration of a dynamic type semiconductor memory device is disclosed in, for example, Japanese Patent Application No. 8-0832424 (hereinafter referred to as "Japanese Patent Application No. 1 as a conventional example).

FIG. 6 is a block diagram showing a circuit configuration of a memory cell array section and a sense amplifier section in the first conventional example shown in the above-mentioned Japanese Patent Application No. 8-083424. Here, a configuration using quaternary memory cells is shown. Further, as shown in FIG. 7, the power supply voltage is set to Vcc in each memory cell.
Then, 0, (1/3) Vcc, (2/3) Vcc,
One of a total of four pieces of information of Vcc is stored. That is, these are (0,0),
It corresponds to four information of (0, 1), (1, 0), and (1, 1).

The 0th to (n−1) th bit line pairs (BL)
j, BLBj) (j = 0 to n-1, where j and n are integer values)
In addition, the 0th to (m−1) th word lines WLi (i = 0 to 0)
m-1, i, m are integer values. A memory cell is connected to the intersection of ().

FIG. 8 shows a configuration of a memory cell (hereinafter, referred to as cell 1) connected to the intersection of the 0th bit line BL0 and the 0th word line WL0. The cell 1 includes a capacitor having a memory cell capacitance C's and an N-channel MOSFET. In the N-channel MOSFET, the gate is connected to the 0th word line WL0, the drain is connected to the 0th bit line BL0, and the source is connected to one end of the capacitor. The other end of the capacitor is connected to the counter electrode. Other memory cells other than the cell 1 have the same configuration.

In FIG. 6, first and second bit lines are connected to each other.
Are provided. First
Are supplied with a first sense amplifier activation signal SAE1 and the second sense amplifier SA2 is supplied with a second sense amplifier activation signal SAE2.
Each bit line pair is divided into a region 1 and a region 2 by a transfer gate SWT. The gate of the transfer gate SWT is connected to a gate selection line TG. The ratio of the stray capacitance C′bl generated on the bit line in the region 1 to the stray capacitance C′b2 generated on the bit line in the region 2 is 2: 1.
It is set to be. In order to achieve such a capacitance ratio, there are methods for providing a difference in the number of word lines in each region,
Although the number of word lines in each region is the same, there is a method of actually providing a dummy capacitor on a bit line.

[0007] Each bit line pair is provided with a coupling capacitance C'c. This connection relationship is as shown in FIG. Further, each bit line pair is provided with four input / output transistors I / OT. Two input / output transistors I / OT on the first sense amplifier SA1 side
Is connected to the first input / output data line I / O1, and the other two input / output transistors I / OT on the second sense amplifier SA2 side are connected to the first input / output data line I / O1. . The 0th to (n-1) th bit line pairs (BLj, B
(LBj) of the four input / output transistors I / OT are respectively connected to the 0th to (n−1) th bit line selection lines CSL0.
~ CSLn-1.

FIG. 9 shows operation waveforms at the time of data reading of the first conventional example shown in FIG. In the following description, FIG.
The description will be made on the assumption that (2/3) Vcc information is stored in the cell 1 and the information is read.

During the period until time T1, the bit line pair (BL
j, BLBj) is precharged to (1/2) Vcc. At this time, the gate selection line TG is at a high active level, and the transfer gate SWT is conductive, so that the region 1 and the region 2 are electrically connected.

At time T1, bit line pair (BLj, BLB
The precharge operation of j) is stopped, the 0th word line WL0 selected by the address input signal becomes a high active level, and (2/3) Vcc, which is the information of cell 1, is output to the 0th bit line BL0. Is done. At this time, the potential of the first bit line BL0 fluctuates from the precharged potential by a very small potential ΔV, and ｛(１ ／) Vcc + Δ
V｝. By the way, the information of cell 1 is 0, (1/3)
Vcc and Vcc, the potentials of the 0th bit line BL0 are {(1/2) Vcc-3ΔV} and {(1
/ 2) Vcc-ΔV}, {(1/2) Vcc + 3ΔV}
Becomes

Next, at time T2, the gate select line TG is set to the low-in active level, the transfer gate SWT is turned off, and the region 1 and the region 2 are electrically separated. Accordingly, the 0th non-inverted bit line BL0 is divided into the 0th region 1 side non-inverted bit line BL01 and the 0th region 2 side non-inverted bit line BL02, and the 0th inverted bit line BLB0 is It is divided into a 0 region 1 side inverted bit line BLB01 and a 0 region 2 side inverted bit line BLB02. Further, at time T3, the first sense amplifier activation signal SAE1 is set to the high active level, and the first sense amplifier circuit SA1 in the area 1 is operated. Thus, the first sense amplifier circuit SA1 amplifies the potential difference between the pair of bit lines (BLj1, BLBj1) on the region 1 side.
In the case of the 0th region 1 side bit line pair (BL01, BLB01), the 0th region 1 side non-inverting bit line BL01 is connected to Vcc
Level, the 0th region 1 side inversion bit line BLB01 is GN
It becomes D level.

At this time, the potential of the 0th area 1 side non-inverted bit line BLB02 increases by ΔVc due to the increase of the electric potential of the 0th area 1 side non-inverted bit line BL01 due to the coupling capacitance C′c. As the potential of the 0th region 1 side inverted bit line BLB01 falls, the potential of the 0th region 2 side non-inverted bit line BL02 decreases by ΔVc. That is, the potential of the non-inverting bit line BL02 on the 0th region 2 side is
｛(1/2) Vcc + ΔV−ΔVc), and the potential of the 0th area 2 side inversion bit line BLB02 becomes ｛(1
/ 2) Vcc + ΔVc).

Here, when the ratio between the coupling capacitance C′c and the memory cell capacitance C ′s is adjusted so that ΔVc = ΔV, 0, (１ ／) Vcc, (2/3) Vcc,
The potential differences of the bit line pair (BL02, BLB02) on the 0th region 2 side with respect to the four information of Vcc are all ΔV,
Become equal. This potential difference is also equal to the minimum value ΔV of the potential difference between the bit line pair (BL01, BLB01) on the 0th region 1 side before amplification by the first sense amplifier circuit SA1.

Next, at time T4, the second sense amplifier activation signal SAE2 is set to the high active level, and the second sense amplifier circuit SA2 in the area 2 is operated. As a result, the second sense amplifier circuit SA2 amplifies the potential difference between the region 2 side bit line pair (BLj2, BLBj2). Bit line pair (BL02, BLB0
In the case of 2), the 0th region 2 side non-inverted bit line BL02 is at the GND level, and the 0th region 2 side inverted bit line BLB02 is
Becomes the Vcc level.

Next, at time T5, the 0th bit line selection line CSL0 selected by the address input signal temporarily becomes a high active level, and the 0th region 1 side bit line pair (BL01, BLB01) is amplified. The data is applied to the first input / output line I / O1, and the bit line pair (BL0
2, BLB02) to the second input / output line I / O
Output to 2. The bit line pair (BL01, BL01,
When the amplified data of BLB01) is made to correspond to the upper bit and the amplified data of the bit line pair (BL02, BLB02) on the 0th area 2 side is made to correspond to the lower bit, the data (1,
0) is output.

Next, at time T6, the first and second sense amplifier activation signals SAE1 and SAE2 attain a low-inactive level, and the first and second sense amplifier circuits SA1 and SA2 are deactivated. As a result, the 0th region 1 side bit line pair (BL01, BLB01) and the 0th region 2 side bit (BL02, BLB02) are both in a high impedance state. Then, at time T7, the gate selection line TG goes to the high active level, and the transfer gate SWT conducts, so that the region 1 and the region 2 are electrically connected. Thereby, the potentials of the bit lines in the region 1 and the region 2 become equal. Stray capacitance C of the bit line in region 1
Since the ratio between the stray capacitance C′b2 of the bit line in the region 2 and the bit line BL0 in the region 2 is not set, the ratio of the non-inverted bit line BL01 to the 0th region 1 side and the non-inverted bit line BL0 to the 0th region 2 is set.
The potential of 2 is Vrest (1,0) = (Cbl * Vcc + Cb2 * 0) / (Cb1 + Cb2) = (2/3) Vcc, which is equal to the potential stored in cell 1 before reading. This potential is written into the cell 1 again in the period from the time T7 to T8.

Thereafter, at time T8, the selected 0th word line WL0 goes to the low inactive level. Then, the precharge operation of the 0th bit line pair (BL0j, BLB0j) is performed, and the read operation ends.

Although the data read operation has been described above, the description of the data write operation will be omitted.

FIG. 10 is a block diagram showing a circuit configuration (for one pair of main pit lines) of a memory cell array section and a sense amplifier section in a second conventional example shown in Japanese Patent Application No. 8-352635. is there. Also in this case, as shown in FIG. 7, each memory cell existing in the memory cell array unit has
Any one of a total of four pieces of information of 0, (1/3) Vcc, (2/3) Vcc, and Vcc is stored. That is, these are (0,0), (0,1),
It corresponds to four pieces of information (1, 0) and (1, 1).

In FIG. 10, a portion S surrounded by a dotted line
SA is a sub sense amplifier circuit. The bit lines are hierarchized into complementary main bit lines (GBL, GBLB) and complementary sub bit lines (SBL, SBLB), and one set of main bit lines (GBL, GBLB) has one layer. One main sense amplifier circuit MSA and a plurality of sub sense amplifier circuits SS
A (However, in FIG. 10, one sub-sense amplifier circuit SSA
Are only shown).

The auxiliary sense amplifier circuit SSA includes sense amplifier transistors 1 and 2, transistors 3 and 4 having a gate input of an offset canceling control signal OCS, and transistors 5 and 6 having a read switch signal RS as a gate input. , Coupling capacitors C′c and C′c, transistors 7 and 8 having a control signal CPE as a gate input, and transistors 9, 10 and 11 having a precharge control signal as a gate input.

In FIG. 10, MC indicates a memory cell of a dynamic semiconductor memory device constituting a memory cell array, and only the cell 1 is shown in the drawing. It is separated into an upper side and a lower side with respect to the sub sense amplifier circuit SSA. The SET is connected to the sub-bit line (SB
L, SBLB) to the upper sub-bit line pair (SBLU, SLB).
BLBU) and the lower side sub-bit line pair (SBLL, SBLB)
L) is a first transfer gate for separating into two. Note that the transistors 7 and 8 are called a second transfer gate.

FIG. 11 shows operation waveforms at the time of data reading of the second conventional example shown in FIG. In the following description,
Description will be made on the assumption that (2/3) Vcc information is stored in the cell 1 selected by the word line WL and the upper non-inverting sub-bit line SBLU, and the information is read.

During a period until time T1, the precharge control signal BBL of the sub-bit line is at a high active level.
Upper sub bit line pair (SBLU, SBLBU), sub bit line pair (SBL, SBLB), lower sub bit line pair (S
BLL, SBLBL) are all precharged to (1/2) Vcc level.

When the precharge control signal BBL of the sub-bit line changes to the low inactive level at time T1, the pre-charge operation of the sub-bit line in FIG. 10 is stopped. Also, at time T1, the lower control signal TGL
Since both 0 and TGL1 change to the low-inactive level, the non-inverted sub-bit line SBL and the lower non-inverted sub-bit line SBLL, and the inverted sub-bit line SBLB and the lower inverted sub-bit line SBLBL are electrically separated. You.

Next, at time T2, the control signal OCS for the offset cancel of the sub sense amplifier circuit SSA
Thus, the OCV changes as shown, and the variation in the threshold voltage of the sense amplifier transistors 1 and 2 is compensated.
However, for the sake of simplicity, the following description will be made on the assumption that the threshold voltages of the sense amplifier transistors 1 and 2 do not vary.

Next, at time T3, the word line WL selected by the address input signal attains a high active level, and (2/3) Vcc, which is the information of the cell 1, changes to the upper non-inverting sub-bit line SBLU, non-inverting. Sub-bit line SBL
Output above. At this time, the upper non-inverting sub-bit line S
The potentials of BLU and the non-inverting sub-bit line SBL fluctuate from the precharged potential by a small potential ΔV. Incidentally, when the information of the cell 1 is 0, (1/3) Vcc, Vcc, the potentials of the upper non-inverting sub-bit line SBLU and the non-inverting sub-bit line SBL are respectively changed from the precharged potential. , -3ΔV, one ΔV, 3ΔV.

Next, at time T4, when the read switch signal RS changes to the high active level as shown in FIG. 11, the transistors 5 and 6 of the sub sense amplifier circuit SSA are turned on, and the main bit line precharge (not shown) is performed. The potential of the main bit line pair (GBL, GBLB) precharged to (1/2) Vcc by the circuit changes the gate potential of the sense amplifier transistors 1 and 2, that is, the sub bit line pair (SBL, SBLB). Lowered according to level. As a result, the potential difference read to the sub-bit line pair (SBL, SBLB) is changed to the main bit line pair (GBL, GBL).
B).

Next, at time T5, the read switch signal RS falls to the low inactive level, and the main sense amplifier circuit MSA causes the main bit line pair (GB
L, GBLB) as shown in FIG.
Amplified to c or GND level. Cell 1 information is
In the case of Vcc or (2/3) Vcc, the non-inverted main bit line GBL is at the Vcc level and the inverted main bit line GBL is
B becomes the GND level. This indicates a read operation of the upper bit, and indicates that "1" data is read in any case. On the other hand, the information of cell 1 is
In the case of (１ ／) Vcc or 0, “0” data is read by the reading operation of the upper bits.

As described above, while the main bit line pair (GBL, GBLB) is being amplified from time T5 to time T6,
Since control signal CPE is at a high active level, main bit line pair (GBL, GBL) is controlled by coupling capacitance Cc.
BLB), the sub-bit line pair (S
BL, SBLB) also fluctuates. When the information of the cell 1 is (2/3) Vcc, the potential of the inverted sub-bit line SBLB becomes ΔVc with the rise of the potential of the non-inverted main bit line GBL.
, And the potential of the non-inverted sub-bit line SBL decreases by ΔVc as the potential of the inverted main bit line GBLB decreases.

Here, as in the first conventional example, ΔVc =
When the ratio between the coupling capacitance Cc and the memory cell capacitance Cs is adjusted to be ΔV, 0, (１ ／) Vcc,
(2/3) The potential differences of the sub-bit line pairs (SBL, SBLB) for the four information Vcc and Vcc are all equal to ΔV and equal. This potential difference is also equal to the minimum value ΔV of the potential difference between the sub-bit line pair (SBL, SBLB) when reading the upper bits.

Next, at time T6, the upper control signals TGU0 and #CPE fall to the low inactive level, and the upper sub bit line pair (SBLU, SBLBU) and the sub sense amplifier circuit SSA in the memory cell array section.
Are electrically separated from each other. Thereafter, the potential of the sub-bit line pair (SBL, SBLB) changes from the main bit line pair (GB
L, GBLB) are not affected.

Next, at time T7, the upper write switch signal WSU rises to the high active level, and the amplified potential of the main bit line pair (GBL, GBLB) is changed to the upper sub bit line pair (SBLU, SBLBU). Are written respectively.

Next, at time T8, the upper write switch signal WSU falls to the low inactive level, and the main bit line pair (GBL, GBLB) becomes (1/1).
2) Precharged to Vcc level.

Next, at time T9, the read switch signal RS rises to the high active level again,
The potential difference between the sub-bit line pair (SBL, SBLB) is transmitted to the main bit line pair (GBL, GBLB).

Next, at time T1O, the read switch signal RS falls to the low inactive level,
The main bit line pair (GB
L, GBLB) as shown in FIG.
Amplified to c or GND level. Cell 1 information is
In the case of (2/3) Vcc or 0, the non-inverted main bit line GBL is at the GND level and the inverted main bit line GBLB is at the Vcc level. This indicates a lower bit read operation, and indicates that "0" data is read in any case. On the other hand, if the information of cell 1 is Vc
In the case of c or (１ ／) Vcc, “1” data is read by the reading operation of the lower pit.

Next, at time T11, the lower write switch signal WSL and the lower control signal TGL0 rise to the high active level, and the potential of the amplified main bit line pair (GBL, GBLB) is changed to the lower sub bit. Line pair (SBLL, SBLBL), sub-bit line pair (SBL,
SBLB).

Next, at time T12, the lower write switch signal WSL falls to the low inactive level, the lower control signal TGU0 rises to the high active level, and the upper sub bit line pair (SBL
U, SBLBU), sub-bit line pair (SBL, SBL
B), the lower bit line pair (SBLL, SBLBL)
All connected. Here, the lower side sub-bit line pair (SB
LL, SBLBL) into two lower control signals TGL
I is a row inactive level, and the ratio of the stray capacitance of the upper sub-bit line pair (SBLU, SBLBU) to the lower sub-bit line pair (SBLL, SBLBL) is 2: 1.

The floating capacitance of the sub bit line pair (SBL, SBLB) in the sub sense amplifier circuit SSA is compared with the upper sub bit line pair (SBLU, SBLBU) and the lower sub bit line pair (SBLL, SBLBL). If the information of the cell 1 is (2/3) Vcc, the potential of the upper non-inverting sub-bit line SBLU becomes Vrest (1,0) = (2/3) Vcc. It becomes equal to the potential stored in 1. This potential is written to the cell 1 again in the period from the time T12 to T13.

Thereafter, at time T13, the selected word line WL goes low. Then, at time T14, the precharge control signal BBL of the sub bit line rises to the high active level, and the upper sub bit line pair (SBLU, SBLBU), the sub bit line pair (SBL, SBLB), and the lower sub bit line pair (SB
LL, SBLBL) are all precharged to the (1/2) Vcc level, and the read operation ends.

Although the data read operation has been described above, the description of the data write operation will be omitted as in the first conventional example.

Here, two points common to the two conventional operation systems described above will be described.

First, in either case, as shown in FIG. 7, (0, 0), (0, 1), (1,
When writing the four information of (0) and (1,1) into the memory cell, they are 0, (1/3) Vcc, and (2/3), respectively.
Vcc and Vcc. Therefore, at the time of the rewrite operation, the ratio between the stray capacitance C'bl of the bit line corresponding to the upper bit and the stray capacitance C'b2 of the bit line corresponding to the lower bit is set to 2: 1, and this potential is set. It has occurred.

Next, in both cases, ΔVc
= ΔV, the ratio between the coupling capacitance C′c and the memory cell capacitance C ′s is adjusted. By setting in this way, the signal voltages at the time of reading the lower bits for each of the four pieces of information are all equal to ΔV and equal. In the case of (0, 1) and (1, 0), the signal voltage becomes equal to the signal voltage ΔV at the time of reading the upper bits.

In the case of the first conventional example, ΔVc = ΔV
Holds when C′c = (1/9) C ′s holds between the coupling capacitance C′c and the memory cell capacitance C ′s. The coupling capacitance C′c that satisfies the above equation can be realized, for example, by connecting nine memory cell capacitances C ′s in series.

In the case of the second conventional example, ΔVc = ΔV
Holds when C′c = (１ ／) C ′s holds between the coupling capacitance C′c and the memory cell capacitance C ′s. The coupling capacitance C′c that satisfies the above equation can be realized, for example, by connecting three memory cell capacitances C ′s in series.

[0047]

However, in the case of the conventional example described above, the sense result of the upper bit is fed back to the sense level of the lower bit by the function of the coupling capacitor C'c, so that multi-value reading is performed. Operation is realized. Therefore, when the ratio between the coupling capacitance C′c and the memory cell capacitance C ′s varies, when the signal voltage of the lower bit is (0, 1) or (1, 0),
It is lower than the signal voltage ΔV of the upper bit. For example, in the first conventional example, when C′c> (1/9) C ′s, the signal voltage of the lower bit in the case of (1, 1) or (0, 0) is smaller than ΔV. Become. Conversely, when C′c <(1/9) C ′s, the signal voltage of the lower bits in (1, 0) and (0, 1) becomes smaller than ΔV. in this way,
When the ratio between the coupling capacitance C'c and the memory cell capacitance C's fluctuates in either direction from the optimum value, the signal voltage of the lower bit decreases, leading to deterioration of the read margin.

Therefore, an object of the present invention is to minimize the reduction of the signal voltage when the upper bits and the lower bits are viewed in total even when the ratio between the coupling capacitance and the memory cell capacitance varies. Accordingly, it is an object of the present invention to provide a semiconductor memory device for a multilevel memory cell having a sufficient read margin.

[0049]

In order to achieve the above object, a semiconductor memory device according to a first aspect of the present invention comprises a complementary first bit line pair and a complementary second bit line pair. A first sense amplifier circuit connected to the first bit line pair, a second sense amplifier circuit connected to the second pit line pair, the first bit line pair, A first transfer gate connecting to a second bit line pair, and a coupling capacitor connected between the first bit line pair and the second bit line pair; Writing different voltages to one bit line pair and the second bit line pair, and then activating the first transfer gate to create four voltage states by charge distribution, Operation by writing four states to In the semiconductor memory device to be realized, the ratio of the stray capacitance of the first bit line pair to the second bit line pair is set to less than 2 and / or the ratio of the coupling capacitance to the memory cell capacitance is ( 1/9).

Further, the semiconductor memory device according to the second aspect of the present invention is configured such that hierarchical main bit lines and complementary sub bit line pairs are connected, and the main bit line pairs are connected to each other. A main sense amplifier circuit, one or more sub-sense amplifier circuits connected to the main bit line pair and each connected to the sub-bit line pair, and a sub-bit line pair, A first transfer gate which is separated into two sub-bit line pairs, and a coupling capacitor connected between the main bit line pair and the sub-bit line pair for each of the sub-sense amplifier circuits. A second transfer gate connected in series, and writing different voltages to the upper sub-bit line pair and the lower sub-bit line pair, and thereafter activating the second transfer gate. , In a semiconductor memory device in which four voltage states are created by load distribution and four states are written in a memory cell to realize a multi-level operation, the stray capacitance of the upper sub-bit line pair with respect to the lower sub-bit line pair And / or the ratio of the coupling capacitance to the memory cell capacitance is set to less than (1/3).

[0051]

By the means described above, in the semiconductor memory device of the present invention, unlike the conventional example, the signal voltage of the lower bit can be made higher than the signal voltage of the upper bit. Therefore, even when the ratio between the coupling capacitance and the memory cell capacitance varies, the signal voltage of the lower bit affected by the variation is increased compared to the conventional example, so that the total of the upper bit and the lower bit is obtained. Can be increased as compared with the conventional example.

[0052]

FIG. 1 shows a circuit configuration of a memory cell array section and a sense amplifier section of a semiconductor memory device according to a first embodiment of the present invention. FIG. 1 shows a configuration using quaternary memory cells, which has the same circuit configuration as the first conventional example shown in FIG. 6 except for the following two points.

(A-1) The ratio of the stray capacitance Cbl generated in the bit line in the region 1 to the stray capacitance Cb2 generated in the bit line in the region 2 is set to less than 2.

(A-2) The ratio of the coupling capacitance Cc to the memory cell capacitance Cs is set to less than (1/9).

In the first embodiment, the above (A-
Although two of 1) and (A-2) are adopted, either one of them may be adopted.

FIG. 2 shows operation waveforms at the time of data reading according to the first embodiment of the present invention. The above (A-1), (A-
Since only the two points 2) exist, the operation waveform shown in FIG. 2 is the same as that of the first conventional example shown in FIG. 9 except for the following two points.

(B-1) Potential of Bit Line Pair at Reading (Periods T1 to T4) (B-2) Potential of Bit Line Pair at Rewriting Operation (Periods T7 to T8) ), (A-2) The effect of the difference between the two points on the two points (B-1) and (B-2) will be described below. A description of the entire data read operation and a description of the data write operation will be omitted.

Now, the first conventional example shown in FIG.
In the first embodiment shown in FIG. Assume that OV Cs = 36 fF Cb1 + Cb2 = 114 fF. In the case of the first conventional example, Cbl = (2/3) * (Cb1 + Cb2) = 76fF Cb2 = (1/3) * (Cb1 + Cb2) = 38fF Cc = (1/9) Cs = 4fF Assuming that the ratio of the coupling capacitance Cc to the memory cell capacitance Cs is always constant (= 1/9), the signal voltage at the time of reading is as follows.

Higher bit signal voltage ΔVu (1,0) in the case of (0,1), (1,0) = 160 mV (1,1), signal voltage ΔVu in the case of (0,0) (1,
1) = 480 mV The amount of transition of the bit line potential due to Cc ΔVc = 160 mV (0,1), (1,0), the signal voltage ΔVl (1,
0) = 160 mV (1,1), (0,0), the signal voltage ΔVu (1,
1) = 160 mV However, in practice, the ratio of the coupling capacitance Cc to the memory cell capacitance Cs varies. Now, the value of the coupling capacitance Cc varies by ± 25% (3
Assuming that fF ≦ Cc ≦ 5fF, Cs is always constant, ΔVc = 200 mV (in the case of +25%) = 120 mV (in the case of −25%) ΔV1 (1,0) = 240 mV (in the case of +25%) = 80 mV ( ΔV1 (1,1) = 80 mV (in the case of + 25%) ΔV1 (1,1) = 240 mV (in the case of −25%), and the signal voltage of the lower bit is obtained in both directions. Is reduced from 160 mV to 80 mV.

On the other hand, in the first embodiment of the present invention, C
When the value of c varies by ± 25%, the signal voltage ΔVu (1,0) of the upper pit in the case of (0,1), (1,0) is within the range of 80 mV <ΔVU (1,0) <160 mV. To adjust the ratio of Cb1 to Cb2. Now, the ratio of Cb1 to Cb2 is set to (5/5) so that ΔVu (1,0) = 120 mV.
Suppose 3). At this time, (0,0), (0,1), (1,0)
, (1,1), the write levels to the memory cells corresponding to the four information are as shown in FIG. Setting the ratio of Cbl to Cb2 to (5/3) is similar to setting the ratio to 2 by setting the difference in the number of word lines in each region, or by setting the number of word lines in each region to the same number. However, there is a method of actually providing a dummy capacitor on a bit line.

Next, in the first embodiment of the present invention, Δ
When Vu (1,0) = 120 mV, the memory cell capacity C
The ratio of the coupling capacitance Cc to s is set to Cc / Cs = 5/48 <1/9. At this time, assuming that the ratio of the coupling capacitance Cc to the memory cell capacitance Cs is always constant, the signal voltage ΔVu (1,0) of the upper bit in the case of (0,1), (1,0)
= 120 mV (1,1), (0,0) upper pit signal voltage ΔVu (1,1)
= 480 mV The amount of transition of bit line potential due to Cc ΔVc = 150 mV (0,1), signal voltage ΔVl (1,0) of lower pit when (1,0)
= 180 mV (1,1), (0,0), upper pit signal voltage ΔVu (1,1)
= 180 mV, and the signal voltage of the lower bits is higher than that of the upper bits. Then, as before, assuming that the coupling capacitance Cc varies ± 25%, ΔVc = 187.5 mV (in the case of +25%) = 112.5 mV (in the case of −25%) ΔVl (1,0) = 255 mV (In the case of +25%) = 105 mV (in the case of −25%) ΔV1 (1,1) = 255 mV (in the case of +25%) = 105 mV (in the case of −25%). As compared with the first conventional example, the minimum value of the signal voltage of the lower bits increases from 80 mV to 105 mV, and the read margin when the upper bits and the lower bits are viewed in total is larger than that of the first conventional example. Become.

FIG. 4 shows a circuit configuration (for one pair of main bit lines) of a memory cell array section and a sense amplifier section of a semiconductor memory device according to a second embodiment of the present invention. FIG. 4 shows a configuration using quaternary memory cells, which has the same circuit configuration as the second conventional example shown in FIG. 10 except for the following two points.

(C-1) Control signals TGU1, TGL1
Are the upper sub-bit line pairs (SBLU, SBL
BU), upper sub-bit line pair (SBLL, SBLBL)
From the side close to the sub sense amplifier circuit SSA, y: 1
It is divided into (1 ≦ y) stray capacitance ratios (see FIG. 4).

(C-2) The ratio of the coupling capacitance Cc to the memory cell capacitance Cs is set to less than (1/3).

In the second embodiment, (C-
Although two of 1) and (C-2) are employed, either one of them may be employed.

FIG. 5 shows operation waveforms at the time of data reading according to the second embodiment of the present invention. The above (C-1), (C-
Since only the two points 2) exist, the operation waveform shown in FIG. 5 is the same as that of the second conventional example shown in FIG. 11 except for the following two points.

(D-1) Potential of bit line pair at the time of reading (period T3 to T11) (D-2) Potential of bit line pair at the time of rewriting operation (period T12 to T13) ) And (C-2), the effect of the difference between the two points on the two points (D-1) and (D-2) will be described below. The description of the entire data read operation and the data write operation will also be omitted in this case.

Now, as in the first embodiment, FIG.
In the second conventional example shown in FIG. 4 and the second embodiment shown in FIG. OV Cs = 36 fF It is assumed that the stray capacitance Cbu of the upper sub-bit line pair (SBLU, SBLBU) is Cbu = 114 fF. The stray capacitance Cbl of the lower sub-bit line pair (SBLL, SBLBL) is Cbl = 114 fF. In the case of the second conventional example, since Cc = (３) Cs = 12fF, it is assumed that the ratio of the coupling capacitance Cc to the memory cell capacitance Cs is always constant (= 1/3). ), The signal voltage at the time of reading is as follows.

The signal voltage ΔVu (1,0) of the upper bit in the case of (0,1), (1,0) = 160 mV The signal voltage ΔVu of the upper bit in the case of (1,1), (0,0) (1,1)
= 480 mV The amount of transition of bit line potential due to Cc ΔVc = 160 mV (0,1), signal voltage ΔVl (1,0) of lower bit in the case of (1,0)
= 160 mV (1,1), signal voltage ΔVu (1,1) of upper bit in the case of (0,0)
However, in practice, there is a variation in the ratio of the coupling capacitance Cc to the memory cell capacitance Cs. Now, the value of the coupling capacitance Cc varies by ± 25% (9
Assuming that fF ≦ Cc ≦ 15fF and Cs is always constant, ΔVc = 200 mV (in the case of +25%) = 120 mV (in the case of −25%) ΔV1 (1,0) = 240 mV (in the case of +25%) = 80 mV ( ΔVl (1,1) = 80 mV (in the case of + 25%) ΔVl (1,1) = 240 mV (in the case of −25%), and the signal voltage of the lower bit is obtained in both directions. Is reduced from 160 mV to 80 mV.

On the other hand, in the second embodiment of the present invention, C
When the value of c varies by ± 25%, the signal voltage ΔVu (1,0) of the upper bit in the case of (0,1), (1,0) is within the range of 80 mV <ΔVu (1,0) <160 mV. The ratio of the stray capacitance in the upper sub-bit line pair (SBLU, SBLBU) and the lower sub-bit line pair (SBLL, SBLBL) separated by the upper control signal TGU1 and the lower control signal TGL1 y:
1, 1 ≦ y). Now, let y = 3/2 so that ΔVu (1,0) = 120 mV. At this time, the write level to the memory cell corresponding to the four information of (0,0), (0,1), (1,0), (1,1) is the same as in the first embodiment. , As shown in FIG. Note that the division into y: 1 (1 ≦ y) is based on a method of giving a difference in the number of word lines in each divided area, and the same number of word lines in each divided area. For example, there is a method of providing a dummy capacitor on a line.

Next, in the second embodiment of the present invention, Δ
When Vu (1,0) = 120 mV, the memory cell capacity C
The ratio of the coupling capacitance Cc to s is set to Cc / Cs = 5/16 <1/3. At this time, assuming that the ratio of the coupling capacitance Cc to the memory cell capacitance Cs is always constant, the signal voltage ΔVu (1,0) of the upper bit in the case of (0,1), (1,0)
0) = 120 mV (1,1), (0,0), the signal voltage ΔVu (1,
1) = 480 mV The amount of transition of the bit line potential due to Cc ΔVc = 150 mV (0,1), the signal voltage ΔV1 (1,0) of the lower bit when (1,0)
= 180 mV (1,1), (0,0), the signal voltage ΔVu (1,
1) = 180 mV, and the signal voltage of the lower bit is higher than that of the upper bit. Then, as in the first embodiment, assuming that the coupling capacitance Cc varies by 25% in soil, ΔVc = 187.5 mV (in the case of +25%) = 112.5 mV (in the case of −25%) ΔVl (1, 0) = 255 mV (in the case of +25%) = 105 mV (in the case of −25%) ΔV1 (1,1) = 255 mV (in the case of +25%) = 105 mV (in the case of −25%). As compared with the second conventional example, the minimum value of the signal voltage of the lower bits increases from 80 mV to 105 mV, and the read margin when the upper bits and the lower bits are viewed in total is larger than that of the second conventional example. Become.

[0072]

As described above, the present invention has a coupling capacitance in the sense amplifier circuit, feeds back the sense result of the upper bit to the sense level of the lower bit, and performs a multi-value read operation. In a semiconductor memory device to be realized, even when the ratio between the coupling capacitance Cc and the memory cell capacitance Cs varies, it is possible to minimize the reduction in the signal voltage when the upper bits and the lower bits are viewed in total. it can.

The reasons are as follows: (1) In the rewriting operation of multi-level data, the ratio of the stray capacitance of the bit line of the upper bit side to the lower bit side is set to be less than the conventional example (<2); 2) By setting the ratio of the coupling capacitance to the memory cell capacitance Cs to be less than the conventional example, the signal voltage of the lower bit affected by the variation in the ratio between the coupling capacitance Cc and the memory cell capacitance Cs can be reduced from the conventional example. Is also to increase.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of a memory cell array unit and a sense amplifier unit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing operation waveforms at the time of reading data according to the first embodiment of the present invention.

FIG. 3 shows (0,0), (0,1), (1,0), (1,
FIG. 3 is a diagram showing an example of a write level to a memory cell corresponding to the four information items 1).

FIG. 4 is a diagram showing a circuit configuration (for one pair of main bit lines) of a memory cell array unit and a sense amplifier unit according to a second embodiment of the present invention;

FIG. 5 is a diagram showing operation waveforms at the time of reading data according to the second embodiment of the present invention.

FIG. 6 is a circuit configuration diagram of a memory cell array section and a sense amplifier section in the first conventional example.

FIG. 7 shows (0,0), (0,1), (1,0), (1,
FIG. 2 is a diagram showing write levels to memory cells corresponding to the four information 1).

FIG. 8 is a configuration diagram of a memory cell in a conventional example.

FIG. 9 is a diagram showing operation waveforms at the time of data reading in the first conventional example.

FIG. 10 is a diagram showing a circuit configuration (for one pair of main bit lines) of a memory cell array section and a sense amplifier section in a second conventional example.

FIG. 11 is a diagram showing operation waveforms at the time of data reading in the second conventional example.

[Explanation of symbols]

 Cb1 Floating capacitance generated on bit line in region 1 Cb2 Floating capacitance generated on bit line in region 2 Cc coupling capacitance

Claims (6)

[Claims] A first pair of complementary bit lines; a second pair of complementary bit lines; a first sense amplifier circuit connected to the first pair of bit lines; A second bit line pair, a second sense amplifier circuit, a transfer gate connecting the first bit line pair and the second bit line pair, a first bit line pair and the second bit line pair. And a coupling capacitor connected between the second bit line pair and writing different voltages to the first bit line pair and the second bit line pair. Is activated, and 4
In a semiconductor memory device that realizes multi-level operation by creating four voltage states and writing four states to memory cells, the ratio of the stray capacitance of the first bit line pair to the second bit line pair is less than 2. A semiconductor memory device characterized by setting: 2. A first complementary bit line pair, a second complementary bit line pair, a first sense amplifier circuit connected to the first bit line pair, and a second sense amplifier circuit connected to the first bit line pair. A second bit line pair, a second sense amplifier circuit, a transfer gate connecting the first bit line pair and the second bit line pair, a first bit line pair and the second bit line pair. And a coupling capacitor connected between the second bit line pair and writing different voltages to the first bit line pair and the second bit line pair. Is activated, and 4
In a semiconductor memory device that realizes a multi-level operation by creating four voltage states and writing four states to a memory cell, the ratio of the coupling capacitance to the memory cell capacitance is set to be less than (1/9). A semiconductor memory device characterized by the following. 3. A complementary first bit line pair, a complementary second bit line pair, a first sense amplifier circuit connected to the first bit line pair, and a second sense amplifier circuit connected to the first bit line pair. A second bit line pair, a second sense amplifier circuit, a transfer gate connecting the first bit line pair and the second bit line pair, a first bit line pair and the second bit line pair. And a coupling capacitor connected between the second bit line pair and writing different voltages to the first bit line pair and the second bit line pair. Is activated, and 4
In a semiconductor memory device that realizes multi-level operation by creating four voltage states and writing four states to memory cells, the ratio of the stray capacitance of the first bit line pair to the second bit line pair is less than 2. And the ratio of the coupling capacitance to the memory cell capacitance is (1/1 /
9) A semiconductor memory device characterized by being set to less than 9). 4. A hierarchized complementary main bit line pair and complementary sub bit line pair, a main sense amplifier circuit connected to the main bit line pair, and one main bit line pair.
Alternatively, a first sub-amplifier circuit in which a plurality of sub-bit line pairs are connected to the respective sub-bit line pairs and a first sub-bit line pair in which the sub-bit line pairs are separated into an upper sub-bit line pair and a lower sub-bit line pair And a second transfer gate in which a coupling capacitor connected between the main bit line pair and the sub bit line pair and a second transfer gate are connected in series for each of the sub sense amplifier circuits. Then, different voltages are written to the upper sub-bit line pair and the lower sub-bit line pair, and thereafter, the first transfer gate is activated, and four voltage states are set by charge distribution. A multi-level operation by writing four states to a memory cell, wherein the stray capacitance of the upper sub-bit line pair with respect to the lower sub-bit line pair A semiconductor memory device wherein the ratio is set to less than 2. 5. A hierarchized complementary main bit line pair and a complementary sub bit line pair, a main sense amplifier circuit connected to the main bit line pair, and one main bit line pair. Alternatively, a first sub-amplifier circuit in which a plurality of sub-bit line pairs are connected to the respective sub-bit line pairs and a first sub-bit line pair in which the sub-bit line pairs are separated into an upper sub-bit line pair and a lower sub-bit line pair And a second transfer gate in which a coupling capacitor connected between the main bit line pair and the sub bit line pair and a second transfer gate are connected in series for each of the sub sense amplifier circuits. Then, different voltages are written to the upper sub-bit line pair and the lower sub-bit line pair, and thereafter, the first transfer gate is activated, and four voltage states are set by charge distribution. Making, A semiconductor memory device for realizing multi-level operation by writing four states in a memory cell, wherein a ratio of the coupling capacity to the memory cell capacity is set to less than (1/3). . 6. A hierarchized complementary main bit line pair and a complementary sub bit line pair, a main sense amplifier circuit connected to the main bit line pair, and one main bit line pair. Alternatively, a first sub-amplifier circuit in which a plurality of sub-bit line pairs are connected to the respective sub-bit line pairs and a first sub-bit line pair in which the sub-bit line pairs are separated into an upper sub-bit line pair and a lower sub-bit line pair And a second transfer gate in which a coupling capacitor connected between the main bit line pair and the sub bit line pair and a second transfer gate are connected in series for each of the sub sense amplifier circuits. Then, different voltages are written to the upper sub-bit line pair and the lower sub-bit line pair, and thereafter, the first transfer gate is activated, and four voltage states are set by charge distribution. Making, In a semiconductor memory device realizing a multi-level operation by writing four states in a memory cell, a ratio of a stray capacitance of the upper sub-bit line pair to the lower sub-bit line pair is set to less than 2, and The ratio of the coupling capacitance to the memory cell capacitance is (1
/ 3) The semiconductor memory device is set to be less than (3).