JPH1173409A - Device and method for computing product sum - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a product sum arithmetic unit and a product sum computing method capable of efficiently executing processing in an optional ratio of three-dimensional graphics data to image encoding data. SOLUTION: The arithmetic unit has a graphics input buffer 1 for simultaneously outputting four graphics data at maximum, an image encoding input buffer 2 for simultaneously outputting two rows at maximum in 8×8 pixel data, a transposed buffer 4 for executing the simultaneous writing of two columns at maximum in the 8×8 pixel data and the simultaneous output of two rows at maximum in the 8 X 8 pixel data, a graphics output buffer 5 for simultaneously writing four graphics data at maximum, an image encoding output buffer 6 for simultaneously writing two rows at maximum in the 8×8 pixel data, and four product sum computing elements 3a to 3d capable of executing both of floating point product sum operation and integer product sum operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a product-sum operation apparatus and a product-sum operation method for encoding / decoding three-dimensional graphics and moving images which are regarded as important in multimedia signals.

[0002]

2. Description of the Related Art In recent years, the field of multimedia signal processing has been remarkably developed, and a great deal of development resources have been invested. Among them, a large number of hardware for performing a product-sum operation required for encoding a natural image and processing for three-dimensional graphics have been developed. In general, compression algorithms based on DCT are often used for encoding a natural image, and this operation mainly requires obtaining a product of an integer 4 × 4 matrix parameter and a 4-column vector. In addition, an operation for three-dimensional graphics requires obtaining a product of a 4 × 4 matrix parameter of a floating-point number using a homogeneous coordinate system and a 4-column vector.

A conventional product-sum calculator constituting a conventional product-sum operation device will be described below. FIG. 7 is a block diagram showing a floating-point product-sum operation unit as a conventional product-sum operation unit. In FIG. 7, reference numeral 31 denotes a multiplicand input register for storing a multiplicand of a floating-point operation by dividing it into an exponent and a mantissa, 32 denotes a multiplier input register for storing a multiplier by dividing the exponent and the mantissa similarly to the multiplicand input register 31, and 13 denotes a multiplicand An exponent adder for inputting the exponent stored in the input register 11 and the exponent stored in the multiplier input register 12 and performing addition, 14 is a mantissa stored in the multiplicand input register and the multiplier input register 1
A partial product generator for generating a partial product of multiplication by inputting the mantissa stored in 2 and an input of a result of exponential addition in the exponent adder 13 and an operation result stored in an output register 22 described later. An exponential comparator 16 for calculating the difference between the exponents and comparing the exponents, and a partial product addition value (that is, a product as a result of calculating the mantissa of the multiplicand × the mantissa of the multiplier) by adding the partial products input from the partial product generator 14. The partial product adders 17 and 18 receive the partial product addition value from the partial product adder 16 and the mantissa from the output register 22, respectively, and select according to the comparison result (that is, the exponent difference) in the exponent comparator 15. , A shifter 19 for shifting the data output by the selector 17 in accordance with the comparison result of the exponent comparator 15, and a selector 20 for outputting the data of the shifter 19 and the selector 18.
Adder that inputs the output data of
1 is a normalizer for inputting the exponent addition value output from the exponent adder 13 and the mantissa addition value output from the adder 20 to normalize a floating-point number, and 22 is output from the normalizer 21 This is an output register that holds a normalized floating-point number divided into an exponent and a mantissa.

[0004] The operation of the conventional product-sum calculator configured as described above will be described with reference to FIG. FIG. 8 is a flowchart for explaining the operation of the conventional floating-point multiply-add unit.

In FIG. 8, first, a multiplier and a multiplicand are input to a multiplicand input register 11 and a multiplier register 12 (S11). Next, the exponent adder 13 reads the exponent stored in the multiplicand input register 11 and the exponent stored in the multiplier input register 12, and performs addition (S12). At the same time, the partial product generator 14 inputs the mantissa stored in the multiplicand input register 11 and the mantissa stored in the multiplier input register 12 to generate a partial product for multiplication (S12).
Next, the partial product adder 16 adds all the partial products generated by the partial product generator 14 to obtain a partial product addition value (S13).
Further, the exponent comparator 15 obtains a difference between the exponent output from the exponent adder 13 and the exponent stored in the output register 22 as a sum for accumulation as an exponent difference, and compares them (S1).
3).

Next, as a result of the comparison in step 13, if the exponent output from the exponent adder 13 is large (S14), the selector 17 selects the mantissa from the output register 22 having the small exponent, and the shifter 19 compares the exponent. The shift is performed according to the exponent difference output from the unit 15 (S15), and the selector 18 selects the partial product addition value output from the partial product adder 16. When the exponent from the output register 22 is large (S14), the selector 17 selects the partial product addition value output from the partial product adder 16, and shifts the shifter 19 according to the exponent difference output from the exponent comparator 15 (S16). ) And selector 1
8 selects a mantissa of a floating-point number having a large exponent.

Next, the mantissa output from the shifter 19 and the mantissa output from the selector 18 are added by the adder 20 (S17). Next, the exponent output from the exponent adder 13 and the mantissa output from the adder 20 are input to the normalizer 21 for normalization (S18), and the exponent and the mantissa output from the normalizer 21 are performed. Is stored in the output register 22 (S19).

The conventional multiply-accumulate device includes the above-described multiply-accumulate unit for floating-point numbers and a general integer multiply-accumulate unit. In general, a configuration is used in which a dedicated product-sum calculator is used for the product-sum operation.

[0009]

However, in the conventional product-sum operation apparatus, when multiplying a 4 × 4 matrix and a 4-element column vector used in image coding and three-dimensional graphics, the image is calculated. An integer sum-of-products unit is used for encoding, and a floating-point sum-of-products unit is used for three-dimensional graphics. Therefore, the floating-point sum-of-products unit is mostly used when handling data with a large amount of image data. Therefore, there is a problem that the upper limit of the overall processing capacity is determined by the integer product-sum operation unit. On the other hand, when the amount of three-dimensional graphics data is large, the opposite occurs, and the overall processing capacity is limited by the floating-point multiply-accumulate unit. In addition, the conventional floating-point multiply-accumulate unit requires comparison and selection processing after addition of partial products in order to support general multiply-accumulate operations with an arbitrary number of terms. In order to improve the speed, there is a problem that a lot of hardware and power consumption are consumed. Furthermore, there is a great difference in accuracy between data for image coding and data for three-dimensional graphics,
When an operation for image encoding is performed by sharing the floating-point multiply-accumulate unit, there is a problem that many circuits are wasted without being used.

In the product-sum operation apparatus and the product-sum operation method, data for three-dimensional graphics (hereinafter referred to as "3
Dimensional graphics data) and data for image coding (hereinafter referred to as "image coding data").
Can be processed efficiently even when given at an arbitrary ratio, and the product-sum operation can be performed efficiently even for integers with different precisions. There is a demand for shrinking high-speed and low hardware.

The present invention can efficiently perform processing even when three-dimensional graphics data and image encoding data are given at an arbitrary ratio, and can process integers having different precisions. The product-sum operation can be performed efficiently,
Further, a multiply-accumulate operation device capable of reducing the number of hardware paths at high speed by shortening the operation path, and efficiently processing even when data for three-dimensional graphics and data for image encoding are given at an arbitrary ratio. To provide a multiply-accumulate operation method in which multiply-accumulate operations are efficiently performed even for integers having different precisions, and furthermore, a path for the operation is shortened to reduce the number of hardware at high speed. And

[0012]

In order to solve the above-mentioned problems, a multiply-accumulate operation device according to the present invention comprises: a graphics input buffer having a function of simultaneously outputting at most four pieces of three-dimensional graphics data; An image encoding input buffer having a function of simultaneously outputting at most two rows of x8 pixel data, a function of simultaneously writing at most two columns of 8x8 pixel data, and at most two rows of 8x8 pixel data A transposition buffer having a function of simultaneously outputting data, a graphics output buffer having a function of simultaneously writing at most four three-dimensional graphics data, and a function of simultaneously writing at most two rows of 8 × 8 pixel data The image encoding output buffer having the functions of: a floating-point multiply-accumulate operation and an integer multiply-accumulate operation; Graphics data from the encoded input buffer, and inputs the data for picture coding and a structure having a four multiplier-adder for outputting graphics data, the pixel data.

As a result, a product-sum operation device capable of efficiently performing processing even when three-dimensional graphics data and image coding data are given at an arbitrary ratio is obtained.

[0014] In addition, a product-sum operation method according to the present invention for solving the above-mentioned problem uses a product-sum operation device using four product-sum operation units capable of performing either floating-point product-sum operation or integer product-sum operation. An arithmetic method, comprising: an input step of inputting a multiplicand and a multiplier; a maximum exponent detecting step of adding exponents to detect a maximum exponent; a mantissa partial product generating step of generating a partial product of a floating-point mantissa; An integer partial product generation step of generating a partial product of two pairs of integers having a small number into an upper bit area and a lower bit area, and a partial product addition step of adding the generated partial products to obtain a partial product addition value; An exponent difference calculating step of calculating an exponent difference that is a difference between the detected maximum exponent and an exponent corresponding to the generated partial product; a shifting step of shifting a partial product addition value based on the calculated exponent difference; An accumulating step of accumulating the divided product addition value to obtain an accumulative value; a normalizing step of normalizing according to the maximum exponent and the accumulative value; and a holding step of holding output data of the normalizing step. In the floating-point multiply-accumulate operation, the input step and the addition detection step are repeated four times, and the mantissa partial product generation step, the partial product addition step, the exponent difference calculation step, the shift step, and the accumulation step are repeated four times. At the time of sum operation, the input step is 4
It has a process of repeating an integer partial product generation step, a partial product addition step, and an accumulation step four times.

Thus, even when the data for three-dimensional graphics and the data for image encoding are given at an arbitrary ratio, the processing can be performed efficiently. A product-sum operation method with less wear can be obtained.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention provides a graphics input buffer having a function of simultaneously outputting at most four pieces of three-dimensional graphics data, and a large number of 8 × 8 pixel data. An image coding input buffer having a function of simultaneously outputting two rows, a function of simultaneously writing at most two columns of 8 × 8 pixel data, and a function of 8 × 8
A transposition buffer having a function of simultaneously outputting at most two rows of pixel data; a graphics output buffer having a function of simultaneously writing at most four three-dimensional graphics data; An image-encoded output buffer having a function of writing two lines at the same time, and a floating-point multiply-add operation and an integer multiply-add operation can be operated. Data and image coding data to be input to output graphics data and pixel data, and four sum-of-products arithmetic units. The three-dimensional graphics data and the image coding data Is given at an arbitrary ratio, the functions of the four sum-of-products arithmetic units are switched and the processing is performed efficiently. A.

According to a second aspect of the present invention, in the first aspect of the invention, the multiply-accumulate unit performs digit alignment by a maximum exponent of four product terms at the time of floating-point arithmetic, and a multiplier at the time of integer arithmetic. The upper and lower bits of the partial product adder are separated in the partial product adder, and different numerical values are input to the upper and lower bits, and the required sign extension is performed. When three-dimensional graphics data and image coding data that are greatly different from each other are given at an arbitrary ratio, the function of the four product-sum calculators is switched, and the processing is performed efficiently.

According to a third aspect of the present invention, in the first aspect of the invention, the multiply-accumulate unit includes a multiplicand input register and a multiplier input register for continuously inputting four sets of floating-point numbers, and four sets of An exponent adder that adds each set of exponents when a floating point number is input, an exponent buffer that temporarily stores the largest exponent of the exponent, and a mantissa of four sets of floating point numbers for each set , A partial product generator that generates a partial product for multiplication by sequentially inputting the partial products, a partial product adder that adds partial products output from the partial product generator to obtain a partial product addition value, and a maximum exponent. A subtractor that subtracts the exponent corresponding to the divided partial product to obtain an exponent difference, a shifter that shifts the partial product addition value output from the partial product adder in the direction of borrow according to the exponent difference, and a shifter sequentially output from the shifter Accumulation that sums partial product addition values to obtain an accumulated value And a normalizer that performs normalization according to the maximum exponent and the accumulated value output from the accumulator, and an output register that holds output data of the normalizer, a multiplicand, By finding the maximum exponent when inputting the multiplier and shifting it before accumulation, there is no need to perform processes such as selection and comparison during the repetition of the product-sum operation.
This has the effect that high-speed processing is performed with a small amount of hardware.

According to a fourth aspect of the present invention, in the third aspect of the present invention, the partial product generator converts two pairs of input integers into an upper bit area and a lower bit area of the partial product adder during an integer operation. The multiplicand of a pair of input integers assigned to the upper bit area is divided and input, a sign is extended by masking a portion corresponding to the lower bit area, and another pair of input integers assigned to the lower bit area is assigned. The input integer masks the part corresponding to the high-order bit area and performs sign extension. This has the effect that the product-sum operation can be performed efficiently even for integers that differ greatly in precision from floating-point numbers. Have.

According to a fifth aspect of the present invention, there is provided a multiply-accumulate method using four multiply-accumulate operators capable of performing either a floating-point multiply-accumulate operation or an integer multiply-accumulate operation. , An exponent detection step for adding exponents to detect a maximum exponent, a mantissa partial product generation step for generating a floating-point mantissa partial product, and a low-precision two-pair integer partial product Generating an integer partial product by dividing the upper bit area and the lower bit area into
A partial product addition step of adding the generated partial products to obtain a partial product addition value; an exponent difference calculation step of calculating an exponent difference that is a difference between the detected maximum exponent and an exponent corresponding to the generated partial product; Shift step for shifting the partial product addition value based on the calculated exponent difference, accumulation step for accumulating the shifted partial product addition value to obtain an accumulated value, and normalization for normalizing according to the maximum exponent and the accumulated value. And a holding step for holding the output data of the normalizer. At the time of the floating-point product-sum operation, the input step and the addition detection step are repeated four times, and a mantissa partial product generation step, a partial product addition step, The exponent difference calculation step, the shift step, and the accumulation step are repeated four times. At the time of the integer product-sum operation, the input step is repeated four times, and the integer partial product generation step and the partial product addition step are performed. The accumulation step is repeated four times, and the functions of the four sum-of-products units are switched when the data for three-dimensional graphics and the data for image encoding are given at an arbitrary ratio. The processing is performed efficiently, and the operation path (critical path)
Has the effect of reducing hardware speed and reducing hardware.

According to a sixth aspect of the present invention, in the invention of the fifth aspect, in the integer partial product generating step, at the time of an integer operation, two pairs of input integers are used in an upper bit area and a lower bit area of a partial product adder. The sign multiplication is performed by masking the portion corresponding to the lower region for the multiplicand of a pair of input integers assigned to the upper bit region, and performing another sign assignment to the lower bit region. Input integers are used to generate partial products by masking the part corresponding to the high-order bit area and performing sign extension, and efficiently multiply and accumulate even integers that differ greatly in precision from floating-point numbers. This has the effect of performing calculations.

Hereinafter, an embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG. (Embodiment) FIG. 1 is a block diagram showing a product-sum operation device according to an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a graphics input buffer, 2 denotes an image coding input buffer, 3a to 3d denote product-sum operators, 4 denotes a transposition buffer, 5 denotes a graphics output buffer, and 6 denotes an image coding output buffer.

The functions and the like of the product-sum operation device configured as described above will be described. The graphics input buffer 1 supplies three-dimensional graphics data.
It has a function to output four vertex data simultaneously. The image encoding input buffer 2 supplies image encoding data (that is, pixel data), and has a function of simultaneously outputting two rows of 8 × 8 pixel data. These buffers 1 and 2 are connected to the respective product-sum calculators 3a to 3d. The product-sum calculators 3a to 3d select one of the graphics input buffer 1, the image coding input buffer 2, and the transposition buffer 4, and receive input data from the selected buffer. The product-sum calculators 3a to 3d select one of the graphics output buffer 5, the image encoding output buffer 6, and the transposition buffer 4, and write the output data to the selected buffer. Transposition buffer 4 is 8 × 8
It has a function of simultaneously outputting two rows of pixel data and simultaneously inputting two columns. The graphics output buffer 5 has a function of writing four inputs at the same time, and the image encoding output buffer 6 has a function of writing two inputs at the same time.

Next, the operation of the product-sum operation device according to the embodiment of the present invention will be described with reference to FIG. FIG.
(A), (b), and FIGS. 3 (a) and (b) are explanatory diagrams of the operation of the product-sum operation device according to the embodiment of the present invention. In the present embodiment, it is assumed that the data is supplied at an arbitrary ratio between the data for three-dimensional graphics and the data for image encoding. For this assumption, four product-sum operation units 3a
The functions of the product-sum calculators 3a to 3d are set at the respective ratios of 4: 0, 3: 1, 2: 2, and 0: 4 by using to 3d to indicate that each of them can be executed.

When processing only three-dimensional graphics data, as shown in FIG. 2A, functions are assigned to the product-sum calculators 3a to 3d in a 4: 0 combination. At this time, the graphics input buffer 1 has four product-sum calculators 3
Four data are simultaneously supplied to a to 3d, and the product-sum calculators 3a to 3d perform calculations for three-dimensional graphics. The results of the operations are simultaneously written to the graphics output buffer 5, respectively.

When the data for three-dimensional graphics and the data for image encoding are mixed, the assignment of the product-sum calculators 3a to 3d is changed as required. Multiply-accumulate operators 3a-3
When the assignment of d is 3: 1 as shown in FIG. 2B, the graphics input buffer 1 has three product-sum calculators 3a to 3a.
Vertex data (graphics data) is output to 3c. The image encoding input buffer 2 supplies data to one product-sum calculator 3d. As for the graphics data, each product-sum operation unit 3
a to 3c each perform an operation and write the result to the graphics output buffer 5. For the data for image encoding, one-dimensional DCT operation is performed by the product-sum operation unit 3 d, and the operation result is stored in the transposition buffer 4. One-dimensional D for 8 rows
After the CT calculation is completed, the transposed data is input from the transposition buffer 4, one-dimensional DCT calculation is further performed for eight columns, and the calculation results are sequentially written to the image encoding output buffer 6.

The assignment of the sum-of-products calculators 3a to 3d is shown in FIG.
In the case of 2: 2 as in (a), the graphics input buffer 1 supplies data to the two sum-of-products calculators 3a and 3b. The image encoding input buffer 2 is a product-sum calculator 3d
And the data output from the product-sum operation unit 3 d is written into the transposition buffer 4. Transpose buffer 4
Is input to the product-sum calculator 3c,
The result is written to the image encoding output buffer 6.

For graphics data:
Similarly to the case of 0, each of the product-sum calculators 3a and 3b performs a calculation, and writes the calculation result to the graphics output buffer 5. For the image encoding data, one-dimensional CDT operation is performed by one product-sum operation unit 3d, and the operation result is stored in the transposition buffer 4. After the one-dimensional DCT operation for one block is completed, the other product-sum operation unit 3c inputs data from the transposition buffer 4 and starts the one-dimensional DCT operation for the column components. The operation results of the one-dimensional DCT operation are sequentially written to the image encoding output buffer 6. When this column component operation is being performed, the one-dimensional DCT operation of the row component for the next block is simultaneously performed by one product-sum operation unit 3d.
Executed in

When all the data is image encoding data, the assignment of the product-sum calculators 3a to 3d is set to 4: 0 as shown in FIG. 3B. At this time, the row component data is output from the image encoding input buffer 2 to the two product-sum calculators 3b and 3d, being divided into even rows and odd rows. This 2
Each of the product-sum calculators 3 b and 3 d performs a one-dimensional DCT calculation, and the calculation result is stored in the transposition buffer 4.
After the one-dimensional DCT operation on the row components of one block is completed, the remaining two multiply-accumulate units 3a and 3c take out the data from the transposition buffer 4 and perform the one-dimensional D-operation on the column components.
The CT operation is started for even and odd rows, respectively, and the operation result is written to an image encoding output buffer.

In this manner, when the three-dimensional graphics data and the image encoding data are supplied at an arbitrary ratio, the processing can be efficiently performed.

FIG. 4 is a block diagram showing the product-sum calculators 3a, 3b, 3c, and 3d constituting the product-sum calculator of FIG. In FIG. 4, 31 is a multiplicand input register, 32 is a multiplier input register, 33 is an exponent adder, 34 is a partial product generator, 35 is an exponent buffer, 36 is a partial product adder, 37
Is a subtractor, 38 is a shifter, 39 is an accumulator, 40 is a normalizer, and 41 is an output register.

The function and the like of the product-sum calculator configured as described above will be described. The multiplicand input register 31 stores the multiplicand, is externally written, and stores each numerical value separately as an exponent and a mantissa. Here, the multiplicand is specifically each element of the four-column vector. The multiplier input register 32 stores the multiplier, and stores the values of the row components of the matrix parameters separately for exponents and mantissas. Here, specifically, the multiplier is an element of a 4 × 4 matrix and is input for each row. The exponent adder 33 adds the exponent stored in the multiplicand input register 31 and the exponent stored in the multiplier input register 32.

The partial product generator 34 generates a partial product for multiplication according to the mantissa stored in the multiplicand input register 31 and the mantissa stored in the multiplier input register 32. The exponent buffer 35 stores the exponent output from the exponent adder 33 while obtaining the maximum exponent among the exponents. The partial product adder 36 adds the partial products input from the partial product generator 34 and outputs a partial product addition value. The subtracter 37 inputs the maximum exponent output from the exponent buffer 35 and the exponent corresponding to the partial product for which the current calculation is being performed, and outputs the difference (exponent difference). The shifter 38 is a partial product adder 36
Subtracting the product of the mantissas (partial product addition value) output from
Shift according to the exponent difference output from. Accumulator 39
Adds the mantissa output from the shifter 38 and the mantissa output from the accumulator 39. The normalizer 40 performs a normalization process on the maximum exponent output from the exponent buffer 35 and the mantissa output from the accumulator 39. Output register 4
1 stores the normalized value output from the normalizer 40 by dividing it into an exponent and a mantissa.

The operation of the product-sum calculator of FIG. 4 having the above-described configuration, functions, and the like will be described with reference to FIG. FIG. 5 is a flowchart showing the operation of the product-sum operation unit of FIG.

In FIG. 5, first, a numerical value is input to the storage location of the exponent 0 and the mantissa 0 of the multiplicand input register 31. Similarly, a numerical value is input to the storage location of the exponent 0 and the mantissa 0 of the multiplier input register 32. This is performed (S1, input step). Next, the exponent 0 input to the multiplicand input register 31 and the exponent 0 input to the multiplier input register 32 are added by the exponent adder 33, and the sum is compared with the maximum exponent in the exponent buffer 35, and the result is larger. The other exponent is stored as the maximum exponent (S2, maximum exponent detection step).

Steps 1 and 2 are repeated four times, and the largest exponent corresponding to the four partial products is stored in the storage location of the largest exponent.

Next, the partial product generator 34 generates a partial product according to the mantissa 0 input to each of the multiplicand input register 31 and the multiplier input register 32 (S3, partial product generation step), and all the partial products are added. The result is a partial product addition value (S4, partial product addition step). This partial product addition value is output from the partial product adder 36. Next, an exponent difference, which is a difference between the maximum exponent obtained in step 2 and the exponent corresponding to the currently calculated partial product, is obtained by the subtractor 37 (S5, exponent difference calculating step), and the shifter is operated according to the exponent difference. Numeral 38 shifts the partial product addition value output from the partial product adder 36 rightward (carrying direction) (S6, shift step). Next, the accumulator 39 accumulates the partial product addition values shifted and digitized in step 6 (S7,
Accumulation step).

Steps 3 to 7 are repeated four times. The sum of the four partial product addition values calculated in this way is normalized by the normalizer 40 (S8, normalization step) and stored in the output register (S9, storage step).

FIG. 6 shows a partial product generator 3 of the product-sum operation unit in FIG.
FIG. In FIG. 6, reference numeral 341 denotes an input register for storing a mantissa of a multiplicand; 342, an input register for storing a mantissa of a multiplier;
41, 342, and receives a value from a partial product register 34 described later.
The combinational circuit 344 for outputting a value to 4 is a partial product register for storing the value output from the combinational circuit 343.

The partial product generator 34 configured as described above
The operation when two multiplications are performed simultaneously will be described. (Equation 1) shows a logical expression realized by the combination circuit 343 of FIG.

[0041]

(Equation 1)

In (Equation 1), it is assumed that the multiplier and the multiplicand in the case of a floating-point number are 32 bits, and in the case of an integer operation, each are 16 bits. “&” Represents a logical AND of a vector in bits, and “&&” represents each bit of the vector and 1
Represents the logical AND of a bit with a binary number, and the result is a vector. Here, for 0 ≦ n, m <31, p (n) is a 32-bit vector, P (n, m) is the m-th bit of the n-th vector,
pp (n) is the n-th 63-bit partial product to be output, PP (n,
m) is the mth bit of the nth partial product, and par (m) is the mth bit of the multiplier.
The ith bit, var, is the multiplicand, and var (m) is the m-th bit of the multiplicand.

K represents the number of bits of the input var, and k = 32 for floating-point arithmetic and k = 16 for integer arithmetic.
And Further, lwb and upb are constants to which different values are assigned at the time of integer operation and floating point operation, respectively. At the time of integer operation, lwb = 0x0000FFFF and upb = 0xFFFF0000 are assigned. At the time of floating point operation, lwb = 0xFFFFFFFF and upb =
0xFFFFFFFF is assigned. The partial product generator 34 always inputs the values given to the input registers 341 and 342 to the combination circuit 343 and stores the output of the combination circuit 343 in the partial product register 344 at a predetermined timing.

The operation when two multiplications are performed simultaneously using the partial product generator 34 will be further described.
The area for each mantissa of the multiplicand input register 31 and the multiplier input register 32 in FIG. 4 is divided into upper bits and lower bits, and different variables are input. In the example of FIG. 6, A × A ′ and B × B ′ are calculated simultaneously. The partial product generator 34 receives the respective mantissas divided into the upper bits and the lower bits as described above. Here, a partial product is generated by the combination circuit 343. At this time, the partial products 0 to 15 of the partial product register 344 store the partial products for B × B ′ on the lower bit side.
6 to 31 store a partial product for A × A ′ on the upper bit side. Here, since the integer multiplication is performed, the operation block relating to the exponent of the floating-point operation in FIG. 4 does not function. Therefore, the shifter 38 continues to send the value as it is to the accumulator 39. In this way, the sum of two multiplications and their four partial products can be calculated simultaneously. Obviously, the features of the partial product generator 34 can also be realized by known means for reducing the number of partial products.

As described above, according to the present embodiment, by providing four multiply-accumulate units capable of performing both the floating-point multiply-add operation and the integer multiply-add operation, the three-dimensional graphics When the data and the image coding data are given at an arbitrary ratio, the functions of the four product-sum calculators can be switched to perform the processing efficiently. In addition, when a multiplicand or a multiplier is input, a maximum exponent is obtained and shifted before accumulation, so that it is not necessary to perform processes such as selection and comparison during repetition of a multiply-accumulate operation, so that high-speed processing is performed with a small amount of hardware. be able to. Further, at the time of integer operation, the partial product generator 34 inputs two pairs of input integers into the upper bit area and the lower bit area of the partial product adder, and inputs the pair of input integers. For the multiplicand, sign extension is performed by masking the portion corresponding to the lower bit region, and another pair of input integers assigned to the lower bit region is masked for the portion corresponding to the upper bit region to perform sign extension. A product-sum operation can be efficiently performed even on an integer having a precision significantly different from that of a floating-point number.

[0046]

As described above, according to the multiply-accumulate operation device according to the first aspect, a graphics input buffer having a function of simultaneously outputting at most four data for three-dimensional graphics, and an 8 × 8 buffer An image encoding input buffer having a function of simultaneously outputting at most two rows of pixel data;
A transposition buffer having a function of simultaneously writing at most two columns of 8 × 8 pixel data and a function of simultaneously outputting at most two rows of 8 × 8 pixel data, and at most four pieces of three-dimensional graphics data A graphics output buffer having a function of writing at the same time, an image encoding output buffer having a function of writing at most two rows of 8 × 8 pixel data at the same time, and an operation of either the floating-point multiply-add operation or the integer multiply-add operation And a graphics input buffer, graphics data from the image encoding input buffer, and four multiply-accumulate units for inputting image encoding data and outputting graphics data and pixel data. When the data for three-dimensional graphics and the data for image encoding are given at an arbitrary ratio, the functions of four product-sum calculators An advantageous effect that it is possible to perform efficient processing is obtained by switching.

According to the invention described in claim 2, according to claim 1,
In the invention described in the above, the multiply-accumulate unit performs digit alignment by the largest exponent of the four product terms at the time of floating-point arithmetic, and at the time of integer arithmetic, the upper bits of the partial product adder in the partial product addition for the multiplier. By separating the lower bits, inputting different numerical values to the upper bits and the lower bits, and performing the required sign extension, the data for three-dimensional graphics and the data for image encoding, which differ greatly in accuracy, can be arbitrarily selected. When given by the ratio, the function of the four sum-of-products arithmetic units is switched, and the advantageous effect that the processing is performed efficiently is obtained.

According to the third aspect of the present invention, the first aspect is provided.
In the invention described in (1), the multiply-accumulate unit includes a multiplicand input register and a multiplier input register for continuously inputting four sets of floating-point numbers, and adding the exponents of each set when the four sets of floating-point numbers are input. Adder for performing exponentiation, an exponent buffer for temporarily obtaining the largest exponent of exponents, and a part for sequentially inputting the mantissas of four sets of floating-point numbers for each set to generate a partial product for multiplication A product generator, and a partial product adder that adds partial products output from the partial product generator to obtain a partial product addition value,
A subtracter that subtracts an exponent corresponding to a partial product generated from a maximum exponent to obtain an exponent difference, a shifter that shifts a partial product addition value output from the partial product adder in a downflow direction according to the exponent difference, and a shifter An accumulator that obtains an accumulated value by summing partial product addition values sequentially output from the accumulator, a normalizer that normalizes according to the maximum exponent and the accumulated value output from the accumulator,
By having an output register that holds the output data of the normalizer, the maximum exponent is obtained when the multiplicand and multiplier are input and shifted before accumulation, so that processing such as selection and comparison can be performed during repetition of the product-sum operation. You do n’t have to do that,
An advantageous effect that high-speed processing can be performed with a small amount of hardware is obtained.

According to the invention set forth in claim 4, according to claim 3,
In the invention described in 1 above, the partial product generator inputs two pairs of input integers into an upper bit region and a lower bit region of the partial product adder at the time of integer operation, and inputs one pair of integers assigned to the upper bit region. The multiplicand of the input integer is sign-extended by masking the portion corresponding to the lower bit area, and the other pair of input integers assigned to the lower bit area is masked by coding the part corresponding to the upper bit area. By performing the extension, it is possible to obtain an advantageous effect that a product-sum operation can be efficiently performed even on an integer whose precision is significantly different from that of a floating-point number.

According to a fifth aspect of the present invention, there is provided a multiply-accumulate method using four multiply-accumulate operators capable of performing either a floating-point multiply-add operation or an integer multiply-add operation. An input step of inputting an exponent and a multiplier; a maximum exponent detection step of adding an exponent to detect a maximum exponent; a mantissa partial product generation step of generating a partial product of a floating-point mantissa;
An integer partial product generating step of generating a partial product of two pairs of integers with low precision into an upper bit area and a lower bit area, and a partial product adding step of adding the generated partial products to obtain a partial product added value An exponent difference calculating step of calculating an exponent difference that is a difference between the detected maximum exponent and an exponent corresponding to the generated partial product; a shifting step of shifting a partial product addition value based on the calculated exponent difference; An accumulating step of accumulating the partial product addition value to obtain an accumulated value, a normalizing step of normalizing according to a maximum exponent and the accumulated value, and a holding step of holding output data of the normalizer. In the floating-point multiply-add operation, the input step and the addition detection step are repeated four times, and the mantissa partial product generation step, the partial product addition step, the exponent difference calculation step, the shift step, the accumulation step, At the time of the integer product-sum operation, the input step is repeated four times, and the integer partial product generation step, the partial product addition step, and the accumulation step are repeated four times. 4 if data and data are given in any ratio
The functions of the multiply-accumulate units are switched to perform the processing efficiently, and the advantageous effect of reducing the number of hardware at high speed by shortening the operation path (critical path) is obtained.

According to the invention described in claim 6, according to claim 5,
In the invention described in the above, in the integer partial product generation step, at the time of integer operation, two pairs of input integers are separately input into an upper bit area and a lower bit area of the partial product adder, and 1 is assigned to the upper bit area. The multiplicand of a pair of input integers is sign-extended by masking the portion corresponding to the lower bit region, and the other pair of input integers assigned to the lower bit region is masked by coding the portion corresponding to the upper bit region. By performing the partial product generation by performing the extension, there is obtained an advantageous effect that the product-sum operation is efficiently performed even for an integer having a precision significantly different from that of the floating-point number.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a product-sum operation device according to a first embodiment of the present invention;

FIG. 2A is an explanatory diagram of an operation of the product-sum operation device according to the first embodiment of the present invention; FIG. 2B is an explanatory diagram of an operation of the product-sum operation device according to the first embodiment of the present invention;

FIG. 3A is an explanatory diagram of an operation of the product-sum operation device according to the first embodiment of the present invention; FIG. 3B is an explanatory diagram of an operation of the product-sum operation device according to the first embodiment of the present invention;

FIG. 4 is a block diagram showing a product-sum operation unit included in the product-sum operation device of FIG. 1;

FIG. 5 is a flowchart showing the operation of the product-sum operation unit in FIG. 4;

FIG. 6 is a block diagram showing a partial product generator of the product-sum operation unit in FIG. 4;

FIG. 7 is a block diagram showing a floating-point product-sum operation unit as a conventional product-sum operation unit;

FIG. 8 is a flowchart for explaining the operation of a conventional floating-point multiply-accumulate unit;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Graphics input buffer 2 Image encoding input buffer 3a, 3b, 3c, 3d Multiply-accumulator 4 Transpose buffer 5 Graphics output buffer 6 Image encoding output buffer 31 Multiplicand input register 32 Multiplier input register 33 Exponent adder 34 Part Product generator 35 Exponent buffer 36 Partial product adder 37 Subtractor 38 Shifter 39 Accumulator 40 Normalizer 41 Output register 341 342 Input register 343 Combination circuit 344 Partial product register

Claims (6)

[Claims] 1. A graphics input buffer having a function of simultaneously outputting at most four pieces of three-dimensional graphics data, and an image encoding having a function of simultaneously outputting at most two rows of 8.times.8 pixel data. Input buffer and 8
A transposition buffer having a function of simultaneously writing at most two columns of x8 pixel data and a function of simultaneously outputting at most two rows of 8x8 pixel data, and at most four three-dimensional graphics data simultaneously A graphics output buffer having a function of writing, an image encoding output buffer having a function of writing at most two rows of 8 × 8 pixel data at the same time, and an arithmetic operation using either a floating-point multiply-add operation or an integer multiply-add operation The graphics input buffer, graphics data from the image encoding input buffer, and four multiply-accumulate units for inputting image encoding data and outputting graphics data and pixel data. A sum-of-products arithmetic unit, characterized in that: 2. The multiply-accumulate unit performs digit alignment by the largest exponent of four product terms during a floating-point operation, and performs upper-order bits of a partial product adder in a partial product addition for a multiplier during an integer operation. 2. The multiply-accumulate operation device according to claim 1, wherein the lower bits are separated, different numerical values are input to the upper bits and the lower bits, and necessary sign extension is performed. 3. The multiply-accumulate unit includes a multiplicand input register and a multiplier input register for continuously inputting four sets of floating-point numbers, and an exponent of each set when the four sets of floating-point numbers are input. An exponent adder for performing addition, an exponent buffer for obtaining and temporarily storing the largest exponent of the exponents, and sequentially inputting the mantissas of the four sets of floating-point numbers for each set to form a partial product for multiplication. A partial product generator to generate, a partial product adder that adds partial products output from the partial product generator to obtain a partial product addition value, and subtracts an exponent corresponding to the generated partial product from the maximum exponent A subtracter that obtains an exponent difference, a shifter that shifts the partial product addition value output from the partial product adder in the direction of borrow according to the exponent difference, and a partial product addition value that is sequentially output from the shifter. An accumulator for summing to obtain an accumulated value; 2. The normalizer according to claim 1, further comprising: a normalizer that performs normalization according to an exponent and an accumulated value output from the accumulator; and an output register that holds output data of the normalizer. Product-sum operation unit. 4. The partial product generator inputs two pairs of input integers into an upper bit area and a lower bit area of a partial product adder at the time of an integer operation, and inputs a pair of integers assigned to the upper bit area. The multiplicand of the input integer is sign-extended by masking the portion corresponding to the lower bit area, and the other pair of input integers assigned to the lower bit area is masked by coding the part corresponding to the upper bit area. 4. The multiply-accumulate operation device according to claim 3, wherein extension is performed. 5. A multiply-and-accumulate method using four multiply-and-accumulate calculators capable of performing both a floating-point multiply-add operation and an integer multiply-add operation, and an input step of inputting a multiplicand and a multiplier. A maximum exponent detection step of adding an exponent to detect a maximum exponent, a mantissa partial product generation step of generating a partial product of a floating-point mantissa, and a low-precision partial product of two pairs of integers in a high-order bit area and a low-order bit. An integer partial product generation step for generating the partial product separately for each area; a partial product addition step for adding the generated partial products to obtain a partial product addition value; an exponent corresponding to the detected maximum exponent and the generated partial product An exponent difference calculating step of calculating an exponent difference that is a difference between the two, a shift step of shifting the partial product addition value based on the calculated exponent difference, and accumulating the shifted partial product addition value. The value An accumulating step, a normalizing step of performing normalization according to the maximum exponent and the accumulated value, and a holding step of holding output data of the normalizer. Step and the addition detection step are repeated four times, and the mantissa partial product generation step, the partial product addition step, the exponent difference calculation step, the shift step, and the accumulation step are repeated four times. , The input step is repeated four times, and the integer partial product generation step, the partial product addition step, and the accumulation step are repeated four times. 6. In the integer partial product generating step, at the time of an integer operation, two pairs of input integers are input separately into an upper bit area and a lower bit area of a partial product adder, and 1 is assigned to the upper bit area. The multiplicand of a pair of input integers is sign-extended by masking the portion corresponding to the lower bit region, and the other pair of input integers assigned to the lower bit region is masked by coding the portion corresponding to the upper bit region. The partial product generation is performed by performing extension.
The product-sum operation method described in 1.