JPH1173254A - Digital signal processor - Google Patents
Digital signal processorInfo
- Publication number
- JPH1173254A JPH1173254A JP9247490A JP24749097A JPH1173254A JP H1173254 A JPH1173254 A JP H1173254A JP 9247490 A JP9247490 A JP 9247490A JP 24749097 A JP24749097 A JP 24749097A JP H1173254 A JPH1173254 A JP H1173254A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- data path
- unit
- digital signal
- instruction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Debugging And Monitoring (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ディジタル信号処
理プロセッサ（ＤＳＰ）やマイクロプロセッサ等のディ
ジタル信号処理装置に係り、特に稼働率に応じて供給電
圧と命令サイクル数を増減制御して省電力を図ると共に
動作安定性や処理能率向上を図ったディジタル信号処理
装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processor such as a digital signal processor (DSP) or a microprocessor, and in particular, to control power supply by increasing or decreasing a supply voltage and the number of instruction cycles according to an operation rate. The present invention relates to a digital signal processing device for improving operation stability and processing efficiency.
【０００２】[0002]
【従来の技術】ディジタル信号処理装置（以下では、プ
ロセッサと呼ぶ）の省エネルギー化には動作電圧の低減
が有効であるが、一般に動作電圧を低減すると構成回路
の動作速度が低下し、プロセッサの処理を実行するイン
ストラクション（命令）の一部が、定められたマシンサ
イクル（命令サイクル）数内に終了しない不都合が起き
る。逆に、動作電圧を高くすると、構成回路は高速化高
能率化されるが、消費電力が増大し、省エネルギー化が
著しく損なわれるという問題がある。2. Description of the Related Art A reduction in operating voltage is effective for saving energy of a digital signal processing device (hereinafter referred to as a processor). However, generally, when the operating voltage is reduced, the operating speed of a constituent circuit is reduced, and the processing speed of the processor is reduced. Is not completed within a predetermined number of machine cycles (instruction cycles). Conversely, when the operating voltage is increased, the speed of the constituent circuit is increased and the efficiency is increased. However, there is a problem that the power consumption is increased and the energy saving is significantly impaired.
【０００３】その対策として、プロセッサで多用される
同期式回路を駆動するクロック周波数を動作電圧に追従
して変化させることが考えられたが、この方法では入出
力のデータのやりとりを行う周辺ＩＣとの間で動作速度
の不整合が生じ、システム全体の安定動作が困難になる
という問題点があった。As a countermeasure, it has been considered to change a clock frequency for driving a synchronous circuit frequently used in a processor so as to follow an operating voltage. In this method, however, a peripheral IC for exchanging input / output data with a peripheral IC is considered. However, there is a problem in that the operation speeds are inconsistent with each other, making it difficult to perform stable operation of the entire system.
【０００４】そこで、従来では、図３に示すように、プ
ロセッサコア部２１の内部回路２２への供給電圧を外部
電源端子２３から電圧変換器２４を介して供給し、この
電圧変換器２４を、内部回路２２の動作速度を監視する
動作速度モニタ（オペレーションモニタ）部２５でモニ
タした結果に応じて、速度劣化による動作不安定が生じ
ないように、制御していた。２６は外部との間でデータ
をやりとりするためのＩ／Ｏ回路である。Therefore, conventionally, as shown in FIG. 3, a supply voltage to an internal circuit 22 of a processor core unit 21 is supplied from an external power supply terminal 23 via a voltage converter 24, and this voltage converter 24 According to the result monitored by the operation speed monitor (operation monitor) unit 25 that monitors the operation speed of the internal circuit 22, control is performed so that operation instability due to speed deterioration does not occur. Reference numeral 26 denotes an I / O circuit for exchanging data with the outside.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、前記従
来方法では、動作不安定を回避する観点から動作電圧を
十分に低減させることができず、省エネルギー効果が不
十分であった。また、動作電圧を高くする場合は、構成
回路が高速化される効果は期待できるものの、消費電力
が増大する割には、処理効率の向上が十分でなかった。However, in the above-mentioned conventional method, the operation voltage cannot be sufficiently reduced from the viewpoint of avoiding the unstable operation, and the energy saving effect is insufficient. When the operating voltage is increased, the effect of increasing the speed of the constituent circuits can be expected, but the processing efficiency has not been sufficiently improved despite the increase in power consumption.
【０００６】本発明は以上のような点に鑑みてなされた
ものであり、その目的は、稼働率をモニタし、そのモニ
タ結果に応じて最適な動作電圧と命令サイクル数を設定
することにより、省エネルギー効果と処理能率の向上を
図ったディジタル信号処理装置を提供することである。[0006] The present invention has been made in view of the above points, and an object thereof is to monitor an operation rate and set an optimum operation voltage and an optimum number of instruction cycles in accordance with the monitoring result. An object of the present invention is to provide a digital signal processing device which achieves an energy saving effect and an improvement in processing efficiency.
【０００７】[0007]
【課題を解決するための手段】前記目的を達成するため
の第１の発明は、外部電源電圧を入力して内部動作電圧
を出力する電圧変換部と、内部にクロックを供給するク
ロックドライバ部と、命令制御部を含むデータパス部と
を具備するディジタル信号処理装置において、前記クロ
ックドライバ部に供給する動作電流と前記データパス部
に供給する動作電流を検出し、両電流の比率の増減、両
電流の個々の絶対量の増減、あるいは両電流の総量の増
減に基づいて前記データパス部の稼働率を判定し、該判
定結果に応じて前記電圧変換部の出力電圧を増減制御す
ると共に、前記命令制御部に対して命令セットの一部又
は全部の実行サイクル数を増減制御させる電流モニタ部
を設けて構成した。第２の発明は第１の発明において、
前記データパス部の信号にパリティチェック信号を保有
させ、パリティチェックの結果を前記電圧変換部の出力
電圧の増減制御および／又は前記実行サイクル数の増減
制御に反映させるよう構成した。According to a first aspect of the present invention, there is provided a voltage conversion section for inputting an external power supply voltage and outputting an internal operation voltage, and a clock driver section for internally supplying a clock. A digital signal processing device including a data path unit including an instruction control unit, an operation current supplied to the clock driver unit and an operation current supplied to the data path unit are detected, and a ratio of the two currents is increased or decreased. The operation rate of the data path unit is determined based on the increase or decrease of the individual absolute amount of the current, or the increase or decrease of the total amount of both currents, and the output voltage of the voltage conversion unit is controlled to increase or decrease according to the determination result. A current monitor unit is provided for controlling the instruction control unit to increase or decrease the number of execution cycles of part or all of the instruction set. The second invention is based on the first invention,
A parity check signal is held in the signal of the data path unit, and the result of the parity check is reflected in the increase / decrease control of the output voltage of the voltage conversion unit and / or the increase / decrease control of the number of execution cycles.
【０００８】[0008]
【発明の実施の形態】図１は本発明の実施の形態を示す
図である。１はプロセッサコア部であり、内部回路２、
Ｉ／Ｏ回路３を主要な構成要素とするものである。内部
回路２は、全体にクロックを供給するクロックドライバ
部４と、データの演算処理その他を実行するデータパス
部５を有する。このデータパス部５は命令制御部（inst
ruction controller)６を含んでいる。７は外部電源端
子８に供給される電圧（ＶＤＤ）を昇圧あるいは降圧し
て内部回路２に供給する電圧変換部、９はその電圧変換
部７からクロックドライバ部４に供給される動作電流を
計測する電流計、１０は電圧変換部７からデータパス部
５に供給される動作電流を計測する電流計、１１はその
両電流計９，１０で計測された電流値に基づいて電圧変
換部７とデータパス部５の命令制御部６に制御信号を送
る電流モニタ部である。なお、Ｉ／Ｏ回路３への供給電
圧は、外部電源端子８から直接的に電圧ＶＤＤが供給さ
れ、そのＩ／Ｏ回路３が外部回路の信号電圧に対応して
コンパチブルに動作できるようになっている。FIG. 1 is a diagram showing an embodiment of the present invention. Reference numeral 1 denotes a processor core unit, and an internal circuit 2,
The I / O circuit 3 is a main component. The internal circuit 2 includes a clock driver unit 4 that supplies a clock to the whole, and a data path unit 5 that executes data arithmetic processing and the like. This data path unit 5 is an instruction control unit (inst
ruction controller) 6. Reference numeral 7 denotes a voltage converter for boosting or stepping down a voltage (VDD) supplied to the external power supply terminal 8 and supplying it to the internal circuit 2, and 9 measures an operating current supplied from the voltage converter 7 to the clock driver 4. Ammeter 10 for measuring the operating current supplied from the voltage converter 7 to the data path unit 5, and 11 for the voltage converter 7 based on the current values measured by the two ammeters 9 and 10. This is a current monitoring unit that sends a control signal to the instruction control unit 6 of the data path unit 5. The voltage VDD supplied to the I / O circuit 3 is directly supplied from the external power supply terminal 8, so that the I / O circuit 3 can operate compatible with the signal voltage of the external circuit. ing.
【０００９】さて、電流モニタ部１１でモニタしたクロ
ックドライバ部４に対する供給電流がＩｃ、データパス
部５に対する供給電流がＩｄであったとすると、データ
パス部５の稼働率γ次の式で表される。 γ ＝ Ｉｄ／（Ｉｄ＋Ｉｃ） ・・・（１） ＝ １−Ｉｃ／Ｉｔ ＝ １−Ｐｃ／Ｐｔ 但し、Ｉｔ＝Ｉｄ＋Ｉｃである。また、Ｐｃはクロック
ドライバ部４の消費電力、Ｐｔは内部回路２の全体の消
費電力であり、 Ｐｃ＝Ｉｃ・（ＶＤＤ±ΔＶ） Ｐｔ＝Ｉｃ・（ＶＤＤ±ΔＶ）＋Ｉｄ・（ＶＤＤ±ΔＶ） である。（ＶＤＤ±ΔＶ）は、電圧変換部７からクロッ
クドライバ部４とデータパス部に共通に供給される電圧
である。If the current supplied to the clock driver 4 monitored by the current monitor 11 is Ic and the current supplied to the data path 5 is Id, the operating rate of the data path 5 is expressed by the following equation: You. γ = Id / (Id + Ic) (1) = 1−Ic / It = 1−Pc / Pt where It = Id + Ic. Pc is the power consumption of the clock driver unit 4, Pt is the total power consumption of the internal circuit 2, and Pc = Ic · (VDD ± ΔV) Pt = Ic · (VDD ± ΔV) + Id · (VDD ± ΔV) It is. (VDD ± ΔV) is a voltage commonly supplied from the voltage converter 7 to the clock driver 4 and the data path.
【００１０】前記稼働率γが十分に小さく０に近い場合
は、消費電流の大半はクロックドライバ部４で消費され
ており、データパス部５の実効的な稼働率が小さいこと
を示す。この場合は、電流モニタ部１１は電圧変換部７
に対して、内部回路２に供給する電圧（ＶＤＤ±ΔＶ）
を低く設定するよう指令する。同時に、プロセッサで実
行する命令セットの一部あるいは全部の命令サイクル数
（１命令サイクルのクロック数）を１あるいは２程度増
加するよう、データパス部５内の命令制御部６に指令す
る。すなわち、通常では１命令サイクルは、例えば２ク
ロック又は３クロックで実行されるが、このクロック数
を増やす。When the operating rate γ is sufficiently small and close to 0, most of the current consumption is consumed by the clock driver section 4, indicating that the effective operating rate of the data path section 5 is small. In this case, the current monitor 11 is connected to the voltage converter 7
With respect to the voltage supplied to the internal circuit 2 (VDD ± ΔV)
Is set lower. At the same time, it instructs the instruction control unit 6 in the data path unit 5 to increase the number of instruction cycles (the number of clocks in one instruction cycle) of part or all of the instruction set executed by the processor by one or two. That is, one instruction cycle is normally executed with, for example, two clocks or three clocks, but the number of clocks is increased.
【００１１】図２に命令サイクル数の増減の様子を示し
た。１２は低電圧動作時のサイクル数、１３は高電圧動
作時のサイクル数、１４は動作電圧低下によるサイクル
時間の増加分である。Ａ，Ｂ，Ｃは命令の種類である。FIG. 2 shows how the number of instruction cycles increases and decreases. 12 is the number of cycles in the low voltage operation, 13 is the number of cycles in the high voltage operation, and 14 is the increase in the cycle time due to the decrease in the operating voltage. A, B, and C are instruction types.
【００１２】前記のように稼働率が小さい場合は、内部
供給電圧が低減されることにより消費電力の削減が達成
され、命令サイクル数が大きくなることにより命令処理
に余裕ができ安定した命令処理が実施されるようにな
る。すなわち、省エネルギー化と安定動作が達成され
る。When the operating rate is low as described above, the reduction in power consumption is achieved by reducing the internal supply voltage, and the number of instruction cycles is increased, so that the instruction processing has a margin and stable instruction processing can be performed. Will be implemented. That is, energy saving and stable operation are achieved.
【００１３】一方、稼働率γが０より十分大きい場合に
は、内部回路２で消費される電力の内、データパス部５
で消費される比率が増大し、データパス部５の実効的な
稼働率が大きいことを示す。この場合は、電流モニタ部
１１は電圧変換部７に対して、内部回路２に供給する電
圧（ＶＤＤ±ΔＶ）を高く設定するよう指令する。同時
に、プロセッサで実行する命令の一部あるいは全部の命
令サイクル数を１あるいは２程度減少するよう、データ
パス部５内の命令制御部６に指令する。On the other hand, when the operating rate γ is sufficiently larger than 0, the data path unit 5 out of the power consumed by the internal circuit 2
Indicates that the effective rate of operation of the data path unit 5 is large. In this case, the current monitor 11 instructs the voltage converter 7 to set the voltage (VDD ± ΔV) supplied to the internal circuit 2 higher. At the same time, it instructs the instruction control unit 6 in the data path unit 5 to reduce the number of instruction cycles of some or all of the instructions executed by the processor by one or two.
【００１４】このように稼働率が大きい場合は、内部供
給電圧を高くなることにより高速動作が実現でき、この
高速動作を生かすように、命令サイクル数が小さく設定
されるので、処理の高効率化が達成される。When the operating rate is high as described above, a high-speed operation can be realized by increasing the internal supply voltage, and the number of instruction cycles is set small so as to make use of this high-speed operation, so that the processing efficiency is improved. Is achieved.
【００１５】前記した命令サイクル数の増減の設定のタ
イミングは、命令の合間をぬって再設定を実行するダイ
ナミック設定によっても、あるいは、命令が実施される
可能性がない場合に限って再設定を実行するスタティッ
ク設定によっても良い。The timing of setting the increase / decrease of the number of instruction cycles can be reset by dynamic setting for executing resetting between instructions, or only when there is no possibility that the instruction will be executed. It may be based on the static setting to be executed.
【００１６】なお、前記稼働率の算出においては、式
（１）に示したクロックドライバ部４への電流Ｉｃとデ
ータパス部４への電流Ｉｄの比率｛＝Ｉｄ／（Ｉｄ＋Ｉ
ｃ）｝以外の比率（＝Ｉｃ／Ｉｄ）のに基づいて行うこ
ともでき、このときの稼働率γは（Ｉｃ／Ｉｄ）に反比
例する。またＩｃ、Ｉｄの絶対値に基づいて行うことも
でき、このときの稼働率γはＩｄに比例する。さらに、
電流ＩｃとＩｄの総量（＝Ｉｃ＋Ｉｄ）に基づいて行う
こともでき、このときの稼働率γは（Ｉｃ＋Ｉｄ）に比
例する。In the calculation of the operation rate, the ratio of the current Ic to the clock driver unit 4 and the current Id to the data path unit 4 shown in equation (1) = ｛Id / (Id + I
c) It can be performed based on a ratio (= Ic / Id) other than｝, and the operation rate γ at this time is inversely proportional to (Ic / Id). Further, it can be performed based on the absolute values of Ic and Id, and the operation rate γ at this time is proportional to Id. further,
It can also be performed based on the total amount of currents Ic and Id (= Ic + Id), and the operation rate γ at this time is proportional to (Ic + Id).
【００１７】また、前記説明において、データパス部５
の主要信号にパリティチェック部分を追加しておけば、
そのパリティチェックを常時実効させ、そのチェック結
果によって、たとえばパリティ誤りが判定さることによ
りプロッセサの不安定動作を即時に検出できるので、こ
の検出結果を内部回路２に供給する電源電圧や命令サイ
クル数の最適化に反映することができる。In the above description, the data path unit 5
By adding a parity check part to the main signal of
The parity check is always executed, and the unstable operation of the processor can be immediately detected based on the check result, for example, by determining a parity error. Can be reflected in optimization.
【００１８】例えば、稼働率γの結果に基づいて供給電
圧を設定して動作した結果、パリティチェックでパリテ
ィ誤りが判定されれば、その供給電圧が低すぎたことに
なるので、その供給電圧を上昇させるよう補正を加え再
計算する。また、稼働率γの結果に基づいて命令サイク
ル数を減少して動作した結果、パリティチェックでパリ
ティ誤りが判定されれば、その命令サイクル数少なすぎ
たことになるので、その命令サイクル数を増加させるよ
う補正を加え再計算する。For example, if a parity error is determined by a parity check as a result of setting and operating the supply voltage based on the result of the operation rate γ, the supply voltage is determined to be too low. Add a correction to raise the value and recalculate. If the parity error is determined by the parity check as a result of operating with the instruction cycle number reduced based on the result of the operation rate γ, the instruction cycle number is too small, and the instruction cycle number is increased. And then recalculate.
【００１９】[0019]
【発明の効果】以上から本発明によれば、電圧変換部、
電流モニタ部等を追加し、稼働率を判定することにより
実現できるので、既存のディジタル信号処理装置の構成
の大幅な変更を伴わずに、すなわちゲート数やチップ面
積の増大を少なく抑えて、最適な動作電圧と命令サイク
ル数を設定することができ、省エネルギー効果と処理能
率の向上を図ることが可能となる。As described above, according to the present invention, the voltage converter,
It can be realized by adding a current monitoring unit and determining the operation rate, so that it can be optimized without significant changes in the configuration of existing digital signal processing devices, that is, with a small increase in the number of gates and chip area. It is possible to set an appropriate operation voltage and the number of instruction cycles, and it is possible to achieve an energy saving effect and an improvement in processing efficiency.
【図１】 本発明の実施の形態のディジタル信号処理装
置の構成を示す説明図である。FIG. 1 is an explanatory diagram illustrating a configuration of a digital signal processing device according to an embodiment of the present invention.
【図２】 命令サイクル数の説明図である。FIG. 2 is an explanatory diagram of the number of instruction cycles.
【図３】 従来のディジタル信号処理装置の構成を示す
説明図である。FIG. 3 is an explanatory diagram showing a configuration of a conventional digital signal processing device.
１：プロッセサコア部、２：内部回路、３：Ｉ／Ｏ回
路、４：クロックドライバ部、５：データパス部、６：
命令制御部、７：電圧変換部、８：外部電源端子、９，
１０：電流計、１１：電流モニタ部。1: Processor core unit, 2: Internal circuit, 3: I / O circuit, 4: Clock driver unit, 5: Data path unit, 6:
Command control unit, 7: voltage conversion unit, 8: external power supply terminal, 9,
10: ammeter, 11: current monitor.
Claims (2)
力する電圧変換部と、内部にクロックを供給するクロッ
クドライバ部と、命令制御部を含むデータパス部とを具
備するディジタル信号処理装置において、 前記クロックドライバ部に供給する動作電流と前記デー
タパス部に供給する動作電流を検出し、両電流の比率の
増減、両電流の個々の絶対量の増減、あるいは両電流の
総量の増減に基づいて前記データパス部の稼働率を判定
し、該判定結果に応じて前記電圧変換部の出力電圧を増
減制御すると共に、前記命令制御部に対して命令セット
の一部又は全部の実行サイクル数を増減制御させる電流
モニタ部を設けたことを特徴とするディジタル信号処理
装置。1. A digital signal processing apparatus comprising: a voltage converter for inputting an external power supply voltage and outputting an internal operating voltage; a clock driver for supplying a clock to the inside; and a data path including an instruction controller. Detecting an operating current supplied to the clock driver unit and an operating current supplied to the data path unit, and increasing or decreasing the ratio of the two currents, increasing or decreasing the individual absolute amounts of the two currents, or increasing or decreasing the total amount of the two currents. The operation rate of the data path unit is determined based on the determination result, and the output voltage of the voltage conversion unit is controlled to increase or decrease according to the determination result. 2. A digital signal processing device comprising a current monitor unit for increasing / decreasing a current.
ク信号を保有させ、パリティチェックの結果を前記電圧
変換部の出力電圧の増減制御および／又は前記実行サイ
クル数の増減制御に反映させることを特徴とする請求項
１に記載のディジタル信号処理装置。2. A signal of the data path section having a parity check signal, and a result of the parity check is reflected in an increase / decrease control of an output voltage of the voltage converter and / or an increase / decrease control of the number of execution cycles. 2. The digital signal processing device according to claim 1, wherein
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24749097A JP3757252B2 (en) | 1997-08-29 | 1997-08-29 | Digital signal processor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24749097A JP3757252B2 (en) | 1997-08-29 | 1997-08-29 | Digital signal processor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH1173254A true JPH1173254A (en) | 1999-03-16 |
| JP3757252B2 JP3757252B2 (en) | 2006-03-22 |
Family
ID=17164250
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24749097A Expired - Fee Related JP3757252B2 (en) | 1997-08-29 | 1997-08-29 | Digital signal processor |
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| Country | Link |
|---|---|
| JP (1) | JP3757252B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2020098493A (en) * | 2018-12-18 | 2020-06-25 | 富士ゼロックス株式会社 | Image processing device |
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1997
- 1997-08-29 JP JP24749097A patent/JP3757252B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2020098493A (en) * | 2018-12-18 | 2020-06-25 | 富士ゼロックス株式会社 | Image processing device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3757252B2 (en) | 2006-03-22 |
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