JPH1168581A - Cyclic redundancy check code replacing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a circuit scale by providing an adding means, etc., which uses a cyclic redundancy check code (CRC), that is calculated by an operating means and newly replaces a CRC part on which information is rewritten among the original CRCs that is added to information before rewriting. SOLUTION: When old information is inputted, a latch 11 latches the inputted old information, addresses the latched old information and adds it to a RAM 12a. A 1st gate 13 compares the old information with new information, extracts bits whose values are different, and outputs them to a CRC operating part 2. Then, the part 2 performs 8 bit exclusive-OR processing for every string and acquires an operation result of CRCbit1 to CRCbit8. Also, the value of old CRC that passes through a delaying part 31 is applied to a 2nd gate 33 via a 1st selector 32. With this, the value of the old CRC is compensated in accordance with the operation result of the part 2, a CRC part is replaced with a new CRC value and it is outputted from a 2nd selector 34.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cyclic redundancy check code (hereinafter abbreviated as "CRC") replacement circuit used in, for example, a transmission apparatus.
It is intended to reduce the circuit scale at the time of CRC replacement.

[0002]

2. Description of the Related Art FIG. 6 is an explanatory diagram of a usage example of a CRC, and FIG.
FIG. 4 is an explanatory diagram of a section requiring an RC field.

[0003] An error detection code or an error correction code such as a CRC is originally used for the purpose of assuming an error in a transmission path and protecting information to be transmitted against the error. For example, as shown in FIG. 6, a CRC adding section 41 for adding a CRC is provided in the transmitter 4, and the CRC adding section 41 adds a CRC to the input information and sets a transmission path. And sends it to the receiver 5.

[0004] A CRC processing section 51 is provided in the receiver. This CRC processing section performs error detection and error correction using a CRC separated from a received signal, and extracts correct information.

Therefore, the field for inserting the CRC is:
It is sufficient if the validity is valid only from the CRC adding unit on the transmitting side to the CRC processing unit on the receiving side. As shown in FIG. 7, the CRC addition part 41a in the device 1
The RC is added and transmitted to the device 2 via the transmission path.

Therefore, the CRC processing portion 51a in the device 2
Performs error detection and error correction using the CRC separated from the received signal, extracts correct information, and
Send to 2.

The internal processing section 52 rewrites the information to
Since the CRC is transmitted to the RC addition section 41b, the CRC addition section generates a CRC for the rewritten information, adds the generated CRC to the rewritten information, and transmits the CRC to the device 3 via the transmission path.

The device 3 performs error detection and error correction using the CRC separated from the received signal by the CRC processing unit 51b, as in the device 2, and extracts correct information. That is, even if the information is rewritten in the devices 1, 2, and 3, the CRC may be changed by the transmitter when going out to the next transmission path. It was present only in the section where the description was written, and in the section where "device processing" was written, the CRC field itself did not exist, or even if it was present, it should have been ignored.

[0009] Originally, no error occurs in the apparatus, and data is often expanded in parallel, so adding horizontal parity to data expanded in parallel poses a problem. There was no.

Furthermore, many transmission devices require information specific to a transmission path (for example, information written in an STM header of an SDH system). Is added to the information in the form of a header or the like and transmitted to the receiving side.

On the receiving side, the header information is processed and then removed, and only the information is passed through the apparatus. Therefore, if the CRC is added to the information in the header form,
The RC did not flow into the device.

[0012]

FIG. 8 is a diagram for explaining the structure of an ATM cell. FIG. 8A is a diagram showing the structure of an ATM cell, and FIG.
It is a block diagram of an M header.

FIG. 9 is an example of a device configuration diagram for multiplexing four inputs from a transmission line, and FIG. 10 is an explanatory diagram of an example in which an additional header is added to the original header to extend the range protected by CRC. 11 is an example of a configuration diagram having an additional header adding unit in the configuration of FIG. 9, and FIG. 12 is a configuration diagram of a conventional example.

The portion of "ATM header" in FIG. 8A is a range protected by CRC, and the portion of "CRC" is called "HEC" in ATM, and more precisely "HEC".
And an ATM header.

The symbols in FIG. 8B are the following abbreviations. GFC: General Flow Control,
VIP: Virtual Path Identifier
n), VCI: Virtual Channel Identifier
ntification), PT: Payload Typ
e), CLP: Cell Loss Priority indication,
HEC: Header Error Control By the way, there is no problem if the CRC is used as usual, but in a new transmission system such as ATM (Asynchronous Transfer Mode) transmission, the CRC is pre-installed in the header, This format remains in the device, and the CRC is added without being removed.

For example, FIG. 8A shows an ATM header and a CR.
C shows the configuration of an ATM cell composed of an ATM payload portion. However, in the case of an ATM, the information of the ATM header shown in FIG. 8B is rewritten in the device. C written in the CRC part
Contradiction with RC occurs.

Therefore, if the CRC written in the ATM device is ignored and the CRC is completely recalculated and replaced using new information immediately before outputting to the transmission line, no problem occurs.

FIG. 9 shows four series of ATs input from the transmission line.
FIG. 3 shows a configuration of a device for multiplexing M cells by four,
Each of the receiving units 61a to 61d extracts the ATM cell shown in FIG. 8A from the low-speed signal input through the transmission path,
The data is sent to the corresponding header rewriting units 62a to 62d.

The header rewriting unit, for example,
A part of the information written in the TM header is rewritten with new information and sent to the multiplexing unit 63. At this time, the CRC remains unchanged without being changed.

The multiplexing unit 63 multiplexes the four series of signals to increase the data rate by a factor of four and sends it to the transmitting unit 65.
The transmitting unit 65 recalculates the CRC for all information in the ATM header added to the multiplexed signal to obtain a new CRC value, and adds these values to the corresponding header. Send to the transmission path.

In this case, it is easier to reconfigure the CRC at point a, where the speed is slow, than to reattach the CRC at point b, where the speed is high. This not only facilitates circuit design, but is also advantageous in terms of cost.

In the configuration of FIG. 9, as shown in FIG.
FIG. 11 shows an example of an apparatus configuration in a case where another header is added to the original header and the range protected by the CRC is changed from the original header alone to both (the original header + another header).

Incidentally, the configuration as shown in FIG.
The ATM header shown in FIG.
It is used when information information necessary for ATM-PON transmission is written in another header area.

Now, in FIG. 11, each of the receiving units 61a-61
61d is obtained from the low-speed signal input through the transmission line as shown in FIG.
The original header indicated by 0 is extracted and sent to the corresponding original header rewriting units 62a to 62d.

The original header rewriting unit, for example, rewrites a part of the information written in the input original header to new information and sends it to the multiplexing unit 63. The multiplexing unit multiplexes the four series of signals, increases the data rate by four times, and sends the data to the additional header adding unit. The additional header adding unit is, for example, as shown in FIG.
As indicated by 0, another header is added to the original header and transmitted to the transmission unit 65.

The transmitting section 65 recalculates the CRC for (original header + another header) and stores the obtained value in FIG.
Is stored in the CRC section. As a result, up to two headers can be protected by CRC.

In the case of FIG. 11, if the CRC calculation is performed at point b (high-speed side), the entire range (the original header + another header)
Rather, it is more advantageous in terms of circuit configuration to add a CRC for the increased (another header).

For that purpose, the CRC of the (original header) needs to be calculated first, and if this part is not calculated, the (original header + another header) is completely deleted as described above. You have to calculate.

From such a background, when a part of the information in the range protected by the CRC is rewritten in the apparatus, a new method is required in which the CRC can be easily replaced with a new CRC at the same time.

By the way, as described above, conventionally, CR
Since C is not used, there is no conventional example to be compared, but a configuration as shown in FIG. 12 can be generally considered. That is,
In FIG. 12, a signal for latching a rewritten portion of the header information is generated using a counter (not shown) or the like.

For example, when rewriting the "VPI" of the ATM header shown in FIG. 8B, when the count value of the counter is "1", the lower 4 bits "VPI" are used, and when the counter value is "2", the upper 4 bits are used. A latch signal for latching 4-bit “VPI” is generated.

Since the ATM cell has 53 bytes,
The counter requires a 53-base counter. By using the generated latch signal, the "VPI" information before rewriting is extracted and latched by the latch 71, and the RAM 72 is accessed using the latched "VPI" information before rewriting as an address.

The RAM 72 stores header information before rewriting (described as old information in the figure) as an address, and header information after rewriting (described as new information in the figure) as data. Because there is RAM
From 72, new "VPI" information is retrieved.

Until the new information is extracted by accessing the RAM 72, a delay is given to the signal before rewriting by the delay unit 73, and the RAM is provided only in the field to be rewritten by the selector 74. If it is switched to the output side, new header information is entered in the ATM header.

After that, the CRC operation unit 75
For the entire range protected by the CRC shown in FIG.
The C operation is performed, and the result of the CRC operation is stored in the CRC section of FIG.

In this way, when a part of the information in the range protected by the CRC is rewritten in the apparatus, the CRC can be replaced with a new CRC.

[0037]

According to a first aspect of the present invention, there is provided a detecting means for comparing bit values of information before rewriting and information after rewriting and detecting and outputting portions having different values, Cyclic redundancy for the output of the detection means;
Using the calculating means for obtaining the check code and the cyclic redundancy check code obtained by the calculating means, the original cyclic data added to the information before rewriting is obtained.
Addition means is provided for replacing the cyclic redundancy check code of the portion of the redundancy check code whose information has been rewritten with a new cyclic redundancy check code.

According to a second aspect of the present invention, there is provided a storage means for storing information before rewriting in a storage area designated by the address, wherein the information before rewriting is an address, It is constituted by first gate means for taking an exclusive OR of the written information read from the storage means.

When the information after rewriting is input, the information side after rewriting is selected. When the information after rewriting is not input, the information before rewriting is delayed. Of the original cyclic redundancy check code added to the output before the rewriting that has passed through the first selector, the first selector that selects Second gate means for taking the exclusive OR of the cyclic redundancy check codes of the parts and replacing the result with a new cyclic redundancy check code; and output states of the first selector and the second gate means And a second selector that performs a select operation in response to the above.

According to a third aspect of the present invention, in the storage means, the information before rewriting is used as an address, and the information after rewriting and the cyclic redundancy check code obtained by the arithmetic means are specified by the address. It is configured to store in the area.

According to a fourth aspect of the present invention, the first arithmetic means is connected to the input side of the storage means, the second arithmetic means is connected to the output side, and the second gate means is connected to the first selector. The output side of the first and second calculation means is connected to the input side.

Next, before explaining FIG. 1 which is a principle diagram of the present invention, when rewriting a part of the information which is error-protected by the CRC, only the CRC of the rewriting part is calculated,
It is shown that the present method of realizing the replacement of the CRC by adding to the original CRC is mathematically the same as the case of performing the entire CRC protection range as shown in FIG.

CRC generally represents a portion of information by a polynomial, divides it by a generator polynomial, and adds the remainder. For example, since the generator polynomial the ATM is represented by ^{G (x) = x 8 +} x 2 + x +1, remainder seven squares polynomial, i.e., of 8 bits.

[0044] Now, when the information code and ^{M (x), x 8 M} (x) = Q (x) G (x) + R (x) to become such a quotient polynomial Q (x) and the remainder R (x) Is defined.

[0045] Then, the coded polynomial for transmission as Tx (x), and generates a ^{Tx (x) = x 8 M} (x) + R (x) (= Q (x) G (x)) .

That is, T (x) can be divided by G (x), and R (x) is written into the CRC field. Since M (x) is 32 bits in ATM, it is a 31-order polynomial.

Then, assuming that the coefficients of the terms of x ⁱ are a ₃₁ , a ₃₀ ,... A ₁ , a ₀ , this R (x) becomes R (x) = a ₃₁ (x ³⁹ mod G ( _{x)) + a 30 (x} 38 mod G (x))
+ · + A ₁ (x ⁹ mod G (x)) + a ₀ (x ⁸ mod G (x)) Here, x ⁱ mod G (x) is a remainder of a fixed value if i is determined.

For example, if the coefficients a ₃₁ , a ₂₅ , a ₁ = 1 and the other coefficients are 0, R (x) = a ₃₁ (x ³⁹ mod G (x)) + a ₂₅ (x ³³ mod G (x )) + A ₁
(x ⁹ mod G (x)).

Therefore, it is assumed that the coefficients a _31, a ₂₄ , a ₁ = 1 and other coefficients are to be changed to 0. To do this, R ′ (x) = a ₃₁ (x ³⁹ mod G (x)) + a ₂₄ (x ³³ mod G (x)) +
The first calculation method for calculating a ₁ (x ⁹ mod G (x)) and the original R (x) are a ₂₅ (x
There is a second calculation method that adds ³³ mod G (x)) + a ₂₄ (x ³² mod G (x)).

In the second calculation method, a ₃₁ (x ³⁹ mod G (x)) + a ₂₅ (x ³³ mod G (x)) + a ₁ (x ⁹ mod G (x)) + a ₂₅ (x ³³ mod G (x)) + a ₂₄ (x ³² mod G (x)) = a ₃₁ (x ³⁹ mod G (x)) + (a ₂₅ + a ₂₅ ) (x ³³ mod G (x)) + a ₂₄ (x ³² mod G (x)) + a ₁ (x ⁹ mod G (x)) = a ₃₁ (x ³⁹ mod G (x)) + a ₂₄ (x ³² mod G (x)) + a ₁ (x ⁹ mod G (x)) , A ₂₅ become 0 by passing through the EX-OR gate, and are replaced with the correct CRC.

That is, the first calculation method is a method of directly calculating R '(x) by calculating over the entire range of protecting the CRC, and the second calculation method is a method of calculating a difference between the two.
₂₅ (x ³³ mod G (x)) + a ₂₄ (x ³² mod G (x))
It is the method of the present invention that is obtained in addition to C, that is, R (x).

As a method, bits having different values before and after rewriting are searched (in the above case, a ₂₅ and a ₂₄ ), and the CRC of that part may be calculated and added to the original CRC. The schematic operation of FIG. 1 will be described based on this, and the detailed operation will be described in the section of the embodiment.

First, the operation of extracting the header information to be rewritten from the input signal and referring to the RAM is the same as the operation of FIG. 7 described above, but the first gate 13 in FIG. The exclusive OR is calculated for each bit of the header information.

In the above calculation example for explaining the principle, a ₂₅ and a ₂₄
, But corresponds to the operation of the first gate 13 extracting a portion having a different value. Next, the CRC calculation unit 2 calculates a ₂₅ (x ³³ mod G (x)) + a ₂₄ (x ³² mod G (x)) which is the difference between the two.

Here, since it is assumed that only partial rewriting is performed, a ₂₅ (x ³³ mod G (x)) + a ₂₄ ( x ³² mod G (x)).

Since it is a CRC operation, it can be calculated by a divider circuit. However, the code generated using the generator polynomial G (x) is 127 bits for the encoder and 119 bits for the information bit M (x).

Therefore, although it is usually used in a shortened manner, a circuit which directly calculates only by exclusive OR unless the information bit is shortened to about 8 to 16 is inferior in circuit scale or processing time.

Specifically, in the case of the generator polynomial G (x) described above, a CRC operation for rewriting eight bits from the 36th bit (the lowest bit is the first bit) to the 29th bit counted from the lower order. FIG. 2 shows a circuit example of the unit.

At this time, the remainder x ⁱ mod G (x) is i =
Since it is from 35 to 28, it is assumed that the value at that time is as follows. That is,

[0060]

(Equation 1)

For example, 10110000 is [x ³⁵ / G
In the remainder of (x)] is ^{x 7 + x 5 + x 4} , in which it is shown in binary.

As shown in FIG. 2, the most significant bit among the remaining 8 bits, 3 bits and 1 bit of old head information + new head information (hereinafter abbreviated as old information + new information) By taking the exclusive OR of the bit (bit 8), an addition output of the column of bit 8 in the above equation (1) is obtained, and this output becomes the rewritten value of CRCbit8.

By taking the exclusive OR of bit 7 of the remainder of the seventh and second bits, an addition output of the column of bit 7 in the above equation (1) is obtained. This is the value of CRCbit7 that has been rewritten.

By repeating this, the rewritten C
The values of RCbit8 to CRCbit1 are obtained. In other words, there is a portion where the bit changes when the formula (1) is viewed in the column direction, that is, vertically, and the CRC portion is calculated by adding (exclusive OR) all the changed portions.

At this time, if the addition result is "0", it indicates that when the original CRC is compared with the new CRC, the bits in that part are the same, so that the original bits are output as they are.

However, if the addition result is "1", it indicates that the result is different, so that the original bit is inverted and output. As a result, the CRC of the rewritten portion becomes the CRC operation unit 2
Thus, at the second gate 33 in FIG. 1, it is added to the original CRC.

The second selector 34 switches to the side of the second gate 33 only in the CRC insertion area (bit 1 to bit 8 in FIG. 9), and performs the operation of replacing the CRC part with a new value.

In this manner, the CRC can be replaced without using the circuit shown in FIG. 12 for performing the CRC operation over the entire range protected by the CRC.

[0069]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of a main part of a first and a second embodiment of the present invention, FIG. 2 is a block diagram of a main part of a CRC calculation unit in FIG. 1, and FIG. FIG. 2 is a configuration diagram of a main part of an embodiment of the present invention.

FIG. 4 is a block diagram of a main part of another embodiment of the third invention, and FIG. 5 is a block diagram of a main part of an embodiment of the fourth invention. The same reference numerals indicate the same objects throughout the drawings. Hereinafter, FIGS. 1 to 5 will be described.

The operation of FIGS. 1 and 2 will be described. First, FIG.
Similarly to FIG. 2, since the correspondence between the old information and the new information is known in advance in FIG. 1, the old information is set as the address of the RAM 12a, and the new information is stored in the corresponding address area in advance.

When the old information is input, the latch 11 latches the input old information and adds the latched old information to the RAM 12a as an address. As a result, new information corresponding to the old information input from the RAM is read, and the first information is read.
The old information from the latch and the new information read out are applied to the gate 13 of.

The first gate 13 performs an exclusive OR operation on each bit corresponding to the old information and the new information. Therefore, if the corresponding bits of the old information and the new information have changed, “1” is changed. If not, "0" is output.

That is, the first gate 13 compares the old information with the new information, extracts bits having different values, and outputs the extracted bits to the CRC operation unit 2. Note that the left part (old information + new information) bit8 to (old information + new information) bit1 in FIG. 2 corresponds to the output of the first gate 13 in FIG. For example, binary codes of (first bit) to (eighth bit) shown in the above equation (1).

Thus, as described in detail above, the CRC operation unit 2 performs an exclusive OR operation of eight bits for each column in the equation (1) to obtain the operation results of CRCbit1 to CRCbit8.

Here, if the operation result is "0", this bit indicates that the old CRC and the new CRC have the same value, and the value of the old CRC is output as it is. But,
If "1", the bit indicates that the old CRC and the new CRC have different values, and a signal for inverting and outputting the bit value of the old CRC is output to the second gate 33. I do.

The value of the old CRC that has passed through the delay unit 31 is also applied to the second gate 33 via the first selector 32. As a result, the value of the old CRC is corrected according to the calculation result of the CRC calculation unit 2, and the CRC part is replaced with the new CRC value.
And is output from the second selector 34.

The new information written in the RAM 12a is output via the first selector 32 and the second selector 34 which have selected the RAM side. At this time, for example, the format shown in FIG. As a result, the first selector and the second selector are driven.

The operation of FIG. 3 will be described. First, since the correspondence between the old information and the new information (which bit changes) is known in advance, the control unit 14 has the new information and the old information.

As a result, the control unit 14 writes the new information in the RAM 12b using the old information as an address, and outputs the exclusive OR obtained by taking the exclusive OR of the old information and the new information in the first gate 13. Is added to the CRC calculation unit 2 and the CR
Find the result of the C operation.

Then, the CRC operation result is written at the same address as the new information. When a signal before rewriting is input, the header portion of the input signal is latched as old information in the latch 11, then the latched old information is applied as an address, and the CRC operation result is read out from the RAM 12b to read out the data. 2 gate 33a.

At this time, the value of the old CRC delayed by a predetermined amount in the delay unit 31 is also applied to the second gate 33a via the first selector 32 that has selected the delay unit side. As a result, if the CRC operation result is "0", the old C
The value of RC is output as it is, and if it is “1”, the value of the old CRC is inverted and output. Therefore, the value of the old CRC is replaced with the value of the new CRC and output via the second selector 34.

The new information read from the RAM 12b is output via the first selector 32 and the second selector 34. The first and second selectors output the new CRC value and the new information. Each of them is driven so as to be inserted into a predetermined position in the format shown in FIG.

That is, in the portion where rewriting is performed as described above, a new value is obtained from the RAM 12b using the value before rewriting as an address. However, when the RAM 12b is set by the control unit 14 in the apparatus, the values before and after rewriting are known at the time of setting, so that the CRC 12
The calculation result can be written together in the RAM.

By doing so, there is no need to calculate the CRC operation every time the header is rewritten, and there is no problem in setting the RAM in the RAM 12b from the control unit 14 even at low speed, which is advantageous in terms of circuit configuration. It is.

The control unit 14 has a function of interfacing with a control unit of a device not described here (configured by a workstation or an interface circuit). When the setting of the RAM 12b is instructed, the setting is performed according to the instruction.

The operation of FIG. 4 will be described. FIG.
In step 5, the CRC calculation result is obtained in advance by software.

That is, the CRC operation result is obtained in advance from the old information and the new information using software, and the new information and the CRC operation result are collectively written as data in the RAM 12c using the old information as an address. This is different from the case of FIG.

The configuration of the part for rewriting the CRC to a new value is the same as that in FIG. By the way, this configuration is the first in FIG.
This part is not included in the constituent elements because the part of the gate 13 and the CRC operation part 2 is performed by software.

The control unit 15 in FIG. 4 has both the control functions not described in FIG. 3 and the control functions in FIG. As an actual operation, when the control unit of the device sets the address and data in the RAM, first, software (not shown) in the control unit of the device determines values before and after writing, and simultaneously calculates a CRC. I do.

The data before rewriting is written into the RAM 12c as an address, and the data after rewriting and the CRC are written into the RAM 12c via an interface function (not shown). This is a part for performing a series of operations.

Here, since the CRC calculation in FIG. 12 calculates over the entire range to be protected, it is too slow with software. However, in this configuration, the CRC calculation can be calculated using software.

In this sense, this is an effective method when it is desired to reduce the load on hardware. The operation of FIG. 5 will be described.
In FIG. 5, only the CRC operation of the old information is performed by the CRC operation unit 21, and only the CRC operation of the rewritten and new information portion of the old information is performed by the CRC operation unit 22.

Then, the exclusive OR of the outputs of these two CRC calculation units and the old information applied through the first selector switched to the delay unit 31 side is output to the second gate 3.
By taking 3b, the same as FIG. 1 can be performed.

Here, comparing FIG. 5 with FIG. 1, in FIG. 1, as described above, the exclusive OR of the old information before the rewriting and the new information after the rewriting is performed by the first gate 13. After that, the CRC calculation unit 2 performs a CRC calculation, and the second gate 33 replaces the original CRC with a new CRC.

On the other hand, in FIG.
The operation units 22 and 21 use the new information and the old information to
The two CRC calculation results obtained by performing the RC calculation and the old CRC delayed by the delay unit 31 and added via the first selector 32 are exclusive ORed by the second gate 33b. I have.

For this reason, the number of gate stages that pass through to change the CRC is not different from that in FIG. 1, but the input and output of the first-stage selector 32 (for rewriting old information to new information) 1 passes through the first gate 13 and the CRC operation unit 2 in FIG. 1, whereas in FIG.
Only the operation units 21 and 22 pass.

Therefore, even if the circuit scale is slightly increased, if the logic between the FFs is reduced, a sufficient circuit configuration can be realized.

[0099]

Although the present invention has been described with respect to CRC, the present invention can be generally used not only for CRC but also for linear codes. However, the present invention has the following advantageous conditions: the code (usually the information bit and the check bit are referred to as a code) has a small number of check bits and a considerably large number of information bits; Part of the bit part (It is considered that it can be configured by exclusive OR without using a division circuit (calculation can be performed with one clock to two clocks))
Is raised.

Although there are many linear codes, the actual
Except for (cyclic code), there are few that satisfy the above conditions, so the description is made for CRC. For example,
In the case of CRC, as an example of a 1-bit error correction code and a 2-bit error detection code (accurately, a BCH code), a code having a code length of 127 bits, a check bit number of which is 8 bits, and information bits of 119 bits can be created.

When it is desired to rewrite about 8 to 16 bits of the information bits of this code, rather than recalculating the check bits from all 119 bits of information, the check bits of only the rewritten several bits are used. Is more effective in terms of circuit configuration and processing time.

[Brief description of the drawings]

FIG. 1 is a main part configuration diagram of a first and a second embodiment of the present invention.

FIG. 2 is a main part configuration diagram of a CRC calculation unit in FIG. 1;

FIG. 3 is a main part configuration diagram of a third embodiment of the present invention.

FIG. 4 is a main part configuration diagram of another embodiment of the third invention.

FIG. 5 is a main part configuration diagram of a fourth embodiment of the present invention.

FIG. 6 is an explanatory diagram of a usage example of a CRC.

FIG. 7 is an explanatory diagram of a section requiring a CRC field.

FIG. 8 is an explanatory diagram of an ATM cell configuration.

FIG. 9 is an example of an apparatus configuration diagram for multiplexing four inputs from a transmission line.

FIG. 10 shows a CR added by adding another header to the original header.
FIG. 9 is an explanatory diagram in the case where the range protected by C is expanded.

11 is an example of a device configuration diagram having an additional header adding unit in the configuration of FIG. 9;

FIG. 12 is a configuration diagram of a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Detecting means 2 Computing means 4 Transmitter 5 Receiver 11 Latch 12 RAM 13 First gate means 14, 15 Control parts 21-28 Exclusive OR gate 31 Delay part 32 First selector 33 Second gate means 34 Second selector 41 CRC addition part 51 CRC processing part 52 Internal processing part 61 Reception part 62 Header rewriting part 63 Multiplexing part 65 Transmission part 64 Additional header addition part 71 Latch 72 RAM 73 Delay part 74 Selector 75 CRC calculation part

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Michio Kusanagi 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Setsuo Abiru 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa No. 1 Inside Fujitsu Limited (72) Inventor Shogo Miyabe 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor ▲ Masaki Hiro ▼ Ta Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture 4-1-1 1-1 Fujitsu Limited (72) Inventor Masamichi Kasa 3-2-28 Hakata Ekimae, Hakata-ku, Fukuoka City, Fukuoka Prefecture Inside Fujitsu Kyushu Digital Technology Co., Ltd.

Claims (4)

[Claims] In a device for transmitting information, in a state where a cyclic redundancy check code is incorporated in a field of network information or the like, when a part of the network information or the like is to be rewritten, Detecting means for comparing the value of the information and the bit of the rewritten information to detect and output a portion having a different value; calculating means for obtaining a cyclic redundancy check code for the output of the detecting means; Using the cyclic redundancy check code obtained by the arithmetic means, the cyclic redundancy check code of the portion of the original cyclic redundancy check code added to the information before rewriting whose information has been rewritten is used. Add check code to new cyclic redundancy check code Cyclic redundancy check code replacement circuit is characterized in that the configuration of providing the means. 2. A storage unit that, among the detection unit and the addition unit, stores the information before rewriting as an address and stores the information after rewriting in a storage area specified by the address.
The first gate means takes an exclusive OR of the information before rewriting and the information after writing read out from the storage means, and the adding means is adapted to execute the rewriting when the information after rewriting is input. When the subsequent information is selected and the rewritten information is not inputted, the first selector for selecting the delayed information before rewriting, the output of the arithmetic means, and the first selector passed through the first selector. Of the original cyclic redundancy check code added to the information before rewriting, exclusive OR of the cyclic redundancy check code of the part where the information was rewritten is added to the new cyclic redundancy check code. A second gate means for changing a check code and changing the check code; and a second selector for performing a select operation corresponding to an output state of the first selector and the second gate means. 3. The cyclic redundancy check code changing circuit according to claim 2, wherein the cyclic redundancy check code changing circuit is constituted by a circuit. 3. The information before rewriting is set as an address in the storage means, and the information after rewriting and the cyclic redundancy check code obtained by the arithmetic means are stored in a storage area specified by the address. 3. The cyclic redundancy check code changing circuit according to claim 1, wherein: 4. The first arithmetic means is connected to the input side of the storage means, the second arithmetic means is connected to the output side, and the input side of the second gate means to which the first selector is connected, 3. The cyclic redundancy check code changing circuit according to claim 2, wherein an output side of said first and second arithmetic means is connected.