JPH1167765A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device which can ensure sufficient flatness with good controllability and good productivity, when planarizing the surface of an interlayer insulating film. SOLUTION: A peripheral circuit element region 3 and a memory cell element region 2 which is higher than the region 3 are formed on a Si substrate 1 for forming an interlayer insulating film 4 on the entire surface of the Si substrate 1. The interlayer insulating film 4 is selectively etched with a resist pattern 5 as a mask to form projections 7 in a part, corresponding to the region near the peripheral part of the memory cell element region 2 and a part, corresponding to the inner region of the memory cell element region 2 and then the resist pattern 5 is removed and the projections 7 are removed by a chemical mechanical method. An interlayer insulating film 8 may be formed on the interlayer insulating film 4 by a bias ECR-CVD method, the projections 7 may be removed, and the surface of the interlayer insulating film 8 may be planarized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method suitable for flattening an interlayer insulating film.

[0002]

2. Description of the Related Art As a method of forming an interlayer insulating film on a semiconductor substrate having an element formed on its surface, conventionally, a BPSG film is deposited on a semiconductor substrate by a thermal CVD method.
There is known a method of performing a heat treatment at about 0 ° C. to reflow the BPSG film and smooth the surface of the BPSG film.

In recent years, efforts have been made to increase the resolution of a resist in a lithography process along with the miniaturization of design rules for semiconductor devices.
(s, DOF) is decreasing. This improvement must wait for the performance improvement of the resist, but at present, the request for the finer design rule precedes the performance improvement of the resist. In view of this, a method has been studied in which the height difference of the device structure is reduced as much as possible to compensate for the lack of depth of focus of the resist and to reliably resolve a fine pattern without causing a defocus.

[0004] In the case of the above-mentioned flattening by reflow of the BPSG film, since the surface can be smoothed, the resist followability in the lithography process is improved, and the resolution limit can be improved. However, in reality, it is hardly expected to reduce the global step in consideration of the decrease in the depth of focus.

[0005] Therefore, as a method of eliminating a surface step due to a height difference of a device structure and flattening the surface, recently, a chemical mechanical polishing (CMP) method using a mirror processing technique of a silicon (Si) wafer has been adopted. Have been. FIG.
FIG. 2 is a schematic diagram illustrating an example of a configuration of a CMP apparatus used for polishing by the CMP method.

[0006] As shown in FIG.
Polishing plate 10 having a polishing pad 101 adhered to the surface
2, a dresser 104 for sharpening the polishing pad 101, a carrier 106 for holding a substrate 105 to be processed such as a wafer, and a polishing pad 1 formed by electrodepositing a diamond powder 103 on a metal plate.
And a polishing slurry supply device 108 having a nozzle 107 for supplying the polishing slurry onto the nozzle. Here, the polishing plate 102, the dresser 104, and the carrier 106
Rotating shaft 109, rotating shaft 110 and rotating shaft 1 respectively
It is rotatable around 11.

[0007] The substrate 105 to be processed is
Is polished, the substrate 105 is attached to the carrier 106 via the back film 112 such that the polishing surface faces the polishing pad 101 side. After dressing (grinding) the polishing pad 102 with the dresser 104, the polishing plate 102 and the carrier 106 are moved to the rotating shaft 109 and the rotating shaft 1 respectively.
11 at a predetermined rotational speed, and the nozzle 107
The polishing pressure adjusting mechanism 113 supplies the polishing slurry to the central portion of the polishing pad 101 from
5 is pressed onto the polishing pad 101 to be processed 105
Is polished.

Here, a conventional method of planarizing an interlayer insulating film by a CMP method eliminates a step formed on the surface of the interlayer insulating film in a semiconductor memory device such as a DRAM and planarizes the surface of the interlayer insulating film. An example will be described.

That is, in this conventional method of planarizing an interlayer insulating film by the CMP method, first, as shown in FIG. 16, a cell part element region 202 and a cell element region 202 are formed on a Si substrate 201 in accordance with a normal DRAM manufacturing method. A peripheral circuit element region 203 is formed. At this time, the surface of the cell part element region 202 from the surface of the Si substrate 201 is
1 from the surface of the peripheral circuit element region 203 from the surface
For example, the height is increased by about 1 μm. The memory cell element region 202 has a rectangular planar shape of, for example, 4 mm × 6 mm. Here, in order to avoid complication of the drawing, the cell part element region 202 and the peripheral circuit part element region 203 are schematically shown.

Next, as shown in FIG.
An interlayer insulating film 204 such as a SiO ₂ film having a thickness of about 2 μm is formed on the entire surface of the substrate 1 by, for example, a CVD method. The interlayer insulating film 204 is conformally grown along the surface of the Si substrate 201, and a portion of the interlayer insulating film 204 corresponding to the memory cell element region 202 has a protrusion 2
04a is formed. Here, the height of the convex portion 204a of the interlayer insulating film 204, and thus the cell portion element region 20
The difference between the height of the surface of the interlayer insulating film 204 at the portion corresponding to No. 2 and the height of the surface of the interlayer insulating film 204 at the portion corresponding to the peripheral circuit element region 203 is the height of the surface of the cell portion element region 202. The difference from the height of the surface of the peripheral circuit element region 203 is almost the same, for example, about 1 μm.

Next, using the CMP apparatus shown in FIG.
The interlayer insulating film 204 is removed by about 1.2 μm from the surface of the projection 204a by the CMP method. At this time, first, after the protrusion 204a of the interlayer insulating film 204 having a height of about 1 μm is removed, the entire surface of the interlayer insulating film 204 is removed by about 0.2 μm. Thereby, as shown in FIG.
The height of the surface of the interlayer insulating film 204 in a portion corresponding to the cell portion element region 202 is equal to the height of the surface of the interlayer insulating film 204 in a portion corresponding to the peripheral circuit portion device region 203. Is flattened.

[0012]

However, the above-mentioned conventional method of planarizing an interlayer insulating film by the CMP method includes the following.
There were the following problems.

FIG. 19 shows that the SiO ₂ film is formed by CMP.
6 is a graph showing a change in the height of the surface of the SiO ₂ film with respect to a polishing time when the polishing is performed by a method. In FIG. 19, the horizontal axis represents the polishing time, and the vertical axis represents the height of the surface of the SiO ₂ film. The solid line is a graph showing the height of the surface of the flat portion of the SiO ₂ film, and the dotted line is a graph showing the height of the surface of the protrusion of the SiO ₂ film. As shown in FIG. 19, in the case of polishing by the CMP method, there is a characteristic that the polishing rate is lower in a wider flat portion and higher in a protruding portion such as a protrusion. This is because the effective polishing pressure of the polished surface depends on the area of the polished surface. For this reason, the CMP method has a great effect in that a flat surface is created by selectively removing and removing small projections at a high speed, whereas the CMP method reduces a step due to a wide flat region. In this regard, it can be seen that a great effect cannot be expected. For this reason, the above-described conventional C
In the case of the method of flattening the interlayer insulating film by the MP method, as shown in FIG. 17, a convex portion 204a formed in a portion of the interlayer insulating film 204 corresponding to the memory cell element region 202 is formed into one large flat surface. In order to reduce the step on the surface of the interlayer insulating film 204 by the CMP method, the area corresponding to the interlayer insulating film 204 in the portion corresponding to the memory cell portion element region 202 and the peripheral circuit portion 203 are reduced. Since the interlayer insulating film 204 in the portion is polished by an almost equal amount, there is a problem that it is theoretically difficult to reduce a step between the two.

Therefore, as a countermeasure against this, for example, Japanese Patent Laid-Open No. 147278/1995 discloses the following method for planarizing an interlayer insulating film by a CMP method. That is, in the method of planarizing the interlayer insulating film by the CMP method, as shown in FIG. 20, a resist pattern having an opening in a portion corresponding to the region inside the memory cell part element region 202 is formed on the interlayer insulating film 204. The interlayer insulating film 204 is selectively etched using the resist pattern 205 as a mask. Thereby, the interlayer insulating film 204
Of these, a portion corresponding to a region inside the memory cell portion element region 204 is removed by a desired depth, and a projection portion 206 is formed in a portion corresponding to a region near the peripheral portion of the memory cell portion element region 202. Next, after removing the resist pattern 205, the interlayer insulating film 204 is polished so that the protrusion 206 is removed by the CMP method. Thereby, the surface of the interlayer insulating film 204 is flattened.

However, this method of flattening the interlayer insulating film employs a method of forming the interlayer insulating film 204 in the memory cell element region 202.
When the polishing of the protrusions 206 formed in the portion corresponding to the region near the peripheral portion of the memory cell is started, the polishing of the portion of the interlayer insulating film 204 corresponding to the region near the center of the memory cell element region 202 is simultaneously performed. After the polishing by the CMP method, the memory cell portion is compared with the surface of a portion of the interlayer insulating film 204 corresponding to a region near the peripheral portion of the memory cell portion element region 202 where the protrusion portion 206 was located. There is a problem that the surface of a portion corresponding to a region near the center of the element region 202 is dented.

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device which has good controllability and productivity when planarizing the surface of an interlayer insulating film, and which can secure sufficient flatness. Is to do.

[0017]

In order to achieve the above object, a method of manufacturing a semiconductor device according to a first aspect of the present invention is directed to a method of manufacturing a semiconductor device, comprising: forming a first element region on a semiconductor substrate; Forming a second element region having a high height, forming an interlayer insulating film over the entire surface of the semiconductor substrate, and etching the region of the interlayer insulating film near the periphery of the second element region. Forming a protrusion on at least a portion corresponding to the region inside the second element region, and polishing the interlayer insulating film to remove at least the protrusion. It is characterized by the following.

According to a second aspect of the present invention, in a method of manufacturing a semiconductor device, a first element region and a second element region having a surface higher than the first element region are formed on a semiconductor substrate. Forming a first interlayer insulating film over the entire surface of the semiconductor substrate; and etching, by etching, a portion of the first interlayer insulating film corresponding to a region near a peripheral portion of the second element region; Forming a projection on at least a part of a portion corresponding to a region inside the element region of the first region, and forming a second interlayer insulating film on the first interlayer insulating film by bias applied high density plasma chemical vapor deposition. Forming a film and removing the protrusions.

According to the first aspect of the present invention, a portion of the interlayer insulating film corresponding to a region inside the second element region is provided.
It is preferable to form the projections regularly. Further, according to the second aspect of the present invention, the second interlayer insulating film is formed of a second material.
It is preferable that protrusions are regularly formed in a portion corresponding to a region inside the element region. In these cases,
More preferably, the protrusions are formed in a portion of the interlayer insulating film or the first interlayer insulating film corresponding to a region inside the second element region so that the protrusions are evenly dispersed.

In the first aspect of the present invention, typically, polishing of the interlayer insulating film is performed by a chemical mechanical polishing method.

In the present invention, typically, the second element region is a memory cell part element region, and the first element region is a peripheral circuit part element region.

According to the first aspect of the present invention configured as described above, at the stage when the interlayer insulating film is formed on the semiconductor substrate, the surface of the interlayer insulating film in a portion corresponding to the second element region is formed. In order to eliminate a step caused by being higher than the surface of the interlayer insulating film in a portion corresponding to the first element region, etching is performed on a region of the interlayer insulating film in the vicinity of a peripheral portion of the second element region. And forming at least part of the portion corresponding to the region inside the second element region, and then polishing the interlayer insulating film to remove at least the protrusion. By
As compared with the case where the interlayer insulating film is polished without forming a projection on the interlayer insulating film, the step can be easily eliminated and the controllability can be improved. In addition, the protruding portion is formed on the second insulating film.
Is formed not only in a portion corresponding to a region near a peripheral portion of the element region, but also in at least a part of a portion of the interlayer insulating film corresponding to a region inside the second element region. When the protrusion is removed by polishing, it is possible to effectively prevent the surface of a portion of the interlayer insulating film corresponding to a region near the center of the second element region from becoming concave.

According to the second aspect of the present invention configured as described above, by etching, a portion of the first interlayer insulating film corresponding to a region near the periphery of the second element region; After a projection is formed on at least a part of a portion corresponding to a region inside the second element region, a second interlayer insulating film is formed on the first interlayer insulating film by bias applied high density plasma chemical vapor deposition. By forming the insulating film to remove the protrusions, the characteristics of the bias-applied high-density plasma enhanced chemical vapor deposition method capable of performing etching and deposition simultaneously can be used. The second interlayer insulating film can be buried in the recesses between the protrusions formed in the first interlayer insulating film to remove the protrusions, and the second interlayer insulating film having a flat surface on the first interlayer insulating film can be removed. Easily and easily It can be sexual well formed.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. In all the drawings of the embodiments, the same or corresponding portions are denoted by the same reference numerals.

First, the method for fabricating the semiconductor device according to the first embodiment of the present invention will be described. In the first embodiment, a case where a step formed on the surface of an interlayer insulating film is eliminated and the surface of the interlayer insulating film is flattened in a semiconductor memory device such as a DRAM will be described as an example.

That is, in the method of manufacturing a semiconductor device according to the first embodiment, first, as shown in FIG. 1, a memory cell element region is formed on a Si substrate 1 in accordance with a normal DRAM manufacturing method. 2 and a peripheral circuit section element region 3 are formed. Here, the height of the surface of the memory cell part element region 2 from the surface of the semiconductor substrate 1 is, for example, about 1 μm higher than the height of the surface of the peripheral circuit part element region 3 from the surface of the semiconductor substrate 1. The memory cell element region 2 has a rectangular planar shape of, for example, 4 μm × 6 μm. Here, in order to avoid complication of the drawing, the memory cell part element region 2 and the peripheral circuit part element region 3 are schematically shown.

Next, as shown in FIG. 2, an interlayer insulating film 4 such as a SiO ₂ film is formed on the entire surface of the Si substrate 1 by, for example, a CVD method. Here, when the interlayer insulating film 4 is formed, the thickness of the interlayer insulating film 4 in a portion corresponding to the peripheral circuit part element region 3 is set to the value corresponding to the memory cell part element region 2.
Is larger than the height of the step caused by mismatch between the surface of the peripheral circuit element region 3 and the surface of the peripheral circuit element region 3. In this case, the thickness of the interlayer insulating film 4 is, for example, about 2 μm. The interlayer insulating film 4 is conformally grown along the surface of the Si substrate 1, and the surface of the interlayer insulating film 4 in a portion corresponding to the memory cell unit element region 2 is formed in the peripheral circuit unit element region 3. The height is higher than the surface of the interlayer insulating film in a corresponding portion, and a protrusion is formed in a portion of the interlayer insulating film 4 corresponding to the memory cell element region 2. In this case, the difference between the height of the surface of the interlayer insulating film 4 at the portion corresponding to the memory cell element region 2 and the height of the surface of the interlayer insulating film 4 at the portion corresponding to the peripheral circuit element region 3 is the memory cell The difference between the surface height of the element region 2 and the surface height of the peripheral circuit element region 3 is substantially the same, for example, about 1 μm.

Next, as shown in FIG. 3, a resist pattern 5 is formed on the interlayer insulating film 4 by, for example, a lithography process. The resist pattern 5 includes, in a portion corresponding to the memory cell part element region 2, a region near the periphery of the memory cell part element region 2 and a part near the memory cell part element region 2.
The opening 5a is provided in a portion excluding a part of a portion corresponding to the internal region of.

FIG. 4 is a plan view showing a state when the resist pattern 5 is formed. In this case, as shown in FIG. 4, the resist pattern 5 has a lattice-shaped opening 5a in a portion corresponding to the memory cell element region 2 and a portion corresponding to a region inside the memory cell element region 2. Has a plurality of island-shaped portions 5b. Here, the end of the opening 5 a of the resist pattern 5 is located on the memory cell part element region 2, for example, about 10 μm inside the memory cell part element region 2 from the outer peripheral part of the memory cell part element region 2. doing. The island portion 5b of the resist pattern 5 has a substantially square planar shape, and the size of one side is, for example, about 100 μm or more or about millimeter order. In this case, the plurality of island-shaped portions 5b are regularly arranged in a portion corresponding to a region inside the memory cell element region 2. Note that the end of the opening 5a of the resist pattern 5 does not have to be displaced from the memory cell element region 2 so that the position of the mask during exposure in the lithography step for forming the resist pattern 5 can be reduced. The alignment can be performed with a rough accuracy of about 10 μm. Therefore, when the resist pattern 5 is formed, there is an advantage that the load on the lithography process is reduced, for example, the reproduction rate is improved.

Next, as shown in FIG. 5, using the resist pattern 5 as a mask, the interlayer insulating film 4 is selectively etched by, for example, a dry etching method. As a result, a recess 6 is formed in a portion of the interlayer insulating film 4 corresponding to the opening 5a of the resist pattern 5, and a portion corresponding to a region near a peripheral portion of the memory cell element region 2 and a memory cell Of the portion corresponding to the region inside the element region 2 (in this case, the island-shaped portion 5 of the resist pattern 5).
(corresponding to b)). At this time, the etching depth of the interlayer insulating film 4 is set so that the bottom surface of the concave portion 6 formed by etching is not lower than the surface of the interlayer insulating film 4 in a portion corresponding to the peripheral circuit element region 3. You can choose the desired value. Here, the etching depth of the interlayer insulating film 4, that is, the depth of the recess 6 is, for example, about 1 μm.
In this case, the depth of the concave portion 6 is almost equal to the height of the step between the surface of the memory cell portion element region 2 and the surface of the peripheral circuit portion element region 3, and the height of the surface of the interlayer insulating film 4 at the bottom of the concave portion 6. The height is almost equal to the height of the surface of the interlayer insulating film 4 in a portion corresponding to the peripheral circuit element region 3.

FIG. 6 is a plan view showing a state when the interlayer insulating film 4 is etched using the resist pattern 5 as a mask. In FIG. 6, the resist pattern 5 is not shown. In this case, as shown in FIG. 6, a portion of the interlayer insulating film 4 corresponding to a region near the peripheral portion of the memory cell portion element region 2 is provided in the memory cell portion element region 2.
Are formed so as to border the outer periphery of the portion corresponding to..., And a plurality of island-shaped protrusions 7 are formed in the portion corresponding to the region inside the memory cell element region 2. A plurality of island-shaped protrusions 7 formed in a portion of the interlayer insulating film 4 corresponding to a region inside the memory cell part element region 2 are regularly formed in a part corresponding to the inside of the memory cell part element region 2. , And are dispersed on average. Note that these protrusions 7 are formed on protrusions formed in a portion of the interlayer insulating film 4 corresponding to the memory cell element region 2. Here, in the portion of the interlayer insulating film 4 corresponding to the memory cell element region 2, it is preferable that the occupied area of the recess 6 be larger than the occupied area of the projection 7. In this case, the area occupancy of the protrusion 7 in a portion of the interlayer insulating film 4 corresponding to the memory cell element region 2 is, for example, 25% or less.

Next, after removing the resist pattern 5,
As shown in FIG. 7, the surface of the interlayer insulating film 4 is planarized by polishing the interlayer insulating film 4 by the CMP method. At this time, the memory cell part element region 2 of the interlayer insulating film 4
Is polished until the thickness at the portion corresponding to is, for example, about 0.5 μm. As an example of polishing conditions by the CMP method, a polishing pad of polyurethane polyurethane and a slurry containing silica particles based on KOH are used, the polishing pressure is 5 × 10 ⁴ Pa, and the rotation speed of the platen is 20 rpm. At this time, the polishing rate on the flat surface of the SiO ₂ film is about 150 nm / min. Under such conditions, when polishing is performed until the thickness of the portion of the interlayer insulating film 4 corresponding to the memory cell element region 2 becomes 0.5 μm,
The polishing time is about 2.5 minutes.

As described above, the step existing in the interlayer insulating film 4 at the stage of forming the interlayer insulating film 4 is eliminated, and the surface of the interlayer insulating film 4 is flattened.

According to the first embodiment configured as described above, the interlayer insulating film 4 is formed on the Si substrate 1 on which the memory cell element region 2 and the peripheral circuit element region 3 are formed. By selectively etching the interlayer insulating film 4 using the resist pattern 5 as a mask, a portion of the interlayer insulating film 4 corresponding to the peripheral region of the memory cell unit element region 2 and the memory cell unit element region The projections 7 are formed on a part of the portion corresponding to the area inside 2. In this case, the area occupancy of the protrusion 7 in the portion of the interlayer insulating film 4 corresponding to the memory cell element region 2 is low. Therefore, according to the first embodiment, even when the step formed of a wide flat area is formed in the interlayer insulating film 4, the protrusion 7 of the interlayer insulating film 4 is polished and removed by the CMP method. By doing so, the surface of the interlayer insulating film 4 can be flattened in an extremely short polishing time, so that productivity can be improved.

Further, since the removal and confirmation of the removal of the protrusion 7 are easy and the amount of polishing is easy to control, the surface of the interlayer insulating film 4 can be flattened with good controllability.
Therefore, the controllability of the thickness of the interlayer insulating film 4 after the planarization is improved, so that the processing of the connection holes and the like in the interlayer insulating film 4 becomes easy, and the interlayer insulating film 4 is formed on the interlayer insulating film 4. There is a problem of poor conduction due to difficulty in filling the conductive film into the connection holes and the like, an increase in parasitic capacitance caused by the reduction in the thickness of the interlayer insulating film 4, and an electrical failure such as poor electrical insulation. It is possible to effectively prevent the problem of characteristic deterioration and the like.

According to the first embodiment, in addition to the portion of the interlayer insulating film 4 corresponding to the region near the peripheral portion of the memory cell portion element region 2, the memory cell portion element region of the interlayer insulating film 4 When the protrusions 7 are removed by polishing the interlayer insulating film 4 by the CMP method, the protrusions 7 are partially formed also in the portions corresponding to the regions inside the substrate 2.
It is possible to effectively prevent the surface of the interlayer insulating film 4 in the region near the center of the memory cell element region 2 from being depressed. Thereby, after planarization by the CMP method,
The interlayer insulating film 4 having extremely high surface flatness can be obtained. For this reason, flatness corresponding to a small depth of focus, which is required for resolution of a fine pattern in a lithography process, can be ensured.

Next, the method for fabricating the semiconductor device according to the second embodiment of the present invention will be described. FIG. 8 is a plan view for explaining the method for manufacturing the semiconductor device according to the second embodiment.

That is, in the method of manufacturing the semiconductor device according to the second embodiment, as shown in FIG. 8, the interlayer insulating film 4 is selectively etched using a resist pattern (not shown) of a predetermined shape as a mask. Thus, the protrusion 7 is formed in a portion of the interlayer insulating film 4 corresponding to a region near the peripheral portion of the memory cell portion element region 2, and the protrusion 7 is formed in the region of the interlayer insulating film 4 in the memory cell portion element region 2 A plurality of stripe-shaped protrusions 7 are formed in the portions to be formed.
In this case, the stripe-shaped protrusions 7 formed in the portion of the interlayer insulating film 4 corresponding to the region inside the memory cell portion element region 2 are formed near the peripheral portion of the memory cell portion element region 2 of the interlayer insulating film 4. It is connected to a protrusion 7 formed at a portion corresponding to the region. In this case, the width of the stripe-shaped protrusion 7 formed in a portion of the interlayer insulating film 4 corresponding to the region inside the memory cell element region 2 is, for example, about 100 μm or more or about millimeters. The other points are the same as those of the method for manufacturing the semiconductor device according to the first embodiment, and the description is omitted.

According to the second embodiment, the same effect as that of the first embodiment can be obtained.

Next, the method for fabricating the semiconductor device according to the third embodiment of the present invention will be explained. FIG. 9 is a plan view for explaining the method for manufacturing the semiconductor device according to the third embodiment.

That is, in the method of manufacturing the semiconductor device according to the second embodiment described above, the stripe-shaped protrusions 7 formed in the portion of the interlayer insulating film 4 corresponding to the region inside the memory cell element region 2 are provided. Has a shape connected to a protrusion 7 formed in a portion of the interlayer insulating film 4 corresponding to a region near the periphery of the memory cell element region 2,
In the method of manufacturing the semiconductor device according to the third embodiment, as shown in FIG. 9, the stripe-shaped protrusions 7 in the portion of the interlayer insulating film 4 corresponding to the area inside the memory cell element region 2 are formed. The interlayer insulating film 4 is formed separately from the protrusion 7 at a portion corresponding to a region near the peripheral portion of the memory cell element region 2. The other points are the same as those in the method for manufacturing the semiconductor device according to the first embodiment.
Description is omitted.

According to the third embodiment, the same effect as in the first embodiment can be obtained.

Next, the method for fabricating the semiconductor device according to the fourth embodiment of the present invention will be explained. FIG. 10 is a plan view for explaining the method for manufacturing the semiconductor device according to the fourth embodiment.

That is, in the method for fabricating a semiconductor device according to the fourth embodiment, as shown in FIG. 10, the interlayer insulating film 4 is selectively etched using a resist pattern (not shown) having a predetermined shape as a mask. As a result, a lattice-like projection 7 is formed in a portion of the interlayer insulating film 4 corresponding to the memory cell element region 2. Other things are number one
Since the method is the same as the method for manufacturing the semiconductor device according to the embodiment, the description thereof will be omitted.

According to the fourth embodiment, the same effect as that of the first embodiment can be obtained.

Next, the method for fabricating the semiconductor device according to the fifth embodiment of the present invention will be explained. FIG. 11 is a plan view for explaining the method for manufacturing the semiconductor device according to the fifth embodiment.

That is, for example, in the method of manufacturing the semiconductor device according to the above-described first embodiment, the interlayer insulating film 4
When the projections 7 are formed at a portion corresponding to a region near the peripheral portion of the memory cell element region 2, the projections 7 are formed with a substantially uniform width. 5
In the method of manufacturing the semiconductor device according to the embodiment, when forming the protrusion 7 in the interlayer insulating film 4, a portion of the interlayer insulating film 4 corresponding to a region near the periphery of the memory cell element region 2 is formed. The width of 7 is partially increased.
In this case, a part of the protrusion 7 formed in a portion of the interlayer insulating film 4 corresponding to a region near the peripheral portion of the memory cell part element region 2 is replaced with a part corresponding to a region inside the memory cell part element region 2. Is also formed in part. In this case, from the viewpoint of effectively preventing the surface of the portion of the interlayer insulating film 4 corresponding to the region near the center of the memory cell element region 2 from being dented when the interlayer insulating film 4 is polished by the CMP method. It is preferable that the protruding portion 7 has a shape that is deeply involved in a portion corresponding to the region inside the memory cell element region 2. The other points are the same as those of the method for manufacturing the semiconductor device according to the first embodiment, and the description is omitted.

According to the fifth embodiment, the same effect as that of the first embodiment can be obtained.

Next, the method for fabricating the semiconductor device according to the sixth embodiment of the present invention will be explained.

That is, in the method of manufacturing a semiconductor device according to the sixth embodiment, a resist pattern is formed on the interlayer insulating film 4 according to the same steps as those of the method of manufacturing a semiconductor device according to the first embodiment. After selectively etching the interlayer insulating film 4 using the resist pattern as a mask, the resist pattern used as the etching mask is removed. Thereby, as shown in FIG. 12, a recess 6 is formed in a portion of the interlayer insulating film 4 corresponding to the opening of the resist pattern (not shown), and a peripheral portion of the memory cell element region 2 is formed. Protrusions 7 are formed in a portion corresponding to a nearby region and a part of a portion corresponding to a region inside memory cell element region 2. In this case, the width of the protruding portion 7 formed in a portion of the interlayer insulating film 4 corresponding to the region inside the memory cell element region 2 is
12 is larger than the width of the protrusion 7 (portion 7 'in FIG. 12) formed in a portion corresponding to a region near the peripheral portion of the memory cell element region 2. Here, the width of the projection 7 formed in a portion of the interlayer insulating film 4 corresponding to the region inside the memory cell element region 2 is, for example, 20 μm.
As described above, specifically, the thickness is, for example, about 100 μm. Also,
A protrusion 7 (a portion indicated by reference numeral 7 ′) formed in a portion of the interlayer insulating film 4 corresponding to a region near the peripheral portion of the memory cell portion element region 2 is, for example, 1
They overlap by about 0 μm. A plan view in this state is the same as, for example, FIG. 7 of the first embodiment.

In FIG. 12, D ₁ is the height of the step on the surface of the Si substrate 1 (the height of the surface of the memory cell element region 2 from the surface of the Si substrate 1 and the height of the step from the surface of the Si substrate 1). Difference from the height of the surface of the peripheral circuit element region 3). D ₂ is the thickness of the interlayer insulating film 4, D ₃ is the depth of the recess 6 corresponding to the etching depth of the interlayer insulating film 4, D ₄ is the interlayer insulating film 4 in the portion corresponding to the recess 6 thickness, A ₁ denotes the width of the protrusion 7 formed in a portion of the interlayer insulating film 4 corresponding to the region inside the memory cell element region 2, and A ₂ denotes the width of the recess 6. In this case, the height D ₁ of the step on the surface of the Si substrate 1 and the thickness D ₂ of the interlayer insulating film 4 satisfy the relationship of D ₁ ≦ D ₂ ,
The height D ₁ of the step on the surface of the i-substrate 1 and the depth D of the recess 6
₃ satisfies the relationship of D ₁ ≧ D ₃ . The thickness D ₄ of the interlayer insulating film 4 at the portion corresponding to the concave portion 6 is D ₄ ≧ 0.
It has become. Here, for example, D ₁ = D ₃ = 1 μm
And D ₂ = 2 μm. In addition, the aspect ratio of the concave portion 6, that is, D ₃ / A ₂ is, for example, D ₃ / A ₂
It is selected so as to satisfy the relationship of ≦ 2.5.

Next, as shown in FIG.
On top, a high-density plasma CVD method, for example, bias EC
An interlayer insulating film 8 such as a SiO ₂ film is formed by the R-CVD method. In the bias ECR-CVD method, the etching and the deposition can be performed simultaneously. Therefore, the interlayer insulating film 8 is formed so as to have a flat surface, including the elimination of the unevenness due to the projections 7. Can be formed. The thickness of the interlayer insulating film 8 in the portions corresponding to the recesses _{6, D 3 + A 1/2} (D 3 is the recess 6 depths, A ₁ is a memory cell section element region 2 of the interlayer insulating film 4 (The width of the protrusion 7 formed in a portion corresponding to the internal region).
An example of conditions for forming the interlayer insulating film 8 by the bias ECR-CVD method is as follows.
₄ , a mixed gas of O ₂ and Ar, and the flow rates of SiH ₄ gas, O ₂ gas and Ar gas are each 80 sc.
cm, 120 sccm, 150 sccm, pressure 0.5 Pa, microwave output 1500 W, high frequency (R
F) Output is 2000W. Under such conditions, the time required to form the interlayer insulating film 8 so that its surface becomes flat, including the elimination of the protrusions 7, is about 2.5 minutes.

Referring to FIG. 14, bias ECR- is formed on interlayer insulating film 4 having concave portions 6 and projecting portions 7.
The state of deposition of the interlayer insulating film 8 when the interlayer insulating film 8 is formed by the CVD method will be described.

That is, as shown in FIG. 14, when the interlayer insulating film 8 is formed by the bias ECR-CVD method on the interlayer insulating film 4 on which the concave portions 6 and the protrusions 7 are formed,
An interlayer insulating film 8 is flatly deposited on the interlayer insulating film 4 and the concave portion 6 in a portion corresponding to the peripheral circuit element region 3, and the interlayer insulating film 8 is formed on the protrusion 7 inward from the edge portion. , For example, while forming a slope inclined at 45 °. Then, the deposition of the interlayer insulating film 8 proceeds, and the concave portions 6 are formed.
Are filled with the interlayer insulating film 8, and as the state of the interlayer insulating film 8 changes from the state I to the state II, the height of the interlayer insulating film 8 protruding from the portion above the protrusion 7 decreases,
When the state of the interlayer insulating film 8 becomes the state III,
Thickness B of interlayer insulating film 8 at a portion corresponding to protrusion 7
_{There, B = A 1/2 (} A 1 , an interlayer width of the protrusion 7 formed in the portion corresponding to the inside of the memory cell portion element region 2 of the insulating film 4) becomes, the interlayer insulating film 8 The surface becomes flat. Therefore, the thickness of the interlayer insulating film 8 in the portions corresponding to the recess 6 by a D ₃ + A _1/2 or more, the surface of the interlayer insulating film 8 it can be seen that becomes flat.

As described above, the surface of the interlayer insulating film 8 is flattened, including the elimination of the protrusions 7 formed on the interlayer insulating film 4.

According to the sixth embodiment configured as described above, the interlayer insulating film 4 is selectively etched, so that the portion of the interlayer insulating film 4 near the peripheral portion of the memory cell element region 2 is formed. Are formed on a portion corresponding to the region corresponding to the region E and a portion corresponding to the region inside the memory cell element region 2, and then a bias E is formed on the interlayer insulating film 4.
Since the interlayer insulating film 8 is formed by the CR-CVD method, the interlayer insulating film 8 is formed on the interlayer insulating film 4 by utilizing the characteristics of the bias ECR-CVD method in which etching and deposition can be performed simultaneously. The protrusion 7 can be removed by embedding the interlayer insulating film 8 in the recess 6 thus formed, and the interlayer insulating film 8 having a flat surface on the interlayer insulating film 4.
Can be formed. At this time, the thickness of the interlayer insulating film 8 in a portion corresponding to the concave portion 6 of the interlayer insulating film 4 is D
₃ + A _1/2 (although, D ₃ is the depth of the recess 6, A ₁ is the width of the protrusion 7 formed in the portion corresponding to the inside of the memory cell portion element region 2 of the interlayer insulating film 4) or If,
Since the surface of the interlayer insulating film 8 can be made flat, the interlayer insulating film 8 having a flat surface can be formed with good controllability and good flatness. In this case, since the interlayer insulating film 8 is formed by the bias ECR-CVD method, unlike the case where the planarization is performed by the CMP method,
It also has the advantage of not scratching the surface.

Further, according to the sixth embodiment, the time required for eliminating the protrusion 7 formed on the interlayer insulating film 4 and forming the interlayer insulating film 8 so that the surface becomes flat is obtained. Since the interlayer insulating film 8 having a short surface and a flat surface can be obtained without polishing by a CMP method which necessarily involves an additional step, the productivity is good.
In this case, reducing the width A ₁ of the protrusion 7 formed in the portion corresponding to the inside of the memory cell portion element region 2 of the interlayer insulating film 4, interlayer insulating necessary to flatten the surface Since the thickness of the film 8 can be small, the interlayer insulating film 8
Can be further reduced.

Therefore, according to the sixth embodiment, effects similar to those of the first embodiment can be obtained.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above embodiments, and various modifications based on the technical concept of the present invention are possible. For example, numerical values, materials, structures, process conditions, and the like described in the embodiments are merely examples, and the present invention is not limited thereto. Specifically, for example, the structures of the protrusions 7 formed on the interlayer insulating film 4 shown in the above-described first to sixth embodiments are merely examples, and the structures of the protrusions 7 are as follows. Various other variations are conceivable.

In the first embodiment described above,
The etching depth of the interlayer insulating film 4, that is, the depth of the recess 6 is about 1 μm, which is almost equal to the height of the step formed in the interlayer insulating film 4.
The height may be smaller than the height of the step formed in the interlayer insulating film 4. Specifically, for example, the depth of the concave portion 6 is set to 0.5 μm.
m. In this case, by making the depth of the concave portion 6 smaller than that in the first embodiment, the height of the protrusion 7 can be reduced, and the amount of polishing for removing the protrusion 7 can be reduced. It becomes possible. In this case, by simply removing the projections 7 by the CMP method, a smooth shape is formed between the portion of the interlayer insulating film 4 corresponding to the memory cell element region 2 and the peripheral circuit element region 3. Despite this, the step remains, so the recess 6
Is smaller than the height of the step formed in the interlayer insulating film 4 only when there is a margin in the lithography process, that is, when the allowable range for the depth of focus is wide. The amount can be greatly reduced, and there is a great process advantage in terms of productivity.

In the sixth embodiment described above,
The interlayer insulating film 8 is formed by a bias ECR-CVD method. The interlayer insulating film 8 is formed, for example, by a bias application type ICP (Inductively Coupled Plasma) -CVD.
It is also possible to form by a bias method or a helicon wave plasma CVD method of a bias application type.

In the above-described sixth embodiment,
A portion of the interlayer insulating film 4 corresponding to a region near a peripheral portion of the memory cell portion element region 2;
Is formed in a portion corresponding to a region inside the semiconductor device. In this case, the protrusion 7 corresponds to a region of the interlayer insulating film 4 near a peripheral portion of the memory cell element region 2. It may be formed only in a part.

In the first to sixth embodiments,
Although the present invention has been described for the case where the present invention is applied to the planarization of an interlayer insulating film in a semiconductor memory device, the present invention can be widely applied to the manufacture of other semiconductor devices in addition to the semiconductor memory device.

[0064]

As described above, according to the first aspect of the present invention, when the interlayer insulating film is formed on the semiconductor substrate, the surface of the interlayer insulating film in a portion corresponding to the second element region is formed. Eliminates a step caused by being higher than the surface of the interlayer insulating film in a portion corresponding to the first element region, and when flattening the surface of the interlayer insulating film, etching of the interlayer insulating film By adding a simple step of forming a projection at a portion corresponding to a region near the peripheral portion of the second element region and at least a part of a portion corresponding to a region inside the second element region By polishing the interlayer insulating film to remove at least the protrusions, the surface of the interlayer insulating film can be planarized with excellent controllability and productivity with an extremely short polishing time. Further, the protrusion is not only a portion corresponding to a region near a peripheral portion of the second element region of the interlayer insulating film, but also at least a part of a portion corresponding to a region inside the second element region of the interlayer insulating film. When the protrusion is removed by polishing the interlayer insulating film, the surface of the interlayer insulating film in a portion corresponding to the vicinity of the center of the second element region has a concave shape. This can be prevented, and the flatness of the surface of the interlayer insulating film after flattening can be made extremely good. Therefore, flatness corresponding to a small depth of focus, which is required for resolving a fine pattern in a lithography process, can be ensured.

According to the second aspect of the present invention, by etching, a portion of the first interlayer insulating film corresponding to a region near the peripheral portion of the second element region and the inside of the second element region. After forming a protrusion on at least a part of a portion corresponding to the region, a second interlayer insulating film is formed on the first interlayer insulating film by a bias applied high density plasma chemical vapor deposition method. By removing the part,
Utilizing the characteristics of the bias-applied high-density plasma-enhanced chemical vapor deposition method in which etching and deposition can be performed simultaneously, the second interlayer insulating film is formed in a concave portion between the projecting portions formed in the first interlayer insulating film. The protrusion can be removed by embedding the insulating film, and the second interlayer insulating film having a flat surface can be easily and well controlled on the first interlayer insulating film. it can. Thereby, the same effect as in the first embodiment can be obtained.

[Brief description of the drawings]

FIG. 1 is a sectional view for explaining a method for manufacturing a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 3 is a sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 4 is a plan view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 5 is a sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 6 is a plan view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 7 is a sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 8 is a plan view for explaining the method for manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 9 is a plan view for explaining the method for manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 10 is a plan view for explaining the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention.

FIG. 11 is a plan view for explaining a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention.

FIG. 12 is a sectional view for explaining the method for manufacturing a semiconductor device according to the sixth embodiment of the present invention;

FIG. 13 is a cross-sectional view of a method for fabricating a semiconductor device according to a sixth embodiment of the present invention, in which an interlayer insulating film is formed by a bias ECR-CVD method on an interlayer insulating film having a concave portion and a protrusion. It is an expanded sectional view for explaining a situation of film deposition.

FIG. 14 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the sixth embodiment of the present invention.

FIG. 15 is a schematic diagram illustrating a configuration example of a CMP apparatus used for polishing by a CMP method.

FIG. 16 is a cross-sectional view for explaining a conventional method for planarizing an interlayer insulating film.

FIG. 17 is a cross-sectional view for explaining a conventional method for planarizing an interlayer insulating film.

FIG. 18 is a cross-sectional view for explaining a conventional method for planarizing an interlayer insulating film.

FIG. 19 is a graph showing a change in the thickness of the SiO ₂ film with respect to the polishing time when the SiO ₂ film is polished by the CMP method.

FIG. 20 is a cross-sectional view for explaining a conventional method for planarizing an interlayer insulating film.

[Explanation of symbols]

1 ... Si substrate, 2 ... Memory cell part element region, 3
... peripheral circuit element region, 4, 8 ... interlayer insulating film,
5: resist pattern, 5a: opening, 5b
..Island-shaped portions, 6 concave portions, 7 projected portions

Claims (13)

[Claims] A step of forming a first element region and a second element region having a surface height higher than that of the first element region on a semiconductor substrate; and forming an interlayer insulating film on the entire surface of the semiconductor substrate. And at least part of a portion of the interlayer insulating film corresponding to a region near a peripheral portion of the second element region and a portion corresponding to a region inside the second element region, by etching. A method of manufacturing a semiconductor device, comprising: a step of forming a projection part; and a step of polishing the interlayer insulating film to remove at least the projection part. 2. The semiconductor device according to claim 1, wherein said protrusions are regularly formed in a portion of said interlayer insulating film corresponding to a region inside said second element region. Manufacturing method. 3. The plurality of island-shaped protrusions are formed in a portion of the interlayer insulating film corresponding to a region inside the second element region. A method for manufacturing a semiconductor device. 4. The semiconductor device according to claim 1, wherein the plurality of stripe-shaped protrusions are formed in a portion of the interlayer insulating film corresponding to a region inside the second element region. A method for manufacturing a semiconductor device. 5. The semiconductor device according to claim 1, wherein said lattice-shaped protrusion is formed in a portion of said interlayer insulating film corresponding to a region inside said second element region. Manufacturing method. 6. The method according to claim 1, wherein the second element region is a memory cell part element region, and the first element region is a peripheral circuit part element region. 7. A step of forming a first element region and a second element region having a surface height higher than that of the first element region on a semiconductor substrate; Forming a film; and etching, by etching, a portion of the first interlayer insulating film corresponding to a region near a periphery of the second element region;
Forming a protrusion on at least a part of a portion corresponding to a region inside the second element region; Forming a second interlayer insulating film and removing the protruding portion. 8. The method of manufacturing a semiconductor device according to claim 7, wherein an aspect ratio of the recess between the projections is 2.5 or less. 9. The projection according to claim 7, wherein said projections are regularly formed in a portion of said first interlayer insulating film corresponding to a region inside said second element region. Of manufacturing a semiconductor device. 10. A plurality of island-shaped protrusions are formed in a portion of the first interlayer insulating film corresponding to a region inside the second element region. 8. The method for manufacturing a semiconductor device according to item 7. 11. A plurality of stripe-shaped protrusions are formed in a portion of the first interlayer insulating film corresponding to a region inside the second element region. 8. The method for manufacturing a semiconductor device according to item 7. 12. The semiconductor device according to claim 7, wherein said lattice-shaped protrusion is formed in a portion of said interlayer insulating film corresponding to a region inside said second element region. Manufacturing method. 13. The method according to claim 7, wherein the second element region is a memory cell part element region, and the first element region is a peripheral circuit part element region.