JPH09246219A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH09246219A JPH09246219A JP5471896A JP5471896A JPH09246219A JP H09246219 A JPH09246219 A JP H09246219A JP 5471896 A JP5471896 A JP 5471896A JP 5471896 A JP5471896 A JP 5471896A JP H09246219 A JPH09246219 A JP H09246219A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- interlayer insulating
- film
- stopper
- cmp
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Mechanical Treatment Of Semiconductor (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置の製造
方法に係り、特に半導体基板上の層間絶縁膜の表面を化
学機械研磨（ＣＭＰ；Chemical Mechanical Polishing
）技術により平坦化する方法に関するもので、例えば
埋め込み素子分離（ＳＴＩ；Shallow TrenchIsolatio
n）の平坦化などに使用されるものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a surface of an interlayer insulating film on a semiconductor substrate, which is subjected to chemical mechanical polishing (CMP).
) Technology for planarization, for example, buried element isolation (STI; Shallow Trench Isolation)
n) is used for flattening.
【０００２】[0002]
【従来の技術】従来、半導体基板上の層間絶縁膜の表面
を平坦化する方法として、（１）多層エッチバック法、
（２）レジストエッチバック法、（３）リフロープロセ
スなどのほかに、（４）ＣＭＰ法が知られている。2. Description of the Related Art Conventionally, as a method for flattening the surface of an interlayer insulating film on a semiconductor substrate, (1) a multilayer etch back method,
Besides (2) resist etch back method, (3) reflow process, etc., (4) CMP method is known.
【０００３】前記多層エッチバック法は、層間絶縁膜上
にステップカバレッジのよい絶縁膜を堆積させ、反応性
イオンエッチング（ＲＩＥ；Reactive Ion Etching）法
によるドライエッチングして平坦化する方法である。The multilayer etch back method is a method of depositing an insulating film having good step coverage on an interlayer insulating film and flattening it by dry etching by a reactive ion etching (RIE) method.
【０００４】前記レジストエッチバック法は、層間絶縁
膜上にフォトレジストを塗布して層間膜とレジストとを
同じ選択比でＲＩＥ法によりエッチングして平坦化する
方法である。The resist etch-back method is a method in which a photoresist is applied on an interlayer insulating film and the interlayer film and the resist are flattened by etching by the RIE method at the same selection ratio.
【０００５】前記リフロープロセスは、半導体基板上に
リフロー性を有するボロン・リン・シリケートガラス
（ＢＰＳＧ；Borophosphosilicate Glass ）膜を形成し
た後に熱により粘性流動を起こさせて平坦化する方法で
ある。The reflow process is a method in which a boron-phosphosilicate glass (BPSG) film having a reflow property is formed on a semiconductor substrate and then viscous flow is caused by heat to flatten the film.
【０００６】これらの（１）〜（３）の方法では平坦化
に限界があり、これらに代わる方法として（４）のＣＭ
Ｐ法が実用化されている。このＣＭＰ法は、スラリーと
呼ばれる研磨材を半導体基板上の例えば層間絶縁膜上に
流しながら、化学的かつ機械的に層間膜表面を研磨して
平坦化する方法であり、半導体デバイスの微細化が進む
中で新しい平坦化技術として着目されている。[0006] These methods (1) to (3) have a limitation in flattening, and as an alternative method, the CM of (4) is used.
The P method has been put to practical use. This CMP method is a method of polishing the surface of an interlayer film chemically and mechanically and flattening it while flowing an abrasive material called a slurry onto, for example, an interlayer insulating film on a semiconductor substrate. As it progresses, it is attracting attention as a new flattening technology.
【０００７】しかし、ＣＭＰ法にもいろいろな問題があ
ることが分かってきた。その一つが平坦化の対象となる
基板表面上の層間絶縁膜のパターンに依存して平坦化の
程度が異なる（パターン依存性を持つ）ことである。However, it has been found that the CMP method also has various problems. One of them is that the degree of planarization varies (has pattern dependence) depending on the pattern of the interlayer insulating film on the substrate surface to be planarized.
【０００８】即ち、図３に示すように、層間絶縁膜３０
の表面に大きさの異なる凸部３１、３２が存在すると、
ＣＭＰ法により平坦化しようとした場合、面積が小さい
方の凸部３１は完全に平坦化されるが、面積が大きい方
の凸部３２は段差が残ってしまう。That is, as shown in FIG. 3, the interlayer insulating film 30 is formed.
If convex portions 31 and 32 having different sizes are present on the surface of
When it is attempted to flatten by the CMP method, the convex portion 31 having a smaller area is completely planarized, but the convex portion 32 having a larger area leaves a step.
【０００９】このように、面積が小さい方の凸部３１の
ような密なパターンと面積が大きい方の凸部３２のよう
な粗なパターンとが混在しているパターンをＣＭＰ法に
より平坦化しようとした場合、密なパターンと粗なパタ
ーンとではポリッシングレートが異なる（密なパターン
のポリッシングレートが粗なパターンのポリッシングレ
ートよりも遅くなる）ので、粗なパターンは完全に平坦
化されるが、密なパターンは段差が残ってしまうので、
均一なポリッシングが不可能であった。As described above, the pattern in which the dense pattern such as the convex portion 31 having the smaller area and the coarse pattern such as the convex portion 32 having the larger area are mixed is flattened by the CMP method. In that case, since the polishing rate is different between the dense pattern and the rough pattern (the polishing rate of the dense pattern becomes slower than the polishing rate of the rough pattern), the rough pattern is completely flattened, Since a dense pattern leaves a step,
Uniform polishing was impossible.
【００１０】[0010]
【発明が解決しようとする課題】上記したように従来の
ＣＭＰ法は、平坦化の対象となる基板表面上の層間絶縁
膜のパターンに依存して平坦化の程度が異なるという問
題があった。本発明は上記の問題点を解決すべくなされ
たもので、ＣＭＰ法による平坦化の対象となる基板表面
上の層間絶縁膜のパターンに依存せずに平坦化し得る半
導体装置の製造方法を提供することを目的とする。As described above, the conventional CMP method has a problem that the degree of planarization varies depending on the pattern of the interlayer insulating film on the surface of the substrate to be planarized. The present invention has been made to solve the above problems, and provides a method for manufacturing a semiconductor device that can be planarized without depending on the pattern of the interlayer insulating film on the surface of the substrate to be planarized by the CMP method. The purpose is to
【００１１】[0011]
【課題を解決するための手段】本発明の半導体装置の製
造方法は、半導体基板上に形成され、その表面に粗密な
凹凸形状を有し、局所的な範囲において凸部の占める面
積が大きい密領域と凸部の占める面積が小さい粗領域と
が混在する層間絶縁膜の表面をＣＭＰ法により平坦化す
る際、前記層間絶縁膜の表面の粗領域における所望の凸
部の側壁部にのみＣＭＰ法によるポリッシングレートが
前記層間絶縁膜より遅いストッパー膜を前記層間絶縁膜
上に形成する工程と、前記層間絶縁膜の表面をＣＭＰ法
によりポリッシングすると同時に前記ストッパー膜もポ
リッシングする工程とを具備することを特徴とする。A method of manufacturing a semiconductor device according to the present invention is a method for forming a semiconductor device, which is formed on a semiconductor substrate and has a rough and uneven shape on its surface, and in which a convex portion occupies a large area in a local range. When the surface of the interlayer insulating film in which a region and a rough region in which the convex portion occupies a small area are mixed is flattened by the CMP method, the CMP method is applied only to the side wall of the desired convex portion in the rough region of the surface of the interlayer insulating film. Forming a stopper film having a polishing rate slower than that of the interlayer insulating film on the interlayer insulating film, and polishing the surface of the interlayer insulating film by a CMP method and at the same time polishing the stopper film. Characterize.
【００１２】また、本発明の半導体装置の製造方法は、
シリコン基板上に形成され、その表面に粗密な凹凸形状
を有し、局所的な範囲において凸部の占める面積が大き
い密領域と凸部の占める面積が小さい粗領域とが混在す
る層間絶縁膜の表面をＣＭＰ法により平坦化する際、前
記層間絶縁膜の表面の粗領域における所望の凸部の側壁
部にのみＣＭＰ法によるポリッシングレートが無限大の
ストッパー膜を前記層間絶縁膜上に形成する工程と、前
記層間絶縁膜の表面をＣＭＰ法によりポリッシングする
工程と、前記ストッパー膜を除去した後、残存している
前記層間絶縁膜の表面をＣＭＰ法によりポリッシングす
る工程とを具備することを特徴とする。Further, a method of manufacturing a semiconductor device according to the present invention
An interlayer insulating film formed on a silicon substrate, having a rough and uneven shape on its surface, in which a dense region in which a convex portion occupies a large area in a local range and a rough region in which a convex portion occupies a small area coexist A step of forming a stopper film having an infinite polishing rate by the CMP method on the interlayer insulating film only on the side wall portion of a desired convex portion in a rough region of the surface of the interlayer insulating film when the surface is planarized by the CMP method. And a step of polishing the surface of the interlayer insulating film by the CMP method, and a step of removing the stopper film and polishing the remaining surface of the interlayer insulating film by the CMP method. To do.
【００１３】[0013]
【発明の実施の形態】以下、図面を参照して本発明の実
施の形態を詳細に説明する。図１（ａ）乃至（ｃ）は、
本発明の半導体装置の製造方法の第１の実施の形態に係
るシリコン基板上の層間絶縁膜表面に対するＣＭＰ法に
よる平坦化工程を示している。BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. 1 (a) to 1 (c),
1 shows a planarization step by a CMP method for a surface of an interlayer insulating film on a silicon substrate according to a first embodiment of a method for manufacturing a semiconductor device of the present invention.
【００１４】本例では、図１（ａ）に示すような半導体
基板（例えばシリコン基板）１０上に形成された埋め込
み素子分離（ＳＴＩ）領域のように、表面に粗密な凹凸
形状を有し、局所的な範囲において凸部の占める面積が
大きい密な領域（密領域）と凸部の占める面積が小さい
粗な領域（粗領域）とが混在する第１の層間絶縁膜１３
の表面をＣＭＰ法により平坦化する場合について説明す
る。In this example, the surface has a rough uneven shape like a buried element isolation (STI) region formed on a semiconductor substrate (for example, a silicon substrate) 10 as shown in FIG. The first interlayer insulating film 13 in which a dense region (a dense region) in which a convex portion occupies a large area and a rough region (a coarse region) in which a convex portion occupies a small area coexist in a local range.
A case will be described in which the surface of is planarized by the CMP method.
【００１５】なお、上記埋め込み素子分離領域を形成す
る際には、シリコン基板１０上にシリコン酸化膜１１と
ポリシュストッパー用の第１の多結晶シリコン膜１２と
を順次形成し、フォトレジスト（図示せず）を塗布して
パターニングし、このレジストパターンをマスクとして
ＲＩＥ法により前記第１の多結晶シリコン膜１２とシリ
コン酸化膜１１とシリコン基板１０とを順次エッチング
加工する。この場合、基板１０上の例えばメモリセル形
成領域１０ａには凹凸形状のパターンが規則的に密に並
び、上記メモリセル形成領域から少し離れた配線領域１
０ｂには凸形状の孤立配線パターンが存在するように形
成する。When forming the buried element isolation region, a silicon oxide film 11 and a first polycrystalline silicon film 12 for a polish stopper are sequentially formed on a silicon substrate 10 and a photoresist (not shown) is formed. No.) is applied and patterned, and the first polycrystalline silicon film 12, the silicon oxide film 11, and the silicon substrate 10 are sequentially etched by the RIE method using this resist pattern as a mask. In this case, for example, in the memory cell formation region 10a on the substrate 10, the uneven patterns are regularly arranged densely, and the wiring region 1 slightly apart from the memory cell formation region is formed.
0b is formed so that a convex isolated wiring pattern exists.
【００１６】次に、前記レジストパターンを除去し、Ｌ
ＰＣＶＤ（減圧気相成長）法により基板上全面に第１の
層間絶縁膜１３となるＴＥＯＳ（Traethylorthosilicat
e 、ＳｉＯ4 Ｃ8 Ｈ2 Ｏ）膜を隙間なく堆積させる。Next, the resist pattern is removed and L
TEOS (Traethylorthosilicat) which becomes the first interlayer insulating film 13 is formed on the entire surface of the substrate by PCVD (Low Pressure Vapor Deposition) method.
e, SiO 4 C 8 H 2 O) film is deposited without gaps.
【００１７】なお、前記第１の多結晶シリコン膜１２は
後工程で行うＣＭＰに対するストッパー材となるが、こ
の第１の多結晶シリコン膜１２に限らず、ＣＭＰに際し
て前記第１の層間絶縁膜１３に対して同程度の選択比を
有する窒化シリコン膜も使用することができる。Although the first polycrystalline silicon film 12 serves as a stopper material for CMP performed in a later step, the first polycrystalline silicon film 12 is not limited to the first polycrystalline silicon film 12, and the first interlayer insulating film 13 is used for CMP. It is also possible to use a silicon nitride film having a similar selection ratio to.
【００１８】前記第１の層間絶縁膜１３の表面に対する
ＣＭＰに際しては、予め、図１（ｂ）に示すように、前
記第１の層間絶縁膜１３の表面の粗領域において基板の
表面方向に対して例えば６０度以上の角度をなす段差を
有する凸部の側壁部にのみ、ＣＭＰ法によるポリッシン
グレートが第１の層間絶縁膜１３より遅いストッパー膜
１４を形成する。Before CMP is performed on the surface of the first interlayer insulating film 13, as shown in FIG. 1B, a rough region of the surface of the first interlayer insulating film 13 is formed in advance in the surface direction of the substrate. As a result, the stopper film 14 having a polishing rate by the CMP method that is slower than that of the first interlayer insulating film 13 is formed only on the side wall portion of the protrusion having a step forming an angle of, for example, 60 degrees or more.
【００１９】このストッパー膜１４を形成するには、ま
ず、ＣＭＰ法によるポリッシングレートが第１の層間絶
縁膜１３より遅い第２の層間絶縁膜（例えば第２の多結
晶シリコン膜）を第１の層間絶縁膜１３上に形成する。
次に、所望の凸部の側壁部上にのみ第２の層間絶縁膜を
残すようにエッチングする。この際、例えば次の
（１）、（２）に述べるような方法がある。In order to form this stopper film 14, first, a second interlayer insulating film (for example, a second polycrystalline silicon film) whose polishing rate by the CMP method is slower than that of the first interlayer insulating film 13 is first formed. It is formed on the interlayer insulating film 13.
Next, etching is performed so that the second interlayer insulating film remains only on the side wall of the desired convex portion. At this time, for example, there are methods described in (1) and (2) below.
【００２０】（１）全ての凸部の側壁部にのみ第２の層
間絶縁膜を残すようにＲＩＥ法により第２の層間絶縁膜
をエッチングする。次に、基板上にフォトレジストを塗
布し、ストッパー膜１４を形成したい所望の凸部の側壁
部上（メモリセル形成領域１０ａのエッジ部上および孤
立配線パターンのエッジ部上）にのみレジストを残すよ
うにパターンを形成し、このレジストパターンをエッチ
ングマスクとしてＲＩＥ法あるいはＣＤＥ法により第２
の層間絶縁膜を選択的に除去した後にレジストパターン
を除去する。(1) The second interlayer insulating film is etched by the RIE method so that the second interlayer insulating film is left only on the sidewalls of all the convex portions. Next, a photoresist is applied on the substrate, and the resist is left only on the side wall portions of the desired convex portions where the stopper film 14 is to be formed (on the edge portions of the memory cell formation region 10a and the edge portions of the isolated wiring pattern). Pattern is formed as described above, and the resist pattern is used as an etching mask to form a second layer by RIE or CDE.
The resist pattern is removed after selectively removing the interlayer insulating film.
【００２１】（２）基板上にフォトレジストを塗布し、
メモリセル形成領域１０ａのエッジ部上および孤立配線
パターン上にのみレジストを残すようにパターンを形成
し、このレジストパターンをエッチングマスクとしてＲ
ＩＥ法あるいはＣＤＥ法により第２の層間絶縁膜を選択
的に除去する。次に、前記レジストパターンを除去した
後、ストッパー膜１４を形成したい所望の凸部の側壁部
上（メモリセル形成領域１０ａのエッジ部上および孤立
配線パターンのエッジ部上）にのみ第２の層間絶縁膜を
残すようにＲＩＥ法により第２の層間絶縁膜を選択的に
除去する。(2) A photoresist is coated on the substrate,
A pattern is formed such that the resist is left only on the edge portion of the memory cell formation region 10a and on the isolated wiring pattern, and the resist pattern is used as an etching mask to form an R pattern.
The second interlayer insulating film is selectively removed by the IE method or the CDE method. Next, after removing the resist pattern, the second interlayer is formed only on the side wall of the desired convex portion where the stopper film 14 is to be formed (on the edge of the memory cell formation region 10a and on the edge of the isolated wiring pattern). The second interlayer insulating film is selectively removed by RIE so that the insulating film remains.
【００２２】上記したようにストッパー膜１４を形成し
た後、第１の層間絶縁膜１３の表面をＣＭＰ法によりポ
リッシングすると同時にストッパー膜１４もポリッシン
グする。この際、ポリッシングレート比は、第１の層間
絶縁膜１３：ストッパー膜１４＝５：１であるので、ス
トッパー膜１４が存在しない従来例に比べて孤立配線パ
ターンのポリッシングレートが遅くなり、第１の層間絶
縁膜１３の表面の粗領域のポリッシングレートと密領域
のポリッシングレートとがほぼ等しくなる。After forming the stopper film 14 as described above, the surface of the first interlayer insulating film 13 is polished by the CMP method, and at the same time, the stopper film 14 is also polished. At this time, since the polishing rate ratio is the first interlayer insulating film 13: stopper film 14 = 5: 1, the polishing rate of the isolated wiring pattern becomes slower than that of the conventional example in which the stopper film 14 does not exist, and The polishing rate of the rough region and the polishing rate of the dense region on the surface of the interlayer insulating film 13 are substantially equal to each other.
【００２３】これにより、図１（ｃ）に示すように、均
一なポリッシングが可能になり、ＣＭＰ法による平坦化
の対象となる基板表面上の層間絶縁膜１３のパターンに
依存せずに平坦化することが可能になる。As a result, as shown in FIG. 1C, uniform polishing is possible, and the planarization is performed without depending on the pattern of the interlayer insulating film 13 on the surface of the substrate which is the object of planarization by the CMP method. It becomes possible to do.
【００２４】上記したようなＣＭＰ法による平坦化工程
によれば、まず、層間絶縁膜１３の表面の粗領域におけ
る所望の凸部の側壁部にのみ、ＣＭＰ法によるポリッシ
ングレートが層間絶縁膜１３より遅いストッパー膜１４
を形成し、この後にＣＭＰ法によるポリッシングを行
う。According to the flattening step by the CMP method as described above, first, the polishing rate by the CMP method is higher than that by the interlayer insulating film 13 only on the side wall portion of the desired convex portion in the rough region of the surface of the interlayer insulating film 13. Slow stopper film 14
Are formed, and thereafter, polishing is performed by the CMP method.
【００２５】この際、層間絶縁膜１３の表面の粗領域の
ポリッシングレートと密領域のポリッシングレートとが
ほぼ等しくなるので、図１（ｃ）に示したように均一な
ポリッシングが可能になる。つまり、ＣＭＰ法による平
坦化の対象となる基板表面上の層間絶縁膜１３のパター
ンに依存せずに平坦化することが可能になる。At this time, since the polishing rate of the rough area and the polishing rate of the dense area on the surface of the interlayer insulating film 13 are substantially equal to each other, uniform polishing can be performed as shown in FIG. 1C. That is, the planarization can be performed without depending on the pattern of the interlayer insulating film 13 on the surface of the substrate which is the target of the planarization by the CMP method.
【００２６】なお、前記ストッパー膜１４は、多結晶シ
リコン膜に限らず、ＣＭＰ法におけるポリッシングレー
トが前記多結晶シリコン膜とほぼ同じ窒化シリコン膜を
使用しても、図１（ｃ）に示したように均一なポリッシ
ングが可能になる。The stopper film 14 is not limited to the polycrystalline silicon film, and a silicon nitride film having a polishing rate in the CMP method which is almost the same as that of the polycrystalline silicon film is used as shown in FIG. 1C. As a result, uniform polishing becomes possible.
【００２７】図２（ａ）および（ｂ）は、本発明の第２
の実施の形態に係るシリコン基板上の層間絶縁膜表面に
対するＣＭＰ法による平坦化工程を示している。この第
２の実施の形態は、前記した第１の実施の形態と比べ
て、ストッパー膜２４としてＣＭＰ法におけるポリッシ
ングレートが無限大のＣ（カーボン）膜を用いた点が異
なる。2 (a) and 2 (b) show a second embodiment of the present invention.
7 shows a planarization step for the surface of the interlayer insulating film on the silicon substrate according to the embodiment by the CMP method. The second embodiment is different from the above-described first embodiment in that a C (carbon) film having an infinite polishing rate in the CMP method is used as the stopper film 24.
【００２８】即ち、第１の層間絶縁膜１３の表面に対す
るＣＭＰに際しては、予め、図２（ａ）に示すように、
第１の層間絶縁膜１３の表面の粗領域において基板の表
面方向に対して例えば６０度以上の角度をなす段差を有
する凸部の側壁部にのみストッパー膜としてカーボン膜
２４を形成する。このストッパー膜２４を形成するに
は、カーボン膜を前記第１の層間絶縁膜１３上に形成し
た後に、所望の凸部の側壁部上（メモリセル形成領域１
０ａのエッジ部上および孤立配線パターンのエッジ部
上）にのみカーボン膜２４を残すようにエッチングす
る。That is, when CMP is performed on the surface of the first interlayer insulating film 13, as shown in FIG.
The carbon film 24 is formed as a stopper film only on the side wall portion of the convex portion having a step forming an angle of, for example, 60 degrees or more with respect to the surface direction of the substrate in the rough region of the surface of the first interlayer insulating film 13. In order to form the stopper film 24, a carbon film is formed on the first interlayer insulating film 13 and then on the side wall portion of a desired convex portion (memory cell forming region 1
Etching is performed so that the carbon film 24 is left only on the edge portion of 0a and the edge portion of the isolated wiring pattern.
【００２９】上記したようにカーボン膜２４を形成した
後、第１の層間絶縁膜１３の表面をＣＭＰ法によりポリ
ッシングする。この時、カーボン膜２４は殆んど削られ
ないので、第１の層間絶縁膜１３に対して選択比が殆ん
ど無限大のストッパー膜として作用するので、ＣＭＰ後
の状態は、図２（ａ）に示すように、メモリセル形成領
域１０ａのエッジ部上および孤立配線パターン部上の第
１の層間絶縁膜１３が凸状に残る。After forming the carbon film 24 as described above, the surface of the first interlayer insulating film 13 is polished by the CMP method. At this time, since the carbon film 24 is hardly etched, it acts as a stopper film having an almost infinite selection ratio with respect to the first interlayer insulating film 13. Therefore, the state after CMP is as shown in FIG. As shown in a), the first interlayer insulating film 13 remains on the edge portion of the memory cell formation region 10a and on the isolated wiring pattern portion in a convex shape.
【００３０】次に、アッシング法によりカーボン膜２４
を除去した後、凸状に残存している第１の層間絶縁膜１
３の表面を再びＣＭＰ法によりポリッシングすると、メ
モリセル形成領域１０ａのエッジ部上および孤立配線パ
ターン部上の残存している第１の層間絶縁膜１３が他の
部分に対して選択的に削られる。Next, the carbon film 24 is formed by the ashing method.
Of the first interlayer insulating film 1 remaining in a convex shape after removing the
When the surface of No. 3 is again polished by the CMP method, the remaining first interlayer insulating film 13 on the edge portion of the memory cell formation region 10a and the isolated wiring pattern portion is selectively shaved with respect to other portions. .
【００３１】これにより、図２（ｂ）に示すように、均
一なポリッシングが可能になり、ＣＭＰ法による平坦化
の対象となる基板表面上の層間絶縁膜のパターンに依存
せずに平坦化することが可能になる。As a result, as shown in FIG. 2B, uniform polishing is possible, and the planarization is performed without depending on the pattern of the interlayer insulating film on the surface of the substrate to be planarized by the CMP method. It will be possible.
【００３２】なお、上記各実施の形態では、埋め込み素
子分離領域上の層間絶縁膜を平坦化する例を示したが、
本発明はそれに限らず、多層配線上の層間絶縁膜を平坦
化する場合にも適用可能である。In each of the above-mentioned embodiments, an example in which the interlayer insulating film on the buried element isolation region is flattened has been described.
The present invention is not limited to this, and can be applied to the case of planarizing the interlayer insulating film on the multilayer wiring.
【００３３】[0033]
【発明の効果】上述したように本発明によれば、ＣＭＰ
法による平坦化の対象となる基板表面上の層間絶縁膜の
パターンに依存せずに平坦化し得る半導体装置の製造方
法を実現することができる。As described above, according to the present invention, CMP
It is possible to realize a method of manufacturing a semiconductor device that can be planarized without depending on the pattern of the interlayer insulating film on the surface of the substrate that is the object of planarization by the method.
【図１】本発明の半導体装置の製造方法の第１の実施の
形態に係るシリコン基板上の層間絶縁膜表面に対するＣ
ＭＰ法による平坦化工程における基板構造を示す断面
図。FIG. 1 is a diagram showing a C for an interlayer insulating film surface on a silicon substrate according to a first embodiment of a method for manufacturing a semiconductor device of the present invention.
Sectional drawing which shows the board | substrate structure in the planarization process by MP method.
【図２】本発明の第２の実施の形態に係るシリコン基板
上の層間絶縁膜表面に対するＣＭＰ法による平坦化工程
における基板構造を示す断面図。FIG. 2 is a cross-sectional view showing a substrate structure in a planarizing step by a CMP method for a surface of an interlayer insulating film on a silicon substrate according to a second embodiment of the present invention.
【図３】従来のＣＭＰ法による半導体基板上の層間絶縁
膜表面に対するＣＭＰ法による平坦化工程における基板
構造を示す断面図。FIG. 3 is a cross-sectional view showing a substrate structure in a planarizing process by a CMP method for a surface of an interlayer insulating film on a semiconductor substrate by a conventional CMP method.
１０…シリコン基板、 １０ａ…メモリセル形成領域、 １０ｂ…配線領域、 １３…第１の層間絶縁膜、 １４、２４…ストッパー膜。 10 ... Silicon substrate, 10a ... Memory cell forming region, 10b ... Wiring region, 13 ... First interlayer insulating film, 14, 24 ... Stopper film.
Claims (7)
密な凹凸形状を有し、局所的な範囲において凸部の占め
る面積が大きい密領域と凸部の占める面積が小さい粗領
域とが混在する層間絶縁膜の表面をＣＭＰ法により平坦
化する際、前記層間絶縁膜の表面の粗領域における所望
の凸部の側壁部にのみＣＭＰ法によるポリッシングレー
トが前記層間絶縁膜より遅いストッパー膜を形成する工
程と、 前記層間絶縁膜の表面をＣＭＰ法によりポリッシングす
ると同時に前記ストッパー膜もポリッシングする工程と
を具備することを特徴とする半導体装置の製造方法。1. A dense region, which is formed on a semiconductor substrate and has a rough and uneven shape on its surface, and in which a convex region occupies a large area and a convex region occupies a small area are mixed in a local range. When the surface of the interlayer insulating film is flattened by the CMP method, a stopper film having a polishing rate slower than that of the interlayer insulating film by the CMP method is formed only on the side wall portion of a desired convex portion in the rough region of the surface of the interlayer insulating film. And a step of polishing the surface of the interlayer insulating film by a CMP method and polishing the stopper film at the same time.
り遅い絶縁膜を前記層間絶縁膜上に形成する工程と、 全ての前記凸部の側壁部にのみ前記絶縁膜を残すように
ＲＩＥ法により前記絶縁膜をエッチングする工程と、 前記半導体基板上にフォトレジストを塗布し、前記スト
ッパー膜を形成したい所望の凸部の側壁部上にのみレジ
ストを残すようにパターンを形成し、このレジストパタ
ーンをエッチングマスクとしてＲＩＥ法あるいはＣＤＥ
法により前記絶縁膜を選択的に除去する工程とを具備す
ることを特徴とする請求項１記載の半導体装置の製造方
法。2. The step of forming the stopper film includes the step of forming an insulating film on the interlayer insulating film, the polishing rate of which is slower than that of the interlayer insulating film by CMP, and only on the sidewalls of all the convex portions. Etching the insulating film by RIE so as to leave the insulating film, and applying a photoresist on the semiconductor substrate to leave the resist only on the side wall of the desired convex portion where the stopper film is desired to be formed. A pattern is formed on the RIE method, and the resist pattern is used as an etching mask for RIE or CDE.
The method of manufacturing a semiconductor device according to claim 1, further comprising the step of selectively removing the insulating film by a method.
り遅い絶縁膜を前記層間絶縁膜上に形成する工程と、 前記半導体基板上にフォトレジストを塗布し、前記密領
域のエッジ部上および前記粗領域の凸部上にのみレジス
トを残すようにパターンを形成し、このレジストパター
ンをエッチングマスクとしてＲＩＥ法あるいはＣＤＥ法
により前記絶縁膜を選択的に除去する工程と、 前記レジストパターンを除去した後、ストッパー膜を形
成したい所望の凸部の側壁部上にのみ前記絶縁膜を残す
ようにＲＩＥ法により絶縁膜を選択的に除去する工程と
を具備することを特徴とする請求項１記載の半導体装置
の製造方法。3. The step of forming the stopper film comprises the steps of forming an insulating film on the interlayer insulating film, the insulating film having a polishing rate slower than that of the interlayer insulating film by CMP, and applying a photoresist on the semiconductor substrate. A pattern is formed so that the resist is left only on the edges of the dense region and on the protrusions of the rough region, and the insulating film is selectively removed by RIE or CDE using this resist pattern as an etching mask. And a step of selectively removing the insulating film by the RIE method after removing the resist pattern so that the insulating film is left only on the side wall of a desired convex portion where a stopper film is desired to be formed. The method for manufacturing a semiconductor device according to claim 1, wherein
記ストッパー膜は多結晶シリコン膜であることを特徴と
する請求項１記載の半導体装置の製造方法。4. The method of manufacturing a semiconductor device according to claim 1, wherein the interlayer insulating film is a TEOS film, and the stopper film is a polycrystalline silicon film.
記ストッパー膜は窒化シリコン膜であることを特徴とす
る請求項１記載の半導体装置の製造方法。5. The method of manufacturing a semiconductor device according to claim 1, wherein the interlayer insulating film is a TEOS film, and the stopper film is a silicon nitride film.
粗密な凹凸形状を有し、局所的な範囲において凸部の占
める面積が大きい密領域と凸部の占める面積が小さい粗
領域とが混在する層間絶縁膜の表面をＣＭＰ法により平
坦化する際、前記層間絶縁膜の表面の粗領域における所
望の凸部の側壁部にのみＣＭＰ法によるポリッシングレ
ートが無限大のストッパー膜を前記層間絶縁膜上に形成
する工程と、 前記層間絶縁膜の表面をＣＭＰ法によりポリッシングす
る工程と、 前記ストッパー膜を除去した後、残存している前記層間
絶縁膜の表面をＣＭＰ法によりポリッシングする工程と
を具備することを特徴とする請求項１記載の半導体装置
の製造方法。6. A dense region, which is formed on a silicon substrate and has a rough and uneven shape on its surface, and in which a convex region occupies a large area and a convex region occupies a small area are mixed in a local range. When the surface of the interlayer insulating film is flattened by the CMP method, a stopper film having an infinite polishing rate by the CMP method is formed only on the side wall portion of the desired convex portion in the rough area of the surface of the interlayer insulating film. A step of forming the upper surface, a step of polishing the surface of the interlayer insulating film by a CMP method, and a step of removing the stopper film and polishing the remaining surface of the interlayer insulating film by a CMP method. The method for manufacturing a semiconductor device according to claim 1, wherein
前記ストッパー膜を除去する際にアッシング法を用いる
ことを特徴とする請求項６記載の半導体装置の製造方
法。7. The stopper film is a carbon film,
7. The method of manufacturing a semiconductor device according to claim 6, wherein an ashing method is used when removing the stopper film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5471896A JPH09246219A (en) | 1996-03-12 | 1996-03-12 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5471896A JPH09246219A (en) | 1996-03-12 | 1996-03-12 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09246219A true JPH09246219A (en) | 1997-09-19 |
Family
ID=12978592
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5471896A Pending JPH09246219A (en) | 1996-03-12 | 1996-03-12 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09246219A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100444627B1 (en) * | 2001-02-22 | 2004-08-21 | 샤프 가부시키가이샤 | Process of manufacturing semiconductor device |
| US7316786B2 (en) | 2004-12-10 | 2008-01-08 | Tdk Corporation | Method of polishing film to be polished |
| US7682923B2 (en) | 2007-12-31 | 2010-03-23 | Tdk Corporation | Method of forming metal trench pattern in thin-film device |
-
1996
- 1996-03-12 JP JP5471896A patent/JPH09246219A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100444627B1 (en) * | 2001-02-22 | 2004-08-21 | 샤프 가부시키가이샤 | Process of manufacturing semiconductor device |
| US7316786B2 (en) | 2004-12-10 | 2008-01-08 | Tdk Corporation | Method of polishing film to be polished |
| US7682923B2 (en) | 2007-12-31 | 2010-03-23 | Tdk Corporation | Method of forming metal trench pattern in thin-film device |
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