JPH1166868A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of shortening a boost operating time for a memory cell wherein a threshold voltage is lowered at the time of a power-on resetting operation. SOLUTION: The threshold voltage of the memory cell of a memory cell array assigned by one unit of address stored in an address storage part 21 at the time of power-on resetting is detected with a sense amplifier 25. Whether the threshold voltage is the voltage wherein data volatilization is generated is judged with a judging circuit 25. In the case of the voltage wherein volatilization is generated, the threshold voltage is boosted into the voltage wherein data volatilization is not generated with a voltage generating circuit 28. In the case of the voltage wherein volatilization is not generated, 1 is added to respective addresses of the address storage part 21 with an address adding circuit 27.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used for a system that frequently performs a power-on reset operation, and is used for raising a threshold voltage of a memory cell (memory transistor) of a nonvolatile memory such as a flash memory in which data is volatilized. And a semiconductor integrated circuit that is suitable.

[0002]

2. Description of the Related Art FIG. 8 is a distribution diagram of a threshold voltage of a conventional semiconductor integrated circuit. In FIG. 8, the vertical axis represents the number of bits of the nonvolatile memory, and the horizontal axis represents the threshold voltage of each memory cell of the nonvolatile memory. In FIG. 8, Vcc is a power supply voltage of the nonvolatile memory, a threshold voltage satisfying a condition that data of each memory cell in the nonvolatile memory is not volatilized, 10 is a read voltage range of data of the memory cell, and 11 is an individual memory. Distribution of data “0” indicating a state where the threshold voltage of the memory cell is increased due to the presence of many electrons in the floating gate of the cell;
Reference numeral 12 denotes a distribution of data "1" indicating that the threshold value of the memory cell is lowered due to the presence of only a small number of electrons in the floating gate.

Next, the operation will be described. As described above, although the threshold voltage of each memory cell of the nonvolatile memory has a certain distribution, some of the memory cells in the state of data “0” may have a threshold voltage due to a process defect or the like. In some cases, the threshold voltage is lower than the voltage without data volatilization. For example, as indicated by reference numeral 13 in FIG. 9, there is a data obtained by subtracting the voltage ΔV corresponding to the voltage drop from the power supply voltage Vcc, or the data may be volatile or possibly.

Conventionally, at power-on reset, memory addresses are automatically accessed sequentially for all memory areas of a non-volatile memory, and a threshold voltage is applied to a memory cell having a threshold voltage of Vcc-.DELTA.V. Has been performing an internal operation to increase the voltage to Vcc or more.

As another conventional example of such an internal operation, there is a semiconductor memory device described in, for example, Japanese Patent Application Laid-Open No. 8-138395. This is selectively activated when the write counter overflows, and selectively performs write-back on a cell whose threshold voltage has been lowered by writing another memory cell coupled to the same data line in the nonvolatile memory. It has become. However, the measurement of the threshold voltage of the memory cell at the time of the power-on reset operation is performed for the entire memory area.

[0006]

Since the conventional semiconductor integrated circuit is configured as described above, every time the power-on reset operation is performed, the threshold voltage is measured for all the memory areas, and the threshold voltage is measured. Since the boosting is performed on the memory cell having the lowered threshold voltage, there is a problem that it takes time to perform the boosting operation.

Further, since the boosting operation takes a long time as described above, there has been a problem that the time required for the system using the memory to operate after reset release becomes long.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and can reduce a boosting operation time for a memory cell having a reduced threshold voltage during a power-on reset operation. It is an object of the present invention to obtain a semiconductor integrated circuit capable of shortening the time until the system operates later.

[0009]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit, wherein an address having one unit for each word line or a plurality of word lines of a memory cell array is set for each power-on reset operation. Address storage means for outputting the threshold voltage of a memory cell designated by one unit address, and determination means for determining whether or not the detected threshold voltage is a voltage at which data volatilization occurs. And, when it is determined that the voltage is such that data volatilization occurs, a voltage generating unit that boosts the threshold voltage to a voltage that does not cause data volatilization, and when it is determined that the voltage does not cause data volatilization, Address adding means for adding 1 to each address stored in the address storage means.

In the semiconductor integrated circuit according to the second aspect of the present invention, when it is determined that the voltage does not cause data volatilization, the address adding means instructs the address adding means to output the address to which 1 has been added to the memory cell array. A function of outputting the address obtained by the addition to the memory cell array when the instruction is issued to the address storage means, and a memory for storing the address when the voltage is determined to cause data volatilization. And a function of not outputting an address to the cell array.

A semiconductor integrated circuit according to a third aspect of the present invention includes a counter for performing a counting operation when it is determined that the voltage does not cause data volatilization, and the count value of the counter is input to the address adding means. Every time the address is stored in the address storage means, a function of adding 1 to each address stored in the address storage means and instructing to output the address obtained by the addition to the memory cell array is provided. It has a function of not outputting an address to the memory cell array when the value is 0.

According to a fourth aspect of the present invention, in the semiconductor integrated circuit, a nonvolatile memory is used for the address storage means.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a block diagram of a semiconductor integrated circuit according to Embodiment 1 of the present invention.
Numeral 1 divides the memory address (address) of the memory cell array 24 for each word line or for each block (a plurality of word lines) and stores this as one unit. When the power-on reset signal PR is input, the stored 1 is stored. An address storage unit (address storage means) of a non-volatile memory such as a flash memory for outputting a memory address of a unit to the address latch 22; an address latch 22 for holding a memory address from the address storage unit 21 and outputting it to an address decoder 23; Reference numeral 23 denotes an address decoder which decodes a memory address from the address latch 22 and outputs it to the memory cell array 24. Reference numeral 24 denotes word lines and data lines which are arranged orthogonally, and which are arranged in a grid at intersections of these word lines and data lines. Including a two-layer gate type memory cell Memory is a memory cell array of the rewritable non like.

Reference numeral 25 denotes a sense amplifier (detection means) for detecting the threshold voltage of each memory cell for one unit of the memory cell array 24 specified by the memory address output from the address decoder 23. Reference numeral 26 denotes a sense amplifier 25. It is determined whether or not the detected threshold voltage has dropped to the voltage Vcc-ΔV at which data is volatilized as described in the conventional example, and if it is determined that the threshold voltage has not dropped to Vcc-ΔV,
Determination result G1 indicating that Vcc-ΔV has not been reduced
Is output to the address adding circuit (address adding means) 27, and when it is determined that the voltage has dropped to Vcc-ΔV, V
A determination circuit (determination unit) that outputs a determination result G2 indicating that the voltage has decreased to cc−ΔV to the voltage generation circuit (voltage generation unit) 28.

Numeral 27 adds "1" to each memory address held in the address latch 22 when the judgment result G1 indicating that the voltage has not dropped to Vcc-.DELTA.V is input from the judgment circuit 26. An address adder circuit for storing the memory address obtained by the addition in the address storage unit 21 as an access destination at the time of the next power-on reset. The determination circuit 28 determines from the determination circuit 26 that the voltage has dropped to Vcc-ΔV. When the result G2 is input,
A voltage generation circuit 28 such as a booster circuit that performs an internal operation so that the threshold voltage of the memory cell that has dropped to Vcc-ΔV becomes equal to or higher than Vcc.

However, as shown in FIG. 2, the sense amplifier 25 includes a threshold voltage detection circuit 35 and a plurality of buffers 3.
6,37. The threshold voltage detection circuit 35
For example, when the voltage V1 of the memory cell 24a of the memory cell array 24 is equal to or higher than the power supply voltage Vcc, the output voltage V2
Becomes "L" level, and when voltage V1 is smaller than Vcc, it becomes "H" level, and each level is output to determination circuit 26. Also, a plurality of buffers 36 and 37
The voltage V3 supplied to the determination circuit 26 via the switch becomes “H” only when V1 is Vcc−ΔV. From this, the determination circuit 26 determines that when both V2 and V3 are “H”,
It is determined that the threshold voltage has dropped to Vcc-ΔV.

Next, the operation will be described. FIG. 3 is a flowchart showing a flow of processing of the semiconductor integrated circuit according to the first embodiment. First, in step ST1, a power-on reset is performed, and when a power-on reset signal PR is input to the address storage unit 21, in step ST2, one unit of memory address stored in the address storage unit 21 is stored in the address latch 22. After the held memory address is decoded by the address decoder 23, it is loaded into the memory cell array 24.

Next, in step ST3, the sense amplifier 25 detects the threshold voltage of each memory cell of one unit of the memory cell array 24 specified by the memory address, and determines the detected threshold voltage. Output to the determination circuit 26. Next, in step ST4, the determination circuit 26
Is the threshold voltage detected by the sense amplifier 25 and the voltage V
It is determined whether or not cc-ΔV has been reduced.

As a result, when it is determined that the threshold voltage has dropped to Vcc-.DELTA.V, in step ST5, the determination circuit 26 determines that the threshold voltage is Vcc-.DELTA.V.
Is output to the voltage generation circuit 28, and the voltage generation circuit 28
The threshold voltage of the memory cell which has dropped to c-ΔV is V
The internal operation to make the value of cc or more is started.

In step ST6, if the threshold voltage is equal to or higher than Vcc, the process proceeds to step ST7. If not, the internal operation in step ST5 is continued. Further, as a result of step ST4, the threshold voltage becomes Vc
The process also proceeds to step ST7 when it has not decreased to c-ΔV.

That is, when the determination circuit 26 determines that the threshold voltage is equal to or higher than Vcc, the determination result G1 indicating that the threshold voltage has not decreased to Vcc-ΔV is obtained from the determination circuit 26. It is output to the address adding circuit 27.

Then, in step ST7, the address addition circuit 27 adds "1" to each memory address held in the address latch 22, and in step ST8, the memory address obtained by the addition is used for the next power-on reset. It is stored in the address storage unit 21 as an access destination at the time. Then, in step ST9, an internal operation, which is a read operation of the memory cell array 24, is started. After this operation is completed, in step ST10, power down for turning off the power is performed.

As described above, according to the first embodiment, every time the power-on reset operation is performed, the memory address of the memory cell array 24 is divided for each word line or block (a plurality of word lines). The threshold voltage of a memory cell specified by a memory address with 1 as a unit is detected, and if the detected threshold voltage is a voltage of Vcc-ΔV at which data volatilization occurs, a voltage at which no data volatilization occurs Since the boost operation of Vcc or more is performed,
The effect that the boosting operation time can be greatly reduced compared to the conventional case where the boosting operation is performed for all the memory regions can be obtained.

Further, since the boosting operation time can be greatly reduced, the effect of shortening the time until the system operates after reset release is obtained.

Embodiment 2 FIG. 4 is a block diagram of a semiconductor integrated circuit according to a second embodiment of the present invention. In the figure, reference numeral 21 denotes a memory for storing a memory address in the same manner as described in the first embodiment. When there is a read instruction from the address addition circuit 27a to the address latch 22, the stored memory address is output to the address latch 22, and the determination circuit 26 determines that the voltage has dropped to Vcc-ΔV. An address storage unit 22 for stopping the operation of outputting a memory address to the address latch 22 when the result G2 is input;
Is an address latch, 23 is an address decoder, 24 is a memory cell array, and 25 is a sense amplifier.

26 determines whether or not the threshold voltage detected by the sense amplifier 25 has dropped to a voltage Vcc-.DELTA.V at which data is volatilized. If it is determined that the threshold voltage has not dropped to Vcc-.DELTA.V, A determination result G1 indicating that the voltage has not decreased to Vcc-ΔV is output to the address adding circuit 27a, and when it is determined that the voltage has decreased to Vcc-ΔV, V
This is a determination circuit that outputs a determination result G2 indicating that the voltage has decreased to cc−ΔV to the address storage unit 21 and the voltage generation circuit 28.

27a, when the judgment result G1 indicating that the voltage has not dropped to Vcc-.DELTA.V is input from the judgment circuit 26, "1" is added to each memory address held in the address latch 22. An address adding circuit that stores a memory address obtained by the addition in the address storage unit 21 and then instructs the address latch 22 to read the address;
28 is a voltage generating circuit.

Next, the operation will be described. FIG. 5 is a flowchart showing a flow of processing of the semiconductor integrated circuit according to the second embodiment. First, in step ST1, a power-on reset is performed, and when a power-on reset signal PR is input to the address storage unit 21, in step ST2, one unit of memory address stored in the address storage unit 21 is stored in the address latch 22. After the held memory address is decoded by the address decoder 23, it is loaded into the memory cell array 24.

Next, in step ST3, the sense amplifier 25 detects the threshold voltage of each memory cell of one unit of the memory cell array 24 designated by the memory address, and detects the detected threshold voltage. Output to the determination circuit 26. Next, in step ST4, the determination circuit 26
Is the threshold voltage detected by the sense amplifier 25 and the voltage V
It is determined whether or not cc-ΔV has been reduced.

As a result, if it is determined that the threshold voltage has not dropped to Vcc-ΔV, step ST5
, The determination result G1 indicating that the voltage has not dropped to Vcc-ΔV from the determination circuit 26 is
Is output to the address adding circuit 27a.
“1” is added to each memory address held in the address latch 22, the memory address obtained by the addition is stored in the address storage unit 21, and then an instruction to read out to the address latch 22 is given.

As a result, the memory address to which the previous "1" has been added is read from the address storage unit 21, and in step ST3, the threshold value of the memory cell designated by one unit of memory address different from that described above. The voltage is detected, and in step ST4, it is determined whether or not the threshold voltage has dropped to voltage Vcc- [Delta] V.

On the other hand, when it is determined in step ST4 that the threshold voltage has dropped to Vcc-.DELTA.V, in step ST6, the determination circuit 26 lowers the threshold voltage to Vcc-.DELTA.V. The determination result G2 indicating that the operation is performed in the address storage unit 21 and the voltage generation circuit 28
The operation of outputting the memory address to the address latch 22 in the address storage unit 21 is stopped, and the voltage generation circuit 28 performs an internal operation of setting the threshold voltage of the memory cell lowered to Vcc-ΔV to Vcc or more. Start.

Thus, in step ST7,
If the threshold voltage is equal to or higher than Vcc, the process proceeds to step ST8, and if not, the internal operation in step ST6 is continued.

Then, in step ST8, the address adding circuit 27 adds "1" to each memory address held in the address latch 22, and in step ST9, the memory address obtained by the addition is used for the next power-on reset. It is stored in the address storage unit 21 as an access destination at the time. At this time, as described in step ST6, the operation of outputting the memory address to the address latch 22 in the address storage unit 21 is stopped, so that the address storage unit 2 described in step ST5 is used.
Reading from 1 is not performed.

Finally, in step ST10, an internal operation, which is a read operation of the memory cell array 24, is started. After the operation is completed, in step ST11, power down for turning off the power is performed.

As described above, according to the second embodiment, if there is no memory cell having a threshold voltage of Vcc-.DELTA.V, "1" is automatically added to the memory address, and the memory obtained by this addition is added. Since the threshold voltage of the memory cell at the address is detected and it is determined whether or not Vcc-ΔV is available, many memory cells are accessed with a small number of power-on resets, and the threshold voltage is determined. Is obtained.

Embodiment 3 FIG. 6 is a block diagram of a semiconductor integrated circuit according to a third embodiment of the present invention. In the figure, reference numeral 21 denotes a function in addition to the functions described in the second embodiment.
An address storage unit for stopping the memory address output operation to the address latch 22 when the count value n = 0 of the counter 39 is input, 22 is an address latch, 23 is an address decoder, 24 is a memory cell array, and 25 is a sense amplifier. It is.

26 determines whether or not the threshold voltage detected by the sense amplifier 25 has dropped to a voltage Vcc-.DELTA.V at which data is volatilized. If it is determined that the threshold voltage has not dropped to Vcc-.DELTA.V, The determination result G1 indicating that the voltage has not dropped to Vcc-ΔV is output to the counter 39,
This is a determination circuit that outputs a determination result G2 indicating a reduction to Vcc-ΔV to the address storage unit 21 and the voltage generation circuit 28 when it is determined that the voltage has decreased to ΔV.

39 is set to 1 every time the judgment result G1 is input.
The counter performs a count operation for each count, and outputs a count value n by this operation to the address addition circuit 27b and the address storage unit 21. When the count value n is input, each of the memories 27b held in the address latch 22 Reference numeral 28 denotes a voltage generation circuit which adds "1" to the address, stores the memory address obtained by the addition in the address storage unit 21, and then instructs the address latch 22 to read the address.

Next, the operation will be described. FIG. 7 is a flowchart showing a flow of processing of the semiconductor integrated circuit according to the third embodiment. First, in step ST1, a power-on reset is performed, and when a power-on reset signal PR is input to the address storage unit 21, in step ST2, one unit of memory address stored in the address storage unit 21 is stored in the address latch 22. After the held memory address is decoded by the address decoder 23, it is loaded into the memory cell array 24.

Next, in step ST3, the sense amplifier 25 detects the threshold voltage of each memory cell of one unit of the memory cell array 24 specified by the memory address, and detects the detected threshold voltage. Output to the determination circuit 26. Next, in step ST4, the determination circuit 26
Is the threshold voltage detected by the sense amplifier 25 and the voltage V
It is determined whether or not cc-ΔV has been reduced.

As a result, if it is determined that the threshold voltage has not dropped to Vcc-.DELTA.V, step ST5
, The determination result G1 indicating that the voltage has not dropped to Vcc-ΔV is output from the determination circuit 26 to the counter 39, and the counter 39 counts up by one. As a result,
In step ST6, if the count value n is not 0, in step ST7, the address adding circuit 27
Adds “1” to each memory address held in the address latch 22, stores the memory address obtained by this addition in the address storage unit 21, and then instructs the address latch 22 to read out.

As a result, the memory address to which "1" has been added is read from the address storage unit 21, and in step ST3, the threshold voltage of the memory cell specified by one unit of memory address different from that described above. Is detected, and in step ST4, it is determined whether or not the threshold voltage has dropped to voltage Vcc- [Delta] V.

On the other hand, if the count value n of the counter 39 is 0 in step ST6, the process proceeds to step ST10, where the count value n = 0 is output to the address storage unit 21, and the address latch 22 is stored in the address storage unit 21. Memory address output operation to the
The address adding circuit 27b adds "1" to each memory address held in the address latch 22, and in step ST11, the memory address obtained by the addition is used as an access destination at the time of the next power-on reset. To memorize.

If it is determined in step ST4 that the threshold voltage has dropped to Vcc-.DELTA.V, in step ST8, the determination circuit 26 lowers the threshold voltage to Vcc-.DELTA.V. The determination result G2 indicating that the operation is performed in the address storage unit 21 and the voltage generation circuit 28
The operation of outputting the memory address to the address latch 22 in the address storage unit 21 is stopped, and the voltage generation circuit 28 performs an internal operation of setting the threshold voltage of the memory cell lowered to Vcc-ΔV to Vcc or more. Start.

Thus, in step ST9,
If the threshold voltage is equal to or higher than Vcc, the process proceeds to step ST10, and if not, the internal operation in step ST8 is continued.

Then, in step ST10, as in the case where the count value n = 0 in step ST6, the address addition circuit 27b adds "1" to each memory address held in the address latch 22, and then proceeds to step ST11.
, The memory address obtained by the addition is stored in the address storage unit 21 as an access destination at the time of the next power-on reset. At this time, as described in step ST8, since the operation of outputting the memory address to the address latch 22 in the address storage unit 21 is stopped in the address storage unit 21, the address storage unit 2 described in step ST7 is used.
Reading from 1 is not performed.

Finally, in step ST12, an internal operation, which is a read operation of the memory cell array 24, is started, and after this operation is completed, in step ST13, power down for turning off the power is performed.

As described above, according to the third embodiment, when there is no memory cell having the threshold voltage according to the count value n, "1" is automatically added to the memory address and the threshold voltage is increased. Since the determination operation is restricted, an effect is obtained in which an arbitrary number of memory cells can be accessed to determine whether the threshold voltage has dropped.

[0050]

As described above, according to the present invention, a semiconductor integrated circuit is transferred to the memory cell array at every power-on reset operation by assigning an address for each word line of the memory cell array or a plurality of word lines as one unit. Address storage means for outputting, detection means for detecting a threshold voltage of a memory cell designated by one unit address, and determination means for determining whether or not the detected threshold voltage is a voltage at which data volatilization occurs. A voltage generating means for increasing the threshold voltage to a voltage at which data volatilization does not occur when the voltage is determined to be a voltage at which data volatilization occurs; Since the configuration is provided with the address addition means for adding 1 to each address stored in the storage means, it is larger than the conventional case where the boosting operation is performed for all memory areas. There is an effect that it is possible to shorten the boost operation time.

According to the present invention, the address adding means includes:
If it is determined that the voltage does not cause data volatilization,
A function of instructing the memory cell array to output the address obtained by adding 1 to the memory cell array; a function of outputting the address obtained by the addition to the memory cell array when the instruction is issued; A function of not outputting an address to the memory cell array when it is determined that the voltage causes volatilization, so that many memory cells can be accessed with a small number of power-on resets, There is an effect that a determination of a decrease in threshold voltage can be made.

According to the present invention, the counter is provided which performs a counting operation when it is determined that the voltage does not cause data volatilization. Each time the count value of the counter is inputted to the address adding means, the address storing means is provided. Is added to each address stored in the memory cell array, and an instruction to output the address obtained by the addition to the memory cell array is provided. Is provided with a function of preventing the output of the address from being performed. Therefore, there is an effect that an arbitrary number of memory cells can be accessed to determine whether the threshold voltage has dropped.

According to the present invention, the address storage means includes:
Since the configuration is made using the nonvolatile memory, an address for performing the next power-on reset operation is stored even if power is not supplied to the semiconductor integrated circuit, and the power-on reset operation can be started from the stored address. Therefore, there is an effect that the efficiency of the power-on reset operation can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram of a semiconductor integrated circuit according to a first embodiment of the present invention;

FIG. 2 is a diagram illustrating a configuration of a sense amplifier.

FIG. 3 is a flowchart showing a processing flow of the semiconductor integrated circuit according to the first embodiment of the present invention;

FIG. 4 is a block diagram of a semiconductor integrated circuit according to a second embodiment of the present invention;

FIG. 5 is a flowchart showing a processing flow of the semiconductor integrated circuit according to the second embodiment of the present invention;

FIG. 6 is a block diagram of a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 7 is a flowchart showing a processing flow of a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 8 is a distribution diagram of a threshold voltage of a conventional semiconductor integrated circuit.

FIG. 9 is a distribution diagram showing that a threshold voltage of a conventional semiconductor integrated circuit has been reduced to a voltage Vcc-ΔV at which data volatilization occurs.

[Explanation of symbols]

21 address storage unit (address storage unit), 24 memory cell array, 25 sense amplifier (detection unit), 26
Judgment circuit (judgment means), 27 address addition circuit (address addition means), 28 voltage generation circuit (voltage generation means), 39 counter.

Claims (4)

[Claims] 1. A memory cell array in which memory cells are arranged in a grid at intersections of orthogonally arranged word lines and data lines, and the address of the memory cell array is defined as one unit for each word line or for each of a plurality of word lines. Remember as
Address storage means for outputting the one unit address to the memory cell array each time a power-on reset operation for boosting the threshold voltage of the memory cell to a voltage free of data volatility is performed; Detecting means for detecting the threshold voltage of the memory cell specified by the address; determining means for determining whether the threshold voltage detected by the detecting means is a voltage at which data volatilization occurs; Voltage generating means for, when it is determined that the threshold voltage is a voltage at which data volatilization occurs, raising a threshold voltage of the memory cell specified by the one unit address to a voltage at which no data volatilization occurs; When the determination means determines that the threshold voltage is a voltage at which data volatilization does not occur, 1 is assigned to each address stored in the address storage means.
A semiconductor integrated circuit comprising: 2. The method according to claim 1, wherein the determining means determines that the threshold voltage is a voltage at which data volatilization does not occur.
A function of instructing the memory cell array to output the added address, and a function of outputting the address obtained by the addition to the memory cell array when the instruction is issued to the address storage means; 2. The apparatus according to claim 1, further comprising a function of not outputting an address to said memory cell array when said threshold value is determined to be a voltage at which data volatilization occurs. A semiconductor integrated circuit as described in the above. 3. A counter for performing a count operation when the threshold voltage is determined to be a voltage at which data volatilization does not occur by the determining means, and the address adding means includes a threshold voltage which is determined by the determining means. Instead of the case where it is determined that the voltage does not occur, each time the count value of the counter is input, 1 is added to each address stored in the address storage means, and the address obtained by this addition is stored in the memory. A function of giving an instruction to output to the cell array, wherein the address storage means has a function of not outputting an address to the memory cell array when the count value is 0. The semiconductor integrated circuit according to claim 1. 4. The semiconductor integrated circuit according to claim 1, wherein a nonvolatile memory is used as the address storage means.