JPH1165972A - Data communication equipment and its method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To sort information contents to each slave station without using identifier information by allowing a main station to generate communication data of a data length obtained by putting together data information of the portion of the number of all the slave stations to transfer to each slave station and to generate a synchronous clock signal to transfer to a slave station. SOLUTION: CPU 21 is also used as a main station at serial communication to execute communication with the slave station. A serial communication transmitting line consists of a loop-like transmitting line and serial data information and a synchronizing clock issued from the main station are transferred to the slave stations 27, 33, 39 and 45 in this order and finally returned to the main station. The main station delivers serial data information corresponding to each slave station arranged in a prescribed arranging order with a synchronizing clock. All the slave stations delete read information and transfer remaining data lengths to a slave station positioned next. Even when identifier information showing which slave station data contents correspond does not exist, information contents can be sorted to each slave station.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a central processing unit mounting unit in a mounting unit mounted in an apparatus, wherein a main station for data communication is arranged and another mounting unit mounted in the apparatus is provided. A data communication device that arranges slave stations for data communication, connects the master station and the slave stations with a loop communication medium, and enables information exchange between a plurality of mounting board units mounted in the device; and It is about the method.

[0002]

2. Description of the Related Art Conventionally, a serial communication device for exchanging information among a plurality of electronic component mounting units existing in a device has been provided by a central processing unit (CMP) which controls the operation of the entire device.
The PU is configured as a master station for serial communication, and the other plurality of mounting units are positioned as slave stations for serial communication to exchange information in the apparatus.

In order to reduce the additional cost, the slave station uses an I / O circuit composed of a small-scale circuit using a gate array.
In most cases, it was composed of C.

In other words, in order to minimize costs, serial communication control in the master station is also used by the CPU of the central processing unit, and serial data communication control in the slave station is implemented as a gate array with a simple circuit configuration. I was Furthermore, the gate array for the slave station can be mass-produced by configuring the same circuit as the number of slave stations used in the device, and the number of devices to be mass-produced. This is because it leads to further cost reduction.

[0005] On the other hand, a transmission line configuration for serial data communication may be a loop type transmission ROM in which a master station and a plurality of slave stations are connected one-to-one or a master station and a plurality of slave stations are connected in a loop. May be used. In the former case, the number of wires spreads in a star shape centering on the master station, so transmission / reception wires for the number of slave stations are required, which is somewhat disadvantageous in cost.

In the latter case, one slave station receives data to be transmitted from the master station and transmits the succeeded data to the next slave station. Then, the data taken over from the slave station to the master station returns. In the information exchange, each slave station takes in the information portion secured by the identifier in the inherited data as output data from the master station,
By adding input data generated at the slave station to the same position, information from the master station is transferred to each slave station, and input data of the slave station is transferred to the master station. As described above, the loop-type transmission communication means can be realized with a configuration having a smaller number of wirings and with easier wiring assembly than the star-shaped transmission path, and thus can be realized at a relatively low cost.

[0007]

However, when the slave station gate array in the above conventional example is manufactured, there are the following disadvantages.

To minimize the cost of the gate array, the minimum number of gates, 400 to 5
Create a circuit with 00 gates, make the IC package a dip type, and use 14 pins or 16 pins.
It is composed of pins.

Regarding the former circuit configuration, the number of gates may be of various means, but basically, a gate which can be sufficiently accommodated by using a shift register circuit, an input / output latch circuit, a counter circuit, etc. Can be composed of numbers. However, considering the latter, the number of terminals cannot be constituted by 14 pins or 16 pins when considering the terminals of the gate array. Therefore, the number of terminals is formed by 18 pins or 20 pins or 24 pins. There is a disadvantage that the package cost increases.

[0010] Specifically, the number of required terminals will be described.
The gate array IC has three terminals, a power supply terminal for operation of the IC, a ground terminal (GND terminal), a reset input terminal, a serial input / output terminal of a synchronization clock for serial communication, and a terminal for serial communication. Four terminals of serial input / output terminals for data information, four input / output terminals for parallel input / output terminals from the IC, and a total of 15 terminals are required at a minimum.

On the other hand, as described in the above-described example, as for the data information in the loop transmission path, each slave station takes in the information portion secured by the identifier with respect to the transmitted data length as output data from the master station. It is necessary to add an input terminal for the need. Although this identifier decoding terminal depends on the number of units of the mounting board in the apparatus, 3 to 5 bits are necessary to obtain the advantage of serial communication.
In order to add an identifier decoding input terminal to the total of 15 terminals described above, the number of terminals is changed to 18 pins or 20 pins,
This results in a configuration with four pins. As a result, the number of pins is inevitably increased, and the cost cannot be reduced.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems. For example, by exchanging data that does not require an identifier to read data information from a master station in a slave station, The number of terminals of the gate array IC constituting the slave station for data communication between the units can be reduced to 14 pins or 16 pins or less, and the cost can be reduced even if the control circuit of the slave station is constituted by the gate array IC. Is what makes it possible.

[0013]

In order to achieve the above object, an embodiment of the present invention has, for example, the following corrugated structure.

That is, a main station for data communication is allocated to a central processing unit mounting unit in a mounting unit mounted in the apparatus, and data communication for each other mounting unit mounted in the apparatus is performed. A data communication device, comprising a slave station, wherein the master station and the slave station are connected by a loop communication medium to enable information exchange between a plurality of mounting board units mounted in the device. A data information transfer means for generating communication data of a data length in which data information for all the slave stations for data communication output from the master station are collected and transferring the communication information to each slave station; Synchronous clock transfer means for generating a synchronous clock signal for communication and transferring the signal to the slave station, wherein the communication data indicates corresponding data information to each slave station in the data information to be transferred. Characterized in that it is constituted by the data information content that does not include the identification data information because.

[0015] For example, the communication data is serial data, and the slave station receives communication data transferred from a station located at a higher rank of each station connected in a loop, and sets a head of the received communication data. Transfer data information input means for taking in data information of a predetermined number of bits from bits as transfer data information to the own station; and data information of a predetermined number of bits from the first bit of communication data taken in by the transfer data information input means And the received synchronous clock corresponding to the data information, and deletes the communication data to the slave station located at the new next stage and the transfer data information to be transferred to the slave station located at the new next stage as a synchronous clock signal. Means.

For example, the slave station detects the timing corresponding to the last bit position of the communication data with respect to the communication data transferred from the station located above each station connected in a loop, and And a transfer data information adding means for adding a data information output generated by the local station having a predetermined number of bits after the last bit of.

Further, for example, the master station sequentially returns, as a return data information from each slave station, communication data transferred from a slave station located at the lowermost position of each station connected in a loop in a predetermined bit number unit. It has a reading means.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

[First Embodiment of the Invention] FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention according to the present invention, and FIG. 2 is a serial communication apparatus according to the embodiment of the present invention. 3 is a detailed circuit configuration diagram of a plurality of slave stations in FIG. FIG. 3 is a control flowchart of the main station of the serial communication device according to the embodiment of the present invention.
4 to 7 are timing charts showing signal processing in a slave station having a plurality of serial communication devices according to the embodiment of the present invention.

In FIG. 1, reference numeral 20 denotes a central processing unit, which has a CPU 21 for controlling the entire apparatus. CPU
Reference numeral 21 also serves as a master station in serial communication, and the transmitters 22 and 23 and the receivers 24 and 25 execute communication with slave stations. 26, 32, 38, 4
Reference numeral 4 denotes an electronic circuit mounting unit (electric base unit) including slave stations, and includes 27, 33, 39, and 45 slave stations.

The transmission line of the serial communication is constituted by a loop transmission line, and serial data information and a synchronous clock (synchronous clock) generated from the master station are transmitted to 27 slave stations 1 and 3.
The slave station 3 is sequentially transferred to the slave station 3, the slave station 3, and the slave station 4, and finally returned to the master station 21. Reference numeral 15 denotes a memory that stores various data, an operation control procedure of the CPU 21, and the like.

Next, the detailed configuration of each slave station will be described with reference to FIG. FIG. 2 is a circuit diagram showing a detailed configuration of the slave station.

In FIG. 2, 1 is a shift register, and 2 and 4 are data latch circuits. Reference numeral 3 denotes an input port of a slave station, which has a circuit configuration for detecting input information of the electronic circuit mounting unit in real time for each bit. 5 is
This is an output port of a slave station, and has a driver circuit configuration for outputting output information to the electronic circuit mounting unit in real time for each bit.

Reference numeral 6 denotes a decoder circuit, and 7 denotes a counter circuit. The count circuit 7 receives a synchronous clock input from a higher-level station, and outputs a clock frequency division result to the decoder circuit 6 as needed. The decoder circuit 6 includes a counter circuit 7
A predetermined timing is detected and output based on the frequency division result from the clock and the synchronous clock. 8 is a flip-flop circuit, 9, 1
0 and 13 are AND circuits, 11 is an OR circuit, and 12 is NOT
Circuit.

In the embodiment of the present invention, the number of bits to be processed is set to 4 bits and the number of slave stations is set to 4 for ease of explanation. It goes without saying that the number of bits and the number of slave stations are not particularly limited.

An outline of the operation of the slave station having the configuration shown in FIG. 2 will be described. When serial communication is started by turning on the power, a reset (RESET) signal is output from the master station to each slave station prior to serial transfer for each serial communication. The counter circuit 7 is initialized by the RESET signal, and the count start value can always be started from a constant value.

The flip-flop circuit 8 is also initialized by the RESET signal, and the flip-flop circuit 8
The output (hereinafter, referred to as “deletion signal”) is fixed to a deletion execution state (low level). As a result, AN
The outputs of the D circuits 9 and 10 also become low level, and it becomes impossible to transfer serial data information and a synchronous clock to a lower station.

On the other hand, the output of the AND circuit 13 is a signal obtained by inverting the delete signal by the NOT circuit 12, so that the gate is opened to transmit the input data into the shift register 1, and the input serial data Information can be transmitted to the shift register 1.

Next, when the serial data information and the synchronous clock are transferred from the station located at a higher position, the counter circuit 7
Starts to operate, and the serial data information is counted up to the predetermined number of bits from the beginning of the serial data information (the predetermined number of bits is defined as “4 bits” in the embodiment of the present invention) until the counting of 4 bits is completed. Shift register 1 for data information
Shift in.

On the other hand, the transfer data information deleting means constituted by the flip-flop circuit 8 and the AND circuits 9 and 10 deletes and executes the transfer of the serial data information and the synchronous clock to the lower station by the delete signal. continuing.
Therefore, the input serial data information during this period is not output to the lower station.

When the counting of four bits from the beginning of the serial data information is completed by the counter circuit 7, the output from the decoder circuit 6 is turned on, and the flip-flop circuit 8, the data latch circuits 2, 4 and the shift register 1 are turned on. To transmit a timing pulse.

As a result, first, the 4-bit data information shifted into the shift register 1 is stored in the data latch circuit 4.
The output data is latched and output to the electronic circuit mounting unit by the output port 5, and at the same time, the shift data value of the shift register 1 is cleared to zero. The data latch circuit 2 has an input port 3 of the electronic circuit mounting unit.
, The updated input data information is latched in.

On the other hand, in the transfer data information deleting means constituted by the flip-flop circuit 8 and the AND circuits 9 and 10,
The deletion execution of the serial data information and the synchronous clock by the delete signal is canceled, and the transfer of the data information of the fifth bit and subsequent bits from the beginning and the synchronous clock of the fifth and subsequent bits from the beginning is started to the lower station.

Finally, when the counter circuit 7 completes the counting for 16 bits (in the embodiment of the present invention, since four slave stations are used, four stations of 4-bit data for each slave station are used). The transfer data information adding means transfers the data information of the electronic circuit mounting unit generated in the own station by the transfer data information adding means after the last bit of the serial data information transferred to the lower station. 4-bit data is added.

Specifically, the decoder circuit 6 transmits a data value load instruction pulse to the shift register 1.
As a result, the return data information from the electronic circuit mounting unit previously latched by the data latch circuit 2 via the input port 3 is loaded into the shift register 1.

Then, the additional data information shifted out of the shift register 1 is added to the serial data information being transferred by the OR circuit 11, and is transferred from the AND circuit 10 to a lower station.

The above is the outline of the operation of the slave station. The operation timing chart of the slave station described above is shown in the slave station 1 of FIGS. 4 to 7 described later.

Next, an example of control by the CPU 21 as the main station will be described with reference to the flowchart of FIG. CPU2
In No. 1, control other than serial communication control is executed, but only the serial communication control part will be described below for ease of explanation. FIG. 3 is a flowchart showing control in the master station according to the embodiment of the present invention.

When the execution of the serial communication is instructed, the control shifts to the control shown in FIG.

First, at step 51, a reset signal before execution of serial communication is issued to all slave stations, and then, at step 52, the reset signal is released. Thus, each slave station is initialized.

Next, in step 53, the serial data information to be transferred to each slave station is transferred from a predetermined specific storage area in the memory 15 to an accumulator (Acc) in the CPU 21.
Read out. Note that the CP in the embodiment of the present invention
The case where U is a one-word 8-bit CPU will be described as an example. For this reason, the handling of 16-bit data for four slave stations is dealt with by executing twice for every 8 bits. However, the configuration of the CPU is not particularly limited.
One word and 16 bits may be used at a time, and 32 bits, 64 bits, 4 bits, etc.
Of course, any configuration can be used.

When the serial data information to be transferred first is stored in the accumulator in step 53, the synchronizing clock is turned on in the following step 54, and the accumulator is shifted by one bit by a shift instruction in step 55. Then, in step 56, the synchronous clock is turned off, and the transfer operation for one bit is completed.

Further, in step 57, the accumulator (A
cc) to determine whether or not the transfer operation of all bits (for 8 bits) has been completed.
And repeat the processing of steps 54 to 57 until all the bits in the accumulator (Acc) are transferred.

When the transfer of all the bits in the accumulator (Acc) is completed, the process proceeds from step 57 to step 58. In step 58, it is determined whether or not the next transfer data information exists in a predetermined specific storage area in the memory 15. This is performed by determining whether or not the read address “n” of the memory is a predetermined value that is the last address value of the specific storage area. In the embodiment of the present invention, data of 16 bits is transferred in total, so that n = 2.

If the transfer of 8 bits is completed, the next transfer data exists, and the process proceeds to step 59. In step 59, the memory pointer is incremented to indicate the next memory address, and the process returns to step 53. Then, the content stored in the next memory is loaded and transferred to the slave station.

In this way, the contents of the memory are sequentially transferred. When all the transfer data in the memory has been transferred, the transfer operation of the serial data information ends, and the process proceeds from step 58 to step 60. In step 60 and subsequent steps, an operation of reading serial data information returned from the slave station is executed.

First, at step 60, m, which is a unit of capture by the CPU 21, is set. In the embodiment of the present invention, the CPU 21 sets 8 as the predetermined value m because the word has 8 bits per word. Thus, the number of read shift bits at one time is determined according to the number of memory bits.

Subsequently, in steps 61 and 62, a synchronous clock is issued, and in step 63, data sent from the slave station is read. Then, in step 64, the predetermined value is decremented by one, and an end operation of reading one bit is executed. Subsequently, in step 65, it is determined whether the predetermined value has become 0 and the read bit has reached 8 bits.
If the predetermined value is not 0, the process returns to step 61 to perform a reading process for the next bit.

The processing from step 61 to step 65 is repeated, and when the read bit reaches 8 bits, the predetermined value becomes 0. From step 65, the process proceeds to step 66, where the read 8-bit data is stored in a predetermined area of the memory 15. . Further, at step 67, it is determined whether or not reading of 16 bits has been completed. If the reading of all the data bits has not been completed, the process proceeds to step 68, instructs the next data storage memory address, returns to step 61, and executes the above-described reading operation again.

On the other hand, if the reading of all data bits has been completed in step 67, the flow advances to step 69 to end one serial communication operation.

As described above, in the serial communication control in the master station, when return data of 16 bits is transmitted,
Immediately thereafter, it operates to read the return data of 16 bits. The contents of the transfer data and the return data are used in the overall control of the CPU (not shown) to update the contents of the transfer data as needed and to determine the control according to the contents of the return data.

FIGS. 4 to 7 show the timing of data transfer between the master station and each slave station described above. 4 to 7 are timing charts for data information processing as viewed from the slave stations. 4 to 7, FIG. 4 shows the slave station 1, FIG. 5 shows the slave station 2, FIG. 6 shows the slave station 3, and FIG.
6 is a timing chart for the data information processing of FIG.

In FIGS. 4 to 7, the data input to each slave station is started after a predetermined timing (timing for five clock signals) elapses from the output of the RESET signal for each slave station. The processing is started after a lapse of a timing delayed by five clock signals sequentially from 1. In FIG. 4 to FIG.
In the following, data is sequentially transferred to lower-order slave stations in the order of slave station 2 → slave station 3 → slave station 4.

As described above, the master station can easily arrange the serial data information corresponding to each slave station arranged in a predetermined arrangement sequence determined in advance in units of a predetermined number of bits, and transfer the serial data information together with the synchronous clock. With a simple configuration and control, information can be transmitted from the main station. When the transfer is completed, the same number of synchronous clocks as in the transfer are issued,
Reply data information corresponding to each slave station arranged in a predetermined arrangement order determined in advance is read in units of a predetermined number of bits.

On the other hand, the slave station reads out a predetermined number of bits from the first bit of the transfer data information, deletes the read information and the number of clocks corresponding thereto, and substitutes the data generated by itself at the end of the transfer data information. By adding the information, the contents of the transfer data information transferred in a predetermined arrangement determined in advance are rotated in units of a predetermined number of bits. As a result, data reading and data adding operations can be performed uniformly and at the same timing in any slave station.

That is, even if there is no identifier information indicating which slave station corresponds to the data content in the transfer data information, the information contents can be classified into each slave station. Therefore, if any of the slave stations is configured to read the transfer data information uniformly from the head by a predetermined number of bits, and deletes the read information and transfers the remaining data length to the next slave station, the main station can obtain the main data. There is an effect that data information from the station is automatically distributed to each station.

As a result, the configuration of each slave station can be made simple and uniform.

[Second Embodiment of the Invention]
An embodiment of the present invention will be described with reference to a circuit configuration diagram of FIG. 8 and a timing chart of FIG. The second
Also in the embodiment of the present invention, similarly to the above-described embodiment of the first invention, the slave station deletes the transferred serial data information and the synchronous clock by a predetermined number of bits from the head, and An operation is performed in which data information generated by the local station having a predetermined number of bits is added to the last part of the serial data information after a predetermined number of bits from the base station and transferred to the lower side. In this way, rotation of each data array is executed with the data information of the transfer data to each slave station as one unit.

However, in the embodiment of the second invention, the number of bits of the serial data information to be deleted and read and the number of bits of the serial data information generated in the own station to be added must always be the same. And the amount of data to be deleted is different from the amount of data to be added and transferred to the master station.

This is because the input / output information of each electronic circuit mounting unit is often not always the same. Therefore, in the master station, the number of processing bits of the serial data information may be determined in consideration of the number of information bits handled by each slave station. The number of bits to be handled is not unified to all 4 bits as in the embodiment.

In the second embodiment of the present invention,
A case where the number of bits of serial data information generated in the own station added by the slave station is different will be described.
It goes without saying that the processing of data information to be read and deleted by the slave station can be similarly performed. However, if different data processing is performed between the slave stations, the decoder circuit 6
Therefore, it is impossible to unify the decoded values of the slave stations. Therefore, the bit unit in the read data processing or the additional data processing of the slave station must be determined by the unified number of processing bits among the slave stations.

FIG. 8 shows a circuit configuration of a slave station according to the embodiment of the second invention, and FIG. 9 shows a second configuration having the circuit configuration of FIG.
3 shows the operation timing of the slave station according to the embodiment of the present invention.
The same components as those of the first embodiment described above are denoted by the same reference numerals, and description thereof is omitted.

In the embodiment of the second invention, the number of bits of data information to be read or deleted is 4
A case will be described as an example where the number of bits of data information processing generated in the own station to be set and added to bits is set to 8 bits. However, this is an example for facilitating the explanation, and the present invention is not limited to the above example at all, and it goes without saying that the number of bits for data information processing is arbitrary.

In the second embodiment of the present invention shown in FIG. 8, a specific configuration different from that of the first embodiment in the circuit configuration of the slave station is a shift register configuration for processing data information. . That is, in the embodiment of the first invention, data processing is performed by one shift register. However, in the embodiment of the second invention, a shift register for data information processing to be read and deleted includes: The shift register for data information processing generated at the own station to be added is configured to be independent of each other, and to execute data processing corresponding to a preset number of bits.

In FIG. 8, reference numeral 70 denotes a shift register which is separate from the shift register 1 and has, for example, an 8-bit shift register configuration. Reference numeral 71 denotes a latch circuit which latches parallel data output from the shift register 70, and is an 8-bit data latch circuit in the embodiment of the second invention.

Reference numeral 72 denotes an input port for receiving input information from the electronic circuit mounting unit corresponding to the number of bits in the data latch circuit 71.

The operation of the embodiment of the second invention having the above configuration will be described below with reference to the timing chart of FIG.

In the second embodiment of the present invention, the transferred serial communication data information is, as in the first embodiment of the invention, the data information of 4 bits from the head of the data length being shifted by a shift register. At the same time as reading in 1, AN
The gates of the D circuits 9 and 10 are closed so that the data is deleted so as not to be output downstream. The timing during this period is the same as in the first embodiment of the present invention.

Next, at a predetermined timing at which the serial data information to be transferred ends, the data from the data latch circuit 71 is transferred to the shift register 70.
And the shift-out of the data information is started. Then, as in the embodiment of the first invention, OR
Sent to the AND circuit 11 via the circuit 11 and added to the serial communication data as data information generated in the own station;
It is transferred to the lower station.

On the other hand, the control at the master station is the same as that of the first embodiment, and the constant n in the flowchart shown in FIG. 3 is changed according to the number of bits of the data length to be transferred. What is necessary is just to change the constant m in the flowchart shown in FIG. 3 according to the number of bits of the received data length.

As described above, according to the embodiment of the present invention, the number of bits of serial communication data information transferred to each slave station and the number of bits of serial communication data information returned from each slave station to the master station are reduced. If they are handled in unified units, data communication can be performed even when the number of bits of serial communication data information to each slave station and the number of bits of serial communication data information returned from each slave station to the master station are different.

That is, the number of data bits in each slave station unit constituting the serial data information to be transferred is defined as one unit, and the data array of the data length is switched for each unit by passing through one slave station. As a result, serial ring data communication can be executed without changing the circuit configuration of all slave stations and without adding, for example, data for identifying and identifying the receiving slave station called an identifier to the transferred serial communication data.

As a result, the gate array I constituting the slave station
Since the number of C terminals can be minimized and mass production can be performed with an IC having a smaller number of pins in a package, lower cost can be realized.

As described above, according to the first and second embodiments of the present invention, each slave station transmits serial communication data transferred from a station located above each station connected in a loop. On the other hand, by having a transfer data information input means for detecting a predetermined number of bits of data information from the first bit of the communication data and reading it as instruction data information to the own station, the slave station can uniformly receive data information from the master station. To read a predetermined number of bits from the head in the serial communication data received by the own station.

When the slave station reads the data information, the slave station transfers the predetermined number of bits from the first bit of the read data length and the corresponding number of synchronous clocks to the next station by the transfer data information deleting means. Not work.

As a result, the slave station located next is operated to read the information of the predetermined number of bits from the head similarly because the serial communication data with the predetermined number of bits deleted from the head at the preceding station is transmitted. Thereby, in each slave station,
It is possible to read the sorted unique data information which does not overlap.

That is, each slave station is configured to read the transfer data information uniformly from a predetermined number of bits from the beginning, deletes the read information, and transfers the remaining data length to the next slave station located next. For example, data information from the master station can be automatically sorted for each slave station.

Therefore, serial communication can be performed without including identification data information for each slave station to take in the corresponding data information in the transferred data information such as an identifier for reading the data information. As a result, the configuration of the slave station can be simplified, and the number of new input / output devices can be minimized.
For example, even if the slave station is constituted by one gate array IC, the number of terminals of the constituted gate array IC can be realized with 16 pins or less. This has the effect of reducing the cost of the IC package and achieving the lowest cost.

Further, the slave station operates to add the data information generated by itself to the final position of the data length to be transferred by the transfer data information adding means. As for the number of bits, the same data length is always transferred by adding a predetermined number of bits equivalent to the deleted predetermined number of bits. Finally, the operation can be performed such that the reply data information from each slave station having the same bit structure as the data length issued by the master station is transferred to the master station. As a result, the number of transmission data information bits and the number of reception data information bits can be matched in the master station, and control can be simplified.

That is, the data processing timing for the slave station is the same in the number of bits of the data length for both the input and output, so that the gate array IC made with the same circuit configuration can be used for all the slave stations, and the effect of mass production of the IC can be obtained. Is improved.

[0081]

[Other Embodiments] The present invention can be applied to one unit even if it is applied between constituent units in each unit of a system composed of a plurality of units (for example, a host computer, an interface unit, a reader, a printer, etc.). The present invention may be applied to a device including a device (for example, a copying machine, a facsimile device, etc.).

An object of the present invention is to provide a storage medium storing a program code of software for realizing the functions of the above-described embodiments to a system or an apparatus, and to provide a computer (or CPU) of the system or the apparatus.
And MPU) read and execute the program code stored in the storage medium.

In this case, the program code itself read from the storage medium implements the functions of the above-described embodiment, and the storage medium storing the program code constitutes the present invention.

Examples of the storage medium for supplying the program code include a floppy disk, hard disk, optical disk, magneto-optical disk, CD-ROM, and CD.
-R, a magnetic tape, a nonvolatile memory card, a ROM, or the like can be used.

When the computer executes the readout program code, not only the functions of the above-described embodiment are realized, but also the OS (Operating System) running on the computer based on the instruction of the program code. ) May perform some or all of the actual processing, and the processing may realize the functions of the above-described embodiments.

Further, after the program code read from the storage medium is written into a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer, based on the instructions of the program code, It goes without saying that the CPU included in the function expansion board or the function expansion unit performs part or all of the actual processing, and the processing realizes the functions of the above-described embodiments.

When the present invention is applied to the storage medium, the storage medium stores program codes corresponding to the flowcharts described above.

[0088]

As described above, according to the present invention, slave station identification data (identifier) indicating to which slave station certain communication data in the communication data is addressed in the communication data.
Each slave station can take in communication data addressed to the own station without having the communication station. In addition, data can be fetched uniformly and at the same timing in any slave station. That is, according to the present invention, it is possible to classify the information content to each slave station even if there is no identifier information indicating which slave station corresponds to the data content in the communication data information.

Also, even if there is no identifier or the like, data from each slave station is sent to the master station, and the master station can recognize and capture data from each slave station separately for each slave station.

Therefore, it is possible to exchange data information with all the slave stations having the same circuit configuration.
In this case, the number of terminals of the IC can be suppressed to the minimum, the IC can be mass-produced as a package having a smaller number of pins, and the serial communication device can be realized at lower cost.

[0091]

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration in an embodiment of the present invention.

FIG. 2 is a detailed circuit configuration diagram of a plurality of slave stations in the serial communication device according to the embodiment of the present invention.

FIG. 3 is a flowchart showing control in a master station according to the embodiment of the present invention.

FIG. 4 is an operation timing chart in each slave station according to the embodiment of the present invention.

FIG. 5 is an operation timing chart in each slave station according to the embodiment of the present invention.

FIG. 6 is an operation timing chart in each slave station according to the embodiment of the present invention.

FIG. 7 is an operation timing chart in each slave station according to the embodiment of the present invention.

FIG. 8 is a circuit configuration diagram of a slave station according to the second embodiment of the present invention.

FIG. 9 is an operation timing chart of a slave station according to the embodiment of the second invention.

[Explanation of symbols]

 1, 70 shift register 2, 4, 71 data latch circuit 5 output port to electronic circuit mounting unit 3, 72 input port to electronic circuit mounting unit 6 decoder circuit 7 counter circuit 8 flip-flop circuit 9, 10, 13 AND circuit Reference Signs List 11 OR circuit 12 NOT circuit 20 Central processing unit 26, 32, 38, 44 Electronic circuit mounting unit 21 Master station 27, 33, 39, 45 Slave station

Claims (9)

[Claims] A central station for data communication is arranged in a central processing unit mounting unit in a mounting unit mounted in an apparatus, and data communication is performed for each of other mounting units mounted in the apparatus. A data communication device comprising a slave station, wherein the master station and the slave station are connected by a loop communication medium to enable information exchange between a plurality of mounting board units mounted in the device. A data information transfer means for generating communication data of a data length in which data information for all the slave stations for data communication output from the master station are collected and transferring the communication data to each slave station; Synchronous clock transfer means for generating a synchronous clock signal for communication and transferring the generated signal to the slave station, wherein the communication data indicates corresponding data information to each slave station in the transferred data information. Data communication apparatus, characterized in that it is constituted by the data information content that does not include the identification data information for. 2. The communication data is serial data, wherein the slave station receives communication data transferred from a station located at a higher rank of each station connected in a loop, and receives a first bit of the received communication data. Transfer data information input means for receiving data information of a predetermined number of bits as transfer data information to the own station from; and a predetermined number of bits of data information from the first bit of communication data captured by the transfer data information input means. Transfer data deleting means for deleting the received synchronous clock corresponding to the data information and transferring the communication data to the slave station located at the new next stage and the synchronous clock signal to the slave station located at the new next stage. 2. The data communication device according to claim 1, comprising: 3. The slave station detects the timing corresponding to the last bit position of the communication data with respect to the communication data transferred from the station located above the stations connected in a loop, and 3. The data communication apparatus according to claim 1, further comprising a transfer data information adding means for adding a data information output generated by the local station having a predetermined number of bits after the last bit. . 4. The return data information reading which sequentially reads communication data transferred from a slave station located at the lowest position of each of the stations connected in a loop as return data information from each slave station in units of a predetermined number of bits. 4. The data communication device according to claim 3, further comprising: means. 5. A central station for data communication is arranged in a central processing unit mounting unit in a mounting unit mounted in an apparatus, and data communication is performed for each of other mounting units mounted in the apparatus. A data communication method in a data communication device in which a slave station is arranged and the master station and the slave station are connected by a loop communication medium to enable information exchange between a plurality of mounting board units mounted in the device. The master station transmits communication data for data communication output from the master station to data information that does not include identification data information for indicating corresponding data information to each slave station in the transferred data information. Along with transferring the data information for all slave stations composed of the contents to the slave stations as serial communication data, the synchronous clock signal for capturing the communication data is transmitted. The slave station receives communication data transferred from a station located above the stations connected in a loop, and receives a predetermined number of bits of data from the first bit of the received communication data. The information is fetched as transfer data information to the own station, and a predetermined number of bits of data information from the first bit of the fetched communication data and the received synchronous clock corresponding to the data information are deleted to form a new next stage. A data communication method comprising: transferring the communication data to a located slave station and a synchronization clock signal to the slave station located at the new next stage. 6. The slave station detects the timing corresponding to the last bit position of the communication data with respect to the communication data transferred from a station located above each station connected in a loop, and detects the timing of the communication data. 6. The data communication method according to claim 5, wherein after the last bit, a data information output having a predetermined number of bits and generated by the own station is added and transferred to a lower slave station. 7. The master station sequentially reads communication data transferred from a slave station located at the lowest position of each station connected in a loop as a return data information from each slave station in a unit of a predetermined number of bits. 7. The data communication method according to claim 6, wherein: 8. A storage medium storing a control procedure for realizing the function according to claim 1. Description: 9. A program for realizing the function according to any one of claims 1 to 7.