JPH1155270A - Cell exchange device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To change the number of storage lines and the combination of the speed of the storage lines by providing a buffer part which temporarily stoves respective inputted cells and a bus contention control part controlling read timing from the buffer part and timing contention and multiplexing and outputting the respective cells which are read by a bus. SOLUTION: An ATM exchange is provided with input control parts 11-15, a main switch part 16 and output control parts 17-20. The ATM exchange contention-controls the outputs of the cells inputted from the respective low speed lines to the multiplex bus 14 and multiplexes the cells from the respective lines on the bus 14 and therefore it can correspond to arbitrary line speed. Then, hardware constitution can be reduced by intensively giving a header required for switching in the switch part 16 by the header conversion part 15 prepared in common to the respective lines.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cell switching apparatus, and is suitably applied to, for example, an asynchronous transfer mode (ATM) exchange.

[0002]

2. Description of the Related Art FIG. 2 shows the configuration of a conventional ATM exchange. Generally, in this type of ATM switch,
It is assumed that a high-speed line requiring a band of 156 Mbps is accommodated. However, the practical line bandwidth is
The speed is relatively low, from 1.5 Mbps to 6.3 Mbps.
Further, even when a LAN is accommodated, the bandwidth of a commonly used Ethernet or the like is about 10 Mbps.

However, the main switch unit 4 of the ATM exchange has
(FIG. 2) is also assumed to accommodate a high-speed line (156 Mbps or the like), and the basic design is often adapted for a high-speed line.

In such an apparatus, in order to accommodate a low-speed line as described above, the line accommodating section (multiplexing section 2 and demultiplexing section 6) accommodates the signal through two processes of multiplexing and demultiplexing. Was common. On the other hand, when accommodating a high-speed line, a method of directly connecting using the high-speed line input / output interfaces 8 and 9 is adopted.

[0005]

Problems of the prior art will be described with reference to FIG. FIG. 3 shows various functions of the ATM exchange in more detail. Less than,
The function and operation of each unit will be described based on FIG.

Each low-speed line input interface unit 1
The cells input from (1), 1 (2),..., 1 (n) are respectively provided with VPI (virtual path connection identifier) and VCI (virtual channel connection identifier) for identifying the connection. .

[0007] Usually, an ATM exchange selects an outgoing port and an identifier based on these identifiers and performs an exchange operation. In this type of exchange, in addition to such identifiers, an in-device header is used. I do. This header is a header (switch control header) used for routing in the main switch unit 4. The additional function is called a switch control header adding function (or a header converting function).

As described above, the switch control header adding unit 1A
In (1), 1A (2),..., 1A (n), when a switch control header is added to a cell input from each line, the multiplexing unit 2 at the next stage next causes the main switch unit 4 Multiplexing cells up to the input link capacity (for example, 156 Mbps).

[0009] Here, the cell input to the multiplexing unit 2 is:
The buffers 2A (1), 2A (2),..., 2A (n) are temporarily stored and multiplexed. The multiplexed cells are input to the main switch unit 4 and exchanged, and then input to the demultiplexing unit 6 in the next stage.

The demultiplexing unit 6 sorts each cell input from the main switch unit 4 into a corresponding line based on the above-described switch control header in the demultiplexing unit 6A. Cell buffer 6B (1), 6B (2)
,..., 6B (n).

As described above, the cell buffers 6B (1), 6B
(2),..., 6B (n) are buffered so that cells arriving at a high speed can be output to a low-speed line.

That is, the transmission speed control section 6C (1) at the next stage
, 6C (2),..., 6C (n) function to keep the outgoing traffic flow to the low-speed line output interface units 7 (1), 7 (2),. , The cell buffers 6B (1), 6B (2),
.., 6B (n) are used.

However, the ATM switch having such a configuration has the following problems.

(1) First, corresponding to each incoming line, a switch control header adding section 1A (1), 1A (2),... 1A (n)
Is required, which increases the hardware scale.

(2) Secondly, since an interface is required for each physical line accommodating the incoming line, it is expected that the number of input signals of the multiplexing unit 2 will increase (that is, a pin neck is expected). ).

(3) Third, since an interface is required for each output line, the number of output signals from the demultiplexing unit 6 is expected to increase (that is, a pin neck is expected).

(4) Fourth, the line speed and the number of lines to be accommodated are specified. For example, in the case of this multiplexing / demultiplexing method, the assumed line speed and number of lines are specified as 1.5M × 8 lines or 6.3M × 4 lines. In addition, even when a line or the like is extended, it is determined according to the above-described implementation specification of the multiplexing / demultiplexing unit, and a problem of lack of flexibility occurs (the multiplexing / demultiplexing unit is expanded).

[0018]

In order to solve the above-mentioned problems, in the present invention, at least two or more low-speed lines are accommodated, and each cell input via each of the low-speed lines is used as a cell.
A cell switching apparatus that exchanges at least twice the speed of each line is provided with the following means.

That is, in the input interface unit accommodating the low-speed line, (1) a buffer unit for temporarily storing each cell input from each low-speed line corresponding to each low-speed line, and (2) a buffer A bus contention control unit that controls the read of cells from the buffer unit, controls the read timing from the buffer unit corresponding to each low-speed line, and controls contention of the timing; and (3) a buffer unit corresponding to each low-speed line. And a bus for multiplexing and outputting each cell read from the cell.

As described above, by multiplexing low-speed lines on the bus, the combination of the number of accommodated lines and the speed of the accommodated lines can be flexibly changed.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION

(A) First Embodiment Hereinafter, a first embodiment of an ATM exchange according to the present invention will be described with reference to the drawings.
An embodiment will be described.

(A-1) Configuration of First Embodiment (A-1-1) Overall Configuration FIG. 1 shows a configuration of an ATM exchange according to a first embodiment. This ATM exchange is roughly divided into an input control unit 1
1 to 15, a main switch section 16, and output control sections 17 to 20 and have the following four feature points.

1. A cell multiplex bus is used (flexibility of the number of accommodated lines and speed is secured).

2. The point of adopting the physical line selection identifier (PID) and the point that the header conversion is controlled centrally (reduction of the scale of the input-side header conversion circuit and reduction of the circuit of the output-side demultiplexing unit).

3. Centralized control of line transmission traffic flow control (reduction of output separation circuit).

Hereinafter, the configuration of each unit will be described in order.

(A-1-2) Configuration of the Input Control Unit The input control unit includes the physical line interfaces 11 and 12,
Incoming cell multiplex bus interface unit (CBIinf) 1
3; an incoming cell multiplexing bus (CBI) 14; and a header converter (HCV) 15.

The physical line interfaces 11, 12 are n
N low-speed line input interface units (PHI) 11 (1), 11 (2),... 11 corresponding to the respective low-speed lines
(n) and n temporary storage cell buffers 12 (1), 12 (2),... 12 (n) corresponding to each of them.

The temporary storage cell buffers 12 (1), 12 (2)
,..., 12 (n) are temporary storage means used to multiplex cells input via each low-speed line.
(1), 13 (2),..., 13 (n).

Incoming cell multiplex bus interface unit 13
(1), 13 (2),..., 13 (n) are physical line selection identifiers (PIDs) for cells input from the corresponding temporary storage cell buffers 12 (1), 12 (2),. This is an interface unit whose main function is to provide the content and control competition.

The cells input from each low-speed line are divided into the n input-side cell multiplex bus interface units 13 (1), 1
.. 13 (n) are read from the temporary storage cell buffers 12 (1), 12 (2),... 12 (n) and multiplexed on the incoming cell multiplex bus 14. Is done.

At this time, the input-side cell multiplex bus interface units 13 (1), 13 (2),..., 13 (n) determine that the total bandwidth of each low-speed line is equal to the bandwidth of the input-side cell multiplex bus 14 (ie, Control is performed so that the bandwidth of each low-speed line is provided so as not to exceed the bandwidth of the main switch (SW) 16).

Thus, the temporary storage cell buffer 12
The capacity required for (1), 12 (2),..., 12 (n) can be minimized (several cells). The cells multiplexed on the incoming cell multiplex bus 14 are output to the header conversion control unit 15.

The header conversion control unit 15 converts the input cell into a header of an outgoing cell based on the header added to the input cell, and adds a switch control header. Here, the header conversion control unit 15 is provided for each route unit of the main switch unit 16.

(A-1-3) Configuration of Output Control Unit The output control unit includes an egress line control unit (PSHP) 17, an egress cell multiplex bus (CBO) 18, and an egress cell multiplex bus interface unit ( CBOinf) 19 and an outgoing line interface unit (PHO) 20.

The outgoing line control unit 17 includes a main switch unit 16
And a cell buffer 17B, a cell buffer selector 17A, and a cell buffer 17B.
7C and a transmission traffic control unit 17D.

The cell distribution unit 17A functions to select the cell buffer 17B based on the physical line selection identifier PID assigned on the input side. The transmission traffic control unit 17D also functions to extract the cell header and determine the transmission traffic flow for each line (for each PID). Further, the cell buffer selecting unit 17C determines whether the cell buffer 17 is based on the determination result of the transmission traffic control unit 17D.
Functions to select B.

As a result, the cells controlled in accordance with the respective outgoing line speeds are multiplexed and outputted to the output of the outgoing line control section 17, and are output to the next stage outgoing cell multiplexing bus 18
Sent up.

The output line interface units 20 (1), 20 (2),..., 20 (n) corresponding to each low-speed line are provided with the outgoing cell multiplex bus interface units 19 (1), 19 (2),. 1
9 (n) is connected to the outgoing cell multiplex bus 18.

(A-2) Operation of the First Embodiment (A-2-1) Changes in Cell Flow and In-Device Header Information Here, the ATM according to the first embodiment will be described with reference to FIG.
A description will be given of an outline of a flow of cells in the exchange and a change of the cell header due to the internal control at this time.

The upper part of FIG. 4 shows the same configuration as that of FIG. 1, and the lower part shows how the cell header changes under the control in the apparatus.

As is well known, ATM is a method of transferring information in cells (fixed-length packets of 53 bytes), and each cell is provided with VPI / VCI for identifying each connection.

The ATM exchange operates as described above with the incoming connection identifier (VPI1) added to the header of each cell.
/ VCI1) to select the outgoing line based on the outgoing line connection identifier (VPI2 / VCI1).
CI2). Hereinafter, the cell exchange operation will be described.

First, each cell input from the low-speed line to the ATM switch (point A in FIG. 4) is input to the incoming-side cell multiplex bus interface units 13 (1), 13 (2),... 13 (n). After the contention control, the physical line selection identifier (PID)
(Point B in FIG. 4).

Each cell that has been subjected to contention control is input to the header conversion unit 15 via the incoming cell multiplex bus 14, and is subjected to header conversion. Here, the header conversion unit 15 uses the identifier (P) assigned to the header of the cell arriving from each low-speed line.
(ID + VPI + VCI), and refers to a conversion table set in advance by software. Then, a route selection identifier SWHD, a physical line identifier PID, and a VPI / VCI on the output side of the main switch unit 16 are assigned (C in FIG. 4).

Each cell whose header has been converted is input to the main switch unit 16. The main switch unit 16 controls the S of each cell.
An outgoing route is selected based on the WHD, and the outgoing line control unit 17 is selected.
(D in FIG. 4).

The outgoing line control unit 17 selects the cell buffer 17B according to the physical line identifier PID assigned to the arriving cell, and outputs it to the corresponding cell buffer 17B.

The output traffic control unit 17D controls the speed of cells to be transmitted for each physical line identifier PID (for each line), and the corresponding cell is not transmitted beyond the bandwidth of each line set in advance by software. Control.

The cell buffer selecting section 17C receives an instruction from the output traffic control section 17D and outputs a signal to each cell buffer 1C.
The cell temporarily stored in 7B is read.

By the functions of the cell buffer selector 17C and the output traffic controller 17D, cells controlled so as not to exceed the bandwidth of each line are multiplexed and read out on the egress cell multiplex bus 18.

Since the outgoing cell multiplex bus 18 is connected to each line unit in a bus form, the outgoing cell multiplex bus 1
The output of 8 is the output cell multiplexed bus interface units 19 (1), 19 (2),...
(n) (E in FIG. 4).

Here, each of the outgoing cell multiplex bus interface sections 19 (1), 19 (2),... 19 (n) is assigned to its own line among the cells inputted from the outgoing cell multiplex bus 18. Only the cell having the physical line selection identifier PID2 extracted is extracted, and the outgoing line interface unit 20 (1),
20 (2),..., 20 (n) (F in FIG. 4).

The above is the outline of the flow of cells in the ATM exchange and the accompanying change operation of the header information.

(A-2-2) Detailed Operation in Input Side Control Unit Next, more detailed operation contents of the input side control unit for realizing the above operation and a configuration for realizing the operation will be described.

FIG. 5 is a detailed block diagram of the entry-side control unit for explaining this operation. FIG. 6 is a diagram illustrating an outline of a header conversion method executed in the input side control unit.

As shown in FIG. 5, cells output from each line input interface unit 11 (i) are input to a cell buffer 12 (i) provided corresponding to each line, and temporarily stored. Is done.

From each cell buffer 12 (i), a cell valid signal clav1 indicating the presence / absence of a cell is output to the corresponding incoming cell multiplex bus interface 13 (i). In addition,
The cell valid signal clav1 is transmitted to each interface 13 (i)
It is input to the competition control circuit (ABT) 13A provided in the inside.

When the cell valid signal clav1 becomes valid,
The contention control circuit 13A is connected to another circuit (a contention control circuit of another input-side cell multiplex bus interface) by a signal line AB.
The contention control of the incoming cell multiplex bus 14 is executed based on information necessary for contention control input / output via Tctl (for example, display during data transfer).

The contention control circuit 13A for the cell that has survived this contention control is sent to the physical line interface section (P
HYinf) Validates the read instruction rdst1 for 13B. When the read instruction rdst1 becomes valid in this manner, the physical line interface unit 13B reads the cell from the cell buffer 12 (i), and reads the cell from the cell buffer 12 (i).
The ID is transferred to the ID stamp unit 13C.

The PID stamp unit 13C stores a PID value (stored in the PID holding register 13E) set by software in advance into a preset VPl
It stamps and outputs the higher-order bits that exceed the effective range (line equipment conditions) (see FIG. 6).

Here, the physical line selection identifier PID is added to the bit portion located immediately above the effective VPI because of the degeneration (only the number of effective bits of the VPI and VCI performed by the header conversion unit 15 at the next stage). This is to make it possible to utilize the function of indexing the conversion table together) effectively.

In order to realize this function, the input-side cell multiplexed bus interface 13 (i) is provided with a register (V set by software) for holding the number of valid VPl bits decided on the line interface.
The PID valid register 13F) has a function of determining the position of the PID bit to be stamped and stamping the PID value set in the PID holding register 13E.

As described above, the information (cell) stamped with the physical line selection identifier PID is transmitted to the input-side cell multiplex bus 14.
Is output to the header conversion unit 15 via the. The contention control unit 13A performs contention control based on various timing signals transmitted from the header conversion unit 15, and performs the transmission before the transmission of the cell.
Is transmitted.

Here, the transmission timing of the cell valid signal clav2 is set to an optimal timing for transferring the cell stream. For example, the cycle is set to “the number of clocks required for cell stream transfer” + “the number of clocks required for switching”. With this setting, useless overhead on the cell bus can be optimized.

The cell bus interface control unit 15A of the header conversion unit 15 checks the cell valid signal clav2 signal supplied from the incoming cell multiplex bus interface 13 (i) at each timing, and reads out the valid cell if there is a valid cell. The control signal rdctl2 is made valid to notify the reception of the cell.

As described above, when a cell is input via the input cell multiplex bus 14, the header conversion section 15
In B, the VPI value extracted from the header portion and V
A process of reducing the Cl value to only valid bits is performed (FIG. 6). The VPI value and the VCI value after degeneration are stored in the conversion table 1
5C to index the corresponding path. The header information to be degenerated is set in consideration of the bit range of the PID in addition to the VPI + VCI.

If the PID is taken into account, header conversion for each line can be realized by one header conversion unit 15. The conversion table 15C stores in advance the outgoing route, PID and VPI value /
The VCI value is set. By doing so, the outgoing header information converted based on the input header information of the cell is added to the cell and output to the main switch unit 16.

(A-2-3) Detailed Operation in Output Control Unit Next, the detailed operation of the output control unit will be described. The feature realized by the outlet control unit is a main switch unit 16.
The point is that the line control unit 17 provided on the outgoing side route can collectively execute speed control corresponding to each line.

This will be described with reference to FIG. Each cell routed for each route by the main switch unit 16 is stored in the cell buffer 17B of the line control unit 17. The cell buffer 17B is controlled by a page memory control unit (MEM-CTL) 17E1, and has a configuration in which pages are managed for each cell.

Further, the write control unit (WR-CTL) 17E2 that writes data in the cell buffer 17B stores the page address (page memory information) and the header information (PID information) written in the arriving cell in the PID. Notify the queue control unit (PID-Queue) 17D1.

Here, the PID queue control unit 17D
1 operates to configure a virtual queue for each notified PID information. That is, a chain of memory addresses in which cells are stored is formed in the order of arrival for each PID. This information is further
The determination unit 17D2 that determines the transmission speed for each ID is notified. Here, a determination unit having a transmission history counter for each PID is assumed.

The information queued in each PID queue control unit 17D1 is determined at a timing corresponding to the maximum transmission speed (coincided with the speed of the outgoing cell multiplex bus 18). (Page memory information) is sent to the read control unit (RD-CTL).

As a result, the cells whose speeds have been controlled for each PID are output to the outgoing cell multiplex bus 18 (function of the outgoing traffic flow control (shaping) unit in FIG. 8). Each cell output to the outgoing cell multiplex bus 18 is connected to an interface unit (CBOinf in FIG. 7, CBoa, CBo in FIG. 8) of the outgoing cell multiplex bus 18 provided for each line.
b, CBoc, CBod).

Here, the egress cell multiplex bus interface unit 19 extracts the PID header from each cell into the PID extraction unit 19.
A is extracted at A, and the extracted PID is provided to the PID determination unit 19B, thereby inspecting the PID header attached to each cell.

At this time, the PID determination section 19B
By comparing the contents of the PID header extracted from the bit position stored in the bit position register 19C with the value set in the outgoing PID value register 19D, it is determined whether or not the cell is addressed to itself. Perform an inspection.

Then, the selector 19E is controlled so that only the one that matches its own PID value is passed to the next stage. Here, the PID bit position indicates the same position as the PID bit position assigned by the input side control unit.

If it is determined as a result of the inspection that the arriving cell matches its own PID value, the PID header deletion unit (PID-del) 19F deletes the PID header added to the header. I do.

Specifically, as shown in FIG. 9, "0" is set to all of the relevant bit portions. By the way, the bit for selecting the exit side route of the main switch which is no longer needed is also deleted at the same time.

On the other hand, if it is determined that the arrived cell does not match its own PID value, the idle cell generator 19
Insert and output idle cells generated in G.

The above is the detailed contents of the operation executed by the output side control unit.

(A-3) Effects of the First Embodiment As described above, in the ATM exchange according to the first embodiment, the output of cells input from each low-speed line to the bus 14 is contention-controlled. By employing a method of multiplexing cells from these lines on the bus, it is possible to realize an ATM switch that can handle an arbitrary line speed.

Further, this makes it possible to configure a line accommodating section which assumes various numbers of lines according to the line type.
For example, expansion for each line is possible.

The headers required for switching in the main switch unit 16 are intensively executed in the header conversion unit 15 prepared in common for each line (that is, provided in the interface unit 13 corresponding to each line). (Using the physical line identifiers PID and the conversion table 15C prepared for them)), it is possible to realize an ATM exchange having a smaller hardware configuration than in the past.

Furthermore, the speed control for each output line is performed centrally in the outgoing line control unit 17, so that the speed control is performed at the interface unit of each line as in the conventional case. The hardware configuration can be made smaller as compared with the above.

(B) Second Embodiment Referring now to the drawings, a second embodiment of the ATM exchange according to the present invention will be described.
An embodiment will be described.

(B-1) Configuration of Second Embodiment FIG. 10 shows the configuration of an ATM exchange according to a second embodiment. The ATM exchange according to the second embodiment is characterized in that the outgoing line control unit 17 'is provided in both the low-speed line accommodating unit and the high-speed line accommodating unit. It has the same configuration as the ATM exchange according to the embodiment.

Here, the configuration of the outgoing line control unit 17 ′
Basically, the delivery control unit 1 described in the first embodiment.
7 is different from that of FIG. 7 in that a VC / port control unit 17D 'that realizes a transmission traffic control function in units of virtual channels (VC) is used for cell read control.

This is for controlling the output traffic flow in VC units for the output line. Note that the transmission traffic speed control of the VC unit for the outgoing line described here is the speed (bandwidth) of the connection set at the end and end, and is independent of the physical line speed.

FIG. 11 shows a detailed configuration of the outgoing line control unit 17 '. The outgoing line control unit 17 'is connected to the outgoing side of the main switch unit 16 like the outgoing side control unit 17 described in the first embodiment. It is connected to the multiplex bus 18 or the high-speed line physical control unit 21.

The output control unit 17 'is a cell buffer (CELBUF) 17B for storing information for each cell controlled by the page memory control unit (MEM-CTL) 17E1.
And page memory write control unit (WR-CTL) 17E2
, Read control unit (RD-CTL) 17E3, and VC / p
and an ort control unit 17D '.

Here, the write control unit 17E2 and VC / po
The rt control unit 17D 'is connected via a signal notifying the header information of the arriving cell and a signal line notifying the written page memory management information.

Similarly, read control unit 17E3 and VC / po
The rt control unit 17D 'is connected via a signal line for notifying a read instruction and page memory management information to be read.

The VC / port control unit 17D '
A C queue control unit (VC-Queue) 17D11;
VP / PID queue control unit (VP / PID-Queue)
e) It is composed of 17D12 and the determination unit 17D2.

Here, the VC queue control unit (VC-Qu
eue) 17D1 'is the V of the header information of the received cell.
It has a function of configuring a queue based on the C information and measuring the cell interval of the same VC that has arrived.

The VP / PID queue control unit (VP
/ PID-Queue) 17D2 'constitutes a VP / PID queue from the received PID and VPl information of the header information of the cell, and arrives at the same VP /
It has a function to measure the cell interval of the PID.

The determination unit 17D2 operates to determine these measured cell intervals based on the transmission cell intervals and allowable values set in advance by software.

(B-2) Operation of the Second Embodiment Next, the operation of the ATM exchange having the above configuration will be described. Since the flow of the entire operation is the same as that of the first embodiment, in the following description, the operation of the outgoing line control unit 17 'which is a component specific to the second embodiment will be described in detail. explain.

First, the cells received from the main switch unit 16 to the outgoing line control unit 17 'are stored in the cell buffer 17B whose pages are managed by the page memory write control unit 17E2.
Is written to.

Here, the page management is a function of dividing the memory into storage areas for one cell information such as one page, two pages,..., And enabling random access in page units. It is controlled by the unit 17E1.

The page memory write control unit 17E2 writes the sequentially arriving cells into the cell buffer 17B managed in this way, and simultaneously writes the sequentially arriving cell header into the VC / port control unit 17D '. Information (PI
D, VPI, and VCI values).

The VC queuing control unit 17D11 constituting a virtual queue (queue) for each VC, based on the header information, converts the valid part (value set in advance by software) of the received VCl value. The cells are extracted, arranged in the order of arrival, and the cell interval is measured (FIG. 12).

At the same time, the VP / PID queue controller 17
In D12, the effective parts of the received PID value and VPI value are extracted and arranged in the arrival order, and the cell interval is measured (FIG. 12).

These results are provided to the next-stage determination section 17D2, where the determination section 17D2 checks against a value set in advance by software. When both the measurement value of the VC queue control unit 17D11 and the measurement value of the VP / PID queue control unit 17D12 satisfy the condition, it is determined to be OK.

The cell judged to be OK is notified of the read instruction signal together with the page memory information in which the user information is stored. The read control unit 17E3 reads the cell based on the read instruction signal and the page memory information. Here, at the time of high-speed line connection, the PID value is set to “0”.
That is, the content of PID + VPI is controlled by software so that only the VPI value has meaning.

(B-3) Effects of the Second Embodiment As described above, according to the second embodiment, a device that needs to control the outgoing traffic flow rate on a VC basis and uses a low-speed line and a high-speed line In an apparatus to be accommodated, hardware can be shared by disposing the outgoing line control unit 17 'on both the low-speed line and the high-speed line.

Further, similarly to the first embodiment, the adoption of the cell bus and the centralized deployment of the outgoing traffic control can be realized, so that the hardware can be reduced in size.

(C) Other Embodiments In the above embodiments, the present invention has been described by taking an ATM exchange as an example, but the present invention can be widely applied to apparatuses having a cell exchange function.

[0108]

As described above, according to the present invention, it is possible to (1) temporarily store each cell input from each low-speed line corresponding to each low-speed line in the input interface unit accommodating the low-speed line. A buffer unit to be used, (2) a bus contention control unit that controls reading of cells from the buffer unit, controls read timing from the buffer unit corresponding to each low-speed line, and controls contention of the timing, 3) a bus for multiplexing and outputting each cell read from the buffer unit corresponding to each low-speed line, and multiplexing the low-speed line on the bus, thereby accommodating compared to the conventional case. The combination of the number of lines and the speed of the accommodated line can be flexibly changed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of an apparatus according to a first embodiment.

FIG. 2 is a block diagram showing a schematic configuration of a conventional device.

FIG. 3 is a block diagram showing a detailed configuration of a conventional device.

FIG. 4 is a diagram showing a flow of a cell transferred in the device according to the first embodiment and a state of change of cell header information.

FIG. 5 is a diagram provided for describing an operation in an entry-side control unit.

FIG. 6 is a diagram illustrating a state of centralized control of header conversion.

FIG. 7 is a diagram provided for describing an operation in an output side control unit.

FIG. 8 is a diagram showing a flow of a cell in an egress control unit.

FIG. 9 is a diagram showing a flow of processing performed on a cell header.

FIG. 10 is a block diagram illustrating a schematic configuration of an apparatus according to a second embodiment.

FIG. 11 is a diagram illustrating an internal configuration of a delivery control unit.

FIG. 12 is a diagram illustrating an operation state of a VC / port control unit.

[Explanation of symbols]

11: Low-speed line input interface unit, 12: Temporary storage cell buffer, 13: Incoming cell multiplex bus interface unit, 13A: Contention control circuit, 13B: Physical line interface unit, 13C: PID stamp unit, 13E: PID
Holding register, 13F: VPl valid register, 14: incoming cell multiplex bus, 15: header conversion unit, 15A: cell bus interface control unit, 15B: degenerate unit, 15C: conversion table, 15D: header adding unit, 15E: SW interface , 16: Main switch unit, 17, 17 ': Outgoing line control unit, 17A: Cell distribution unit, 17B: Cell buffer, 17C: Cell buffer selection unit, 17D: Outgoing traffic control unit, 17D1: PID queue control unit , 1
7D ': VC / port control unit, 17E1: page memory control unit, 17E2: write control unit, 17E3: read control unit, 18: outgoing cell multiplex bus, 19 ... outgoing cell multiplex bus interface unit, 19A: PID Header extractor, 19
B: PID determination unit, 19C: PID bit position register, 19D: output PID value register, 19E: selector,
19F: PID header deletion unit, 20: outgoing line interface unit, 21: high-speed line physical control unit.

Claims (8)

[Claims] At least two or more low-speed lines are accommodated,
In a cell switching apparatus for exchanging each cell input via each of the low-speed lines at a speed at least twice as high as the line speed, an input interface unit for accommodating the low-speed lines corresponds to each of the low-speed lines. A buffer unit used to temporarily store each cell input from the low-speed line; controlling reading of cells from the buffer unit; controlling read timing from a buffer unit corresponding to each low-speed line; A cell switching device, comprising: a bus contention control unit that controls contention of a cell; and a bus that multiplexes and outputs each cell read from a buffer unit corresponding to each low-speed line. 2. The cell switching device according to claim 1, wherein each cell before multiplexing is input to the input interface unit accommodating the low-speed line, and an input line of each cell is indicated in a header of each cell. A physical line selection identifier assigning unit that assigns a physical line selection identifier, and inputs each multiplexed cell, and is used for switching each cell based on the physical line selection identifier and the connection identifier read from the header of each cell. Cell switching device, comprising: a header switching unit for providing an egress route selector of an egress main switch unit, an egress physical line selection identifier corresponding to an egress low-speed line, and an egress connection identifier. . 3. The cell switching device according to claim 2, wherein an output interface provided by said header conversion unit to an output interface unit for outputting each cell exchanged in said main switch unit to a corresponding low-speed line. A cell switching device comprising a transmission traffic control unit for controlling a transmission traffic flow rate so as not to exceed a band of an outgoing low-speed line for each physical line selection identifier. 4. The cell switching device according to claim 3, wherein the output interface unit includes a bus for inputting each cell output from the transmission traffic control unit, and a cell among the cells input via the bus. And a bus interface unit for outputting only a cell having an outgoing physical line selection identifier assigned thereto to a corresponding outgoing low speed line. 5. The cell switching device according to claim 2, wherein the physical line selection identifier assigning unit has a register that holds a value of the physical line selection identifier to be assigned, and a register that holds the number of effective bits of the connection identifier. Wherein the value of the physical line selection identifier held in the register is added to the position immediately above the effective bit of the virtual path identifier in the connection identifier. 6. The cell switching device according to claim 2, wherein said header conversion unit indexes effective bits of an outgoing physical line selection identifier and an outgoing connection identifier to look up a conversion table. Cell switching equipment. 7. The cell switching device according to claim 3, wherein the output interface unit forms a virtual queue for each outgoing physical line selection identifier,
A cell switching device comprising a determination unit for measuring a cell interval for a corresponding outgoing line. 8. The cell switching device according to claim 3, wherein the output interface unit comprises a determination unit that forms a virtual queue for each connection and measures a cell interval for a corresponding outgoing line. Characteristic cell switching equipment.