JPH1153307A - Serial interface bus transmitting and receiving circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the influence of malfunctions even when the timing limit condition is not satisfied by performing a time limit operation based on the detection result of a data transmission/reception start and stop detection means and outputting the stop and start condition recognizing signals after a set time. SOLUTION: A stop condition detecting D flip-flop 6a and a start condition detecting D flip-flop 6b are reset when a clock signal is set at an L level on a clock signal supply line SCL despite the simultaneous changes of the clock signal set on the SCL and the data set on a data supply line SDA. Then a 2nd time limit measurement circuit 56 is reset when the clock signal is set at an L level. Thereby, the stop condition disappears when the clock signal is set at an L level even right after the stop condition is detected by the flip-flop 6a when both clock signal and data simultaneously change. As a result, the malfunctions can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial interface bus transmitting / receiving circuit for transferring information by using two signal lines, a data signal line and a clock signal line.

[0002]

2. Description of the Related Art As a conventional serial interface bus transmitting / receiving circuit, there is an I ² C bus, which is used for information transfer between ICs used in electric circuits such as TV products and VTR products. FIG. 6 is a circuit diagram showing a configuration of a conventional serial interface bus transmission / reception circuit.
1 is a data signal line for outputting data of a serial interface bus, and 2 is a clock signal line for outputting a clock signal of the serial interface bus. This serial interface bus is connected to a master device (not shown) such as a microcontroller. It is connected. Reference numeral 3 denotes a data input buffer circuit for taking in the data output to the data signal line 1 into the serial interface bus transmission / reception circuit, and reference numeral 4 denotes a data input buffer circuit for outputting data from the serial interface bus transmission / reception circuit to the data signal line 1. The output buffer circuit 5 is a clock input buffer circuit for taking the clock signal output to the clock signal line 2 into the serial interface bus transmitting / receiving circuit.

A stop / start condition generating circuit 6 for generating a stop condition and a start condition includes a D flip-flop 6a for detecting a stop condition, a D flip-flop 6b for detecting a start condition, a NOR circuit 6c, a latch circuit 6d, and a D flip-flop. 6e and a D flip-flop 6f. A reset terminal of the start condition detecting D flip-flop 6b is connected to a clock signal supply line (hereinafter, referred to as SCL) through which a clock signal supplied from the master device to the clock signal line 2 is output via the clock input buffer circuit 5. Connected to Also,
A clock signal input terminal of the start condition detecting D flip-flop 6b is connected to a data supply line (hereinafter referred to as SDA) through which data supplied from the master device to the data signal line 1 is output via the data input buffer circuit 3. Is connected to The data terminal of the start condition detecting D flip-flop 6b is connected to the Vcc line. D flip-flop 6 for detecting stop condition
The reset terminal a is connected to the inverted Q # output terminal of the D flip-flop 6b for detecting the start condition. The clock signal input terminal of the stop condition detecting D flip-flop 6a is connected to the SDA. The data terminal of the start condition detecting D flip-flop 6a is connected to the Vcc line.

Each of the input terminals of the NOR circuit 6c has one input terminal connected to the non-inverted Q output terminal of the D flip-flop 6a for detecting a stop condition and the other input terminal connected to the D flip-flop 6b for detecting a start condition. Non-inverted Q
Connected to output terminal. The output terminal of the NOR circuit 6c is connected to the set terminal of the latch circuit 6d and the reset terminal of the D flip-flop 6f.

The non-inverted Q output terminal of the latch circuit 6d is connected to the data terminal of the D flip-flop 6e, the reset terminal is connected to the inverted Q output terminal of the D flip-flop 6f, and the inverted Q output of the latch circuit 6d. A bus free signal (BUS FREE) for initializing the serial interface operation is output from the output terminal.

The clock signal input terminals of the D flip-flops 6e and 6f are connected to the SCL, and the non-inverted Q output terminal of the D flip-flop 6e is connected to the data terminal of the D flip-flop 6f.

[0007] 7 is a control logic unit, 8 is an 8-bit shift register for converting 8-bit data from serial to parallel or parallel-to-serial, 9 is an N-bit counter for holding and outputting a sub address as an internal state, and 10 is an 8-bit shift register An output selection circuit for outputting internal information or acknowledgment output from 8; 11 a delay circuit for adding a delay amount specified by a bus standard to an output of the output selection circuit 10;
Reference numerals 14 and 14 denote an address decoder for decoding a sub-address to which data information is written, 13 an internal register to which data information is written by a decode output of the address decoder 12, and 15 an internal register to which data information is written by a decode output of the address decoder 14. . 16 and 18 are address decoders for decoding sub-addresses for reading internal information, 17 is an information selection element for reading internal information by decode output of the address decoder 16, and 19 is an information decoder for reading internal information by decode output of the address decoder 18. Information selection element.

[0008] The control logic unit 7 comprises: a data output to the SDA via the data input buffer circuit 3; a clock signal output to the SCL via the clock input buffer circuit 5; (4) The bus-free signal output from the output terminal and the data converted by the 8-bit shift register 8 are supplied, and the operation signals PIDSC, SR8T, DATAO
UTEN, ACKOUT, SAEP, SALDC, ST
RBC and LQBOEC are generated and output to each control signal line. PIDSC is an operation signal for loading the read internal information into the 8-bit shift register 8, SR8T is an operation signal for defining the shift timing of the 8-bit shift register 8, and DATAOUTEN is the output of the internal information from the output selection circuit 10. ACKOUT to control the operation signal
Is an operation signal for controlling the output of the acknowledge from the output selection circuit 10, and SAEP is an operation signal for updating the internal state of the N-bit counter 9 by '+1'. SALDC
Is an operation signal for loading the sub-address information into the N-bit counter 9. STRBC is the internal register 1
This is an operation signal for writing data information to 3 and 15. LQBOEC is an operation signal for giving the read internal information to the 8-bit shift register 8.

Next, the operation will be described. FIG. 7 is a timing chart showing the operation of the serial interface bus transmitting / receiving circuit. First, by detecting the rising edge of the data on SDA when the clock signal level on SCL is at “H” level, the D flip-flop 6
a detects a stop condition. D flip-flop 6a
Is output to a set terminal of a latch circuit 6d and a reset terminal of a D flip-flop 6f via a NOR circuit 6c. As a result, the latch circuit 6d is set and the latch circuit 6d is set.
The bus-free signal, which is the inverted Q # output, becomes significant, and the operation of the control logic unit 7 is initialized. Subsequently, the D flip-flop 6b detects the start condition by detecting the falling edge of the data on SDA when the clock signal level on SCL is at "H" level. The output from the inverted Q # output terminal of the D flip-flop 6b resets the D flip-flop 6a and cancels the stop condition detection output output from the D flip-flop 6a. The start condition detection output from the non-inverting Q output terminal of the D flip-flop 6b is applied to the set terminal of the latch circuit 6d and the reset terminal of the D flip-flop 6f via the NOR circuit 6c, and the latch circuit 6d maintains the set state. , The control logic unit 7 continues the initialization.

Next, a serial transfer operation is started,
A negative clock signal is supplied from the master device to the SCL. As a result, the D flip-flop 6b is reset by the first "L" level of the clock signal, and the start condition detection output output from the non-inverted Q output terminal of the D flip-flop 6b disappears. In this state, the latch circuit 6d maintains the set state, and the bus free signal is significant.

The non-inverted Q output of the latch circuit 6c is transmitted to the D flip-flop 6e by the falling edge of the first clock signal, and the latch circuit transmitted to the D flip-flop 6e by the rising edge of the first clock signal. 6c is transmitted to the D flip-flop 6f, and as a result, the D flip-flop 6f
The latch circuit 6c shifts from the set state to the reset state by the inverted Q # output of f. At this point, the bus free signal becomes insignificant, and the control logic unit 7 starts operating.

When the control logic unit 7 has started operation, first, device address information is sent from the master device to the SDA. This device address information is input to the 8-bit shift register 8. The 8-bit shift register 8 controls the operation signal SR output from the control logic unit 7.
8T, the device address information 8
At the end of the bit transfer, the device address information is output to line LDB <7: 0>. This line LDB
If the device address information output to <7: 0> matches the device address of the serial interface bus transmission / reception circuit, the control logic unit 7 outputs the operation signal A
At the same time as making CKOUT significant, the output selection circuit 10 is controlled by the operation signal DATAOUTEN to output an acknowledge signal from the output selection circuit 10. As a result, an “L” level acknowledge signal is output to the data signal line 1. On the other hand, if they do not match, the control logic unit 7 stops the internal operation without making the operation signal ACKOUT significant. In the acknowledgment period, the master device monitors the acknowledgment of the slave by opening the data signal line 1.

If the device address information matches the device address of the serial interface bus transmission / reception circuit, an "L" level acknowledge signal is output and the LSB of the device address is "L" level, the data An information writing sequence is started. In this sequence, the sub address information is sent from the master device via the data signal line 1. When the 8-bit transfer of the sub-address information is completed, the 8-bit shift register 8 stores the sub-address information in the line LD.
B <7: 0>.

The control logic unit 7 outputs an acknowledge signal to the output of the output selection circuit 10 by controlling the operation signal DATAOUTEN while making the operation signal ACKOUT significant. At this time, the value of the sub-address information output to the line LDB <7: 0> is simultaneously loaded into the N-bit counter 9 by the operation signal SALDC output from the control logic unit 7 and output to the line LAB <N-1: 0>. Update the sub-atres information. Next, the write data information sent from the master device is input, and at the end of the 8-bit transfer, the 8-bit shift register 8 outputs the write data information to the line LDB <7: 0>. The control logic unit 7 makes the operation signal ACKOUT significant and outputs an acknowledgment signal of 'L' level to the data signal line 1 and at the same time makes the operation signal STRBC for writing data information to the internal register significant. As a result, in the address decoders 12 and 14, the line LAB <N-1:
0> stores the write data on the line LDB <7: 0> in the internal register 13 or the internal register 15 during the significant period of the operation signal STRBC.

Thereafter, the write data information continues to be 8
Every time a bit is input, the operation signal SAEP output from the control logic unit 7 causes the content of the N-bit counter 9 to be "+1".
Be updated. Then, the sub address on the line LAB <N-1: 0> is updated, and the operation of updating the write data to the internal register is repeated. The write data update operation ends when the STOP condition is detected or the START condition is detected again.

When an acknowledgment signal of "L" level is output for the device address information and the LSB of the device address is at "H" level, a data information read sequence is started. Immediately after outputting the "L" level acknowledge signal, the address decoder 16,
Only the address decoder corresponding to the sub-address output on line LAB <N-1: 0> among 18 outputs read data on line LQB <7: 0> during the significant period of operation signal LQBOEC. . Operation signal LQBO
The control logic unit 7 at the timing when the significant period of EC sufficiently covers
The read data on the line LQB <7: 0> is loaded into the 8-bit shift register 8 by the operation signal PIDSC generated and output by the above. SCL to be input
The operation signal SR8 output from the control logic unit 7 with the same timing as the rising edge of the upper clock signal
According to T, the 8-bit shift register 8 converts the read data into serial data and outputs it to the output selection circuit 10.
In response to the operation signal DATAOUTEN output from the control logic unit 7, the output selection circuit 10 outputs the read data converted to the serial data. Note that the read data output from the output selection circuit 10 is
1 is delayed by the bus standard and output to the data signal line 1.

After the 8-bit output, the master device
When the above data is operated by “L”, the internal state of the N-bit counter 9 is updated by “+1” by the operation signal SAEP output from the control logic unit 7, and the line LAB <N−
1: 0>, and the read data output operation is repeated. Master device outputs S after 8 bits output
When the data on DA is being operated by “H”, the internal operation is stopped in a state where the data signal line 1 is released.

In order to transfer information to and from the master device using the serial interface bus transmission / reception circuit as a slave, data on the SDA when the signal level on the SCL is at the "H" level is "H" level. From the “L” level to the “L” level, the master device generates a start condition, and the data on the SDA when the signal level on the SCL is the “H” level changes from the “L” level to the “H” level. This causes the master device to generate a stop condition. When the signal level on the SCL is “H” level, the state of the data on the SDA must be constant,
State change is allowed only at the "L" level. Further, in order to satisfy these definitions, an SDA signal hold time of at least 300 nsec in which data on the SDA must not change starting from the change of the signal level on the SCL from the “H” level to the “L” level is provided. And other timing constraints.

[0019]

Since the conventional serial interface bus transmission / reception circuit is configured as described above, the timing constraint condition that the SDA signal hold time is provided among a plurality of slaves connected to the master device. If there is a serial interface bus transmitting / receiving circuit that does not satisfy
There has been a problem that the data on A and the clock signal on SCL may change simultaneously and the possibility of malfunction may increase.

The cause of such a malfunction is that, when a plurality of slaves are connected to the bus, the resistance value and the parasitic capacitance of the bus line and the input capacitance of the slave connected to the bus are changed at each slave input terminal. This is because, in order to vary the amount of propagation delay between the signal on the SDA and the signal on the SCL, data on the SDA to another slave and the clock signal on the SCL may change simultaneously. This malfunction will be further described. When the slave causing the malfunction performs an acknowledgment or data read / output operation, the other slaves detect the start condition and stop condition of the communication, and the subsequent information on the SDA is transmitted to the master device. In the transfer cycle managed as data, the other slave receives the address as an address, and when the received address matches the device address of the other slave, the slave starts a transmission / reception operation. Such a malfunction is dealt with by adding a delay element at the SDA input terminal of the slave that caused the malfunction. However, such an erroneous reaction is difficult to detect early because it is related to the variety of functions of the target slave and the change in the electrical environment of the bus. When testing the serial interface function of a product incorporating such a serial interface bus transmission / reception circuit, high-speed stable operation beyond that specified by the bus standard is desired to reduce the test time. In such a high-speed operation, there is a problem that it is desired that the input phase management of the SDA input terminal and the SCL input terminal does not depend on the operation accuracy of the tester, and that it is easy to set timing constraint conditions.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and does not satisfy the timing constraint condition which causes a malfunction of another slave among a plurality of slaves connected to a master device. Even if there is something,
An object of the present invention is to provide a serial interface bus transmission / reception circuit which is hardly affected by a malfunction and has improved resistance to a malfunction.

It is another object of the present invention to provide a serial interface bus transmitting / receiving circuit capable of reducing a test time for testing a serial interface function.

[0023]

According to a first aspect of the present invention, there is provided a serial interface bus transmitting / receiving circuit according to the present invention, wherein the data input from the master device via a data signal line and the master device via the clock signal line. Based on the clock signal input from the CPU, the stop of data transmission / reception to / from the master device and the start of the data transmission / reception are detected to output the detection result, and the data reset by the signal level of the clock signal A condition recognition signal time period for performing a timed operation based on detection results by the transmission / reception stop / start detection means and the data transmission / reception stop / start detection means, and outputting a stop condition recognition signal and a start condition recognition signal after a set time has elapsed. Output means;
Initialization instruction signal generation means for generating and outputting an initialization instruction signal for instructing initialization for data transmission / reception based on the output of the condition recognition signal timed output means; and Initialization instruction signal reset means for resetting the initialization instruction signal output by the initialization instruction signal generation means, and initialization for data transmission / reception based on the initialization instruction signal output from the initialization instruction signal generation means. Run,
After the initialization instruction signal is reset by the initialization instruction signal reset means, control means for transmitting and receiving data to and from the master device in synchronization with the clock signal is provided.

According to a second aspect of the present invention, there is provided a serial interface bus transmission / reception circuit which stops the data transmission / reception to / from the master device detected by the output of the condition recognition signal timed output means or the data transmission / reception stop / start detection means. An initialization instruction signal generating means for generating and outputting an initialization instruction signal for instructing initialization for data transmission / reception based on a detection result of start of transmission / reception is provided.

According to a third aspect of the present invention, there is provided a serial interface bus transmitting / receiving circuit for determining a mutual input condition between data input through a data signal line and a clock signal input through a clock signal line. Determination data storage means for storing determination data to be used, mutual input condition determination means for determining the mutual input condition based on the determination data stored in the determination data storage means, and determination by the mutual input condition determination means A judgment result storing means for storing a result, and a judgment result reading means for reading the judgment result stored in the judgment result storing means from a master device are provided.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a circuit diagram showing a configuration of the serial interface bus transmitting / receiving circuit according to the first embodiment. In FIG. 1, reference numeral 1 denotes a data signal line to which data of a serial interface bus is output, and 2 denotes a clock signal line to which a clock signal of the serial interface bus is output. Connected to the master device. Reference numeral 3 denotes a data input buffer circuit for taking in the data output to the data signal line 1 into the serial interface bus transmission / reception circuit, and reference numeral 4 denotes a data input buffer circuit for outputting data from the serial interface bus transmission / reception circuit to the data signal line 1. The output buffer circuit 5 is a clock input buffer circuit for taking the clock signal output to the clock signal line 2 into the serial interface bus transmitting / receiving circuit.

Reference numeral 100 denotes a stop / start condition generating circuit for generating a stop condition and a start condition. The stop condition detection D flip-flop (data transmission / reception stop / start detection means) 6a and the start condition detection D flip-flop (data transmission / reception) are provided. Stop / start detection means) 6b, first
Time measurement circuit (condition recognition signal time output means) 54, second
Time measurement circuit (condition recognition signal time output means) 56, NO
R circuit 6c, latch circuit (initialization instruction signal generation means) 6
d, a D flip-flop (initialization instruction signal resetting means) 6e and a D flip-flop (initialization instruction signal resetting means) 6f. The time value set in the first time measurement circuit 54 and the second time measurement circuit 56 may be a change in data or clock for generating a stop condition and a start condition by the master device, or an acknowledge output of the slave device. The value is set to a value that enables identification of a change in data or clock due to a read data output operation. The reset terminals of the D flip-flop 6a for detecting the stop condition and the D flip-flop 6b for detecting the start condition are connected to the SCL to which the clock signal supplied from the master device to the clock signal line 2 is input via the clock input buffer circuit 5. (Clock signal supply line). The clock signal input terminals of the D flip-flop 6a for detecting the stop condition and the D flip-flop 6b for detecting the start condition are:
The data supplied from the master device to the data signal line 1 is connected to an SDA (data supply line) input via a data input buffer circuit 3. Also,
The data terminals of the D flip-flop 6a for detecting the stop condition and the D flip-flop 6b for detecting the start condition are connected to the Vcc line.

D flip-flop 6 for detecting stop condition
The non-inverted Q output terminal of a is connected to the reset terminal of the first time measurement circuit 54. The non-inverted Q output terminal of the D flip-flop 6b for detecting a start condition is connected to the reset terminal of the second time measuring circuit 56. Internal clocks are supplied to clock input terminals of the first time measurement circuit 54 and the second time measurement circuit 56. One input terminal of the NOR circuit 6c is connected to the FL of the first time measurement circuit 54.
The other input terminal is connected to the FLAG output terminal of the second time measuring circuit 56.
The FLAG output terminal of the second time measurement circuit 56 is connected to the second reset terminal (R_FLA) of the first time measurement circuit 54.
G). The output terminal of the NOR circuit 6c is connected to the set terminal of the latch circuit 6d and the D flip-flop 6.
f is connected to the reset terminal.

The non-inverted Q output terminal of the latch circuit 6d is connected to the data terminal of the D flip-flop 6e, the reset terminal is connected to the inverted Q output terminal of the D flip-flop 6f, and the inverted Q output of the latch circuit 6d. A bus free signal (BUS FREE) for initializing the serial interface operation is output from the output terminal.

The clock signal input terminals of the D flip-flops 6e and 6f are connected to the SCL, and the non-inverted Q output terminal of the D flip-flop 6e is connected to the data terminal of the D flip-flop 6f.

7 is a control logic unit (control means), 8 is an 8-bit shift register that converts 8-bit data into serial-parallel or parallel-serial, 9 is an N-bit counter that holds and outputs a subaddress as an internal state, and 10 is An output selection circuit for outputting internal data or acknowledgment output from the 8-bit shift register 8; 11, a delay circuit for adding a delay amount specified by the bus standard to the output of the output selection circuit 10; An address decoder 13 decodes a sub-address to which information is written, 13 is an internal register to which data information is written by a decode output of the address decoder 12, and 15 is an internal register to which data information is written by a decode output of the address decoder 14. 16 and 18 are address decoders for decoding sub-addresses for reading internal data, 17 is an information selection element for reading internal data based on the decoded output of the address decoder 16, and 19 is an information decoder for reading internal data based on the decoded output of the address decoder 18. Information selection element.

The control logic unit 7 is configured to control the data input to the SDA via the data input buffer circuit 3, the clock signal input to the SCL via the clock input buffer circuit 5, and the inverted Q of the latch circuit 6d. (4) The bus-free signal output from the output terminal and the data converted by the 8-bit shift register 8 are supplied, and the operation signals PIDSC, SR8T, DATAO
UTEN, ACKOUT, SAEP, SALDC, ST
RBC and LQBOEC are generated and output to each control signal line. PIDSC is an operation signal for loading the read internal information into the 8-bit shift register 8, SR8T is an operation signal for defining the shift timing of the 8-bit shift register 8, and DATAOUTEN is the output of the internal information from the output selection circuit 10. ACKOUT to control the operation signal
Is an operation signal for controlling the output of the acknowledge from the output selection circuit 10, and SAEP is an operation signal for updating the internal state of the N-bit counter 9 by '+1'. SALDC
Is an operation signal for loading the sub-address information into the N-bit counter 9. STRBC is the internal register 1
This is an operation signal for writing data information to 3 and 15. LQBOEC is an operation signal for giving the read internal information to the 8-bit shift register 8.

D flip-flop 6 for detecting stop condition
a and D flip-flop 6b for detecting start condition
Is made insignificant when the level of the clock signal on the SCL is 'L' level. The stop condition detecting D flip-flop 6a detects a rising edge of data supplied to the SDA when the level of the clock signal on the SCL is at the “H” level, and outputs the signal from the non-inverted Q output terminal. STOP condition is significant. The start condition detecting D flip-flop 6b detects the falling edge of the data supplied to the SDA when the level of the clock signal on the SCL is at the “H” level, and outputs the signal from the non-inverted Q output terminal. The SART condition which is the output of is made significant.

When the STOP condition or the START condition is satisfied, the first time measuring circuit 54 and the second time measuring circuit 56
Starts operation, and when a predetermined time period is reached, a signal WDT_STO from the FLAG output terminal of the first time measurement circuit 54 is output.
P, the signal WDTSTART from the FLAG output terminal of the second time measurement circuit 56 becomes significant. If the STOP condition output from the non-inverted Q output terminal of the D flip-flop 6a for detecting a stop condition is insignificant, the first time measurement circuit 5
The time measurement function of No. 4 is initialized. However, the signal WDT_
The initialization of the STOP output function is performed by the signal WDT_STAR.
Implemented by the transition edge from T insignificant to significant.
If the START condition is insignificant, the second time measurement circuit 56
The time measurement function and the output function of the signal WDT_START are both initialized. These signals WDT_STOP, WD
The output of the NOR circuit 6c becomes significant by T_START, and the latch circuit 6d is set. The output from the inverted Q # output terminal of the latch circuit 6d initializes the serial interface operation as a bus-free signal.

The output from the non-inverted Q output terminal of the latch circuit 6d is taken into the D flip-flop 6e at the falling edge of the negative clock signal on the SCL and output from the non-inverted Q output terminal. Propagate to the D flip-flop 6f at the next rising edge of the active clock signal. The output from the inverted Q # output terminal of the D flip-flop 6f resets the latch circuit 6d and terminates the bus free signal output from the latch circuit 6d. As a result, the serial interface operation starts.
In the D flip-flop 6f, the insignificance of the bus-free signal propagates from the latch circuit 6d and becomes insignificant, or is made insignificant by the output of the NOR circuit 6c. The serial signal of the data supplied to the SDA is serial-parallel converted to an 8-bit parallel signal by an 8-bit shift register 8, and
Output to DB <7: 0>. Thus LDB <7:
0> is output to the internal register 1
At the timing with the contents of the sub-addresses 3 and 15, the internal register 1 is loaded into the N-bit counter 9 and
3 and 15 are stored as LAB <N-
1: 0>. The subaddress output to LAB <N-1: 0> is stored in the internal registers 13 and 15.
It is used for register selection designation for selecting the internal registers 13 and 15 when writing data information to be used internally for writing, or for internal information selection designation when reading internal data to the outside.

Next, the operation of the serial interface bus transmitting / receiving circuit will be described. In the description of the operation of the serial interface bus transmitting / receiving circuit, reference is made to the timing chart shown in FIG. When the level of the clock signal on the SCL is at the “H” level, the rising edge of the data supplied to the SDA is detected, and the stop condition detecting D flip-flop 6a detects the STOP condition. When this STOP condition is detected, the output of the non-inverted Q output terminal of the D flip-flop 6a for detecting the stop condition changes to "H" level, and a signal output from the first time measuring circuit 54 after a predetermined time from this timing. W
DT_STOP becomes significant. As a result, the NOR circuit 6
The output of c sets the latch circuit 6d, and the inverted Q #
The bus free signal output from the output terminal becomes significant, and the operation of the control logic unit 7 is initialized.

Subsequently, the falling edge of the data supplied to the SDA when the level of the clock signal on the SCL is at the "H" level is detected, and the start condition detection signal D is detected.
The flip-flop 6b detects a START condition. When this START condition is detected, the output of the non-inverted Q output terminal of the D flip-flop 6b for detecting the start condition becomes "H".
Level, and the signal WDT_ output from the second time measuring circuit 56 after a predetermined time from this timing.
START is significant. As a result, the latch circuit 6d is set again by the output of the NOR circuit 6c. Signal W
When DT_START becomes significant, the first time measurement circuit 5
4 is initialized, and the significant signal WDT_STOP, which is the output of the first time measurement circuit 54, becomes insignificant. At this time, the bus free signal continues to initialize the operation of the control logic unit 7.

Then, a serial transfer operation is started, and S
A negative clock is input to CL. By the first negative polarity clock input to the first SCL, the stop condition detecting D flip-flop 6a and the start condition detecting D flip-flop 6b are reset and initialized, and the STOP condition and the START condition disappear. . When the STOP condition disappears and the level of the non-inverted Q output terminal of the D flip-flop 6a for detecting the stop condition becomes “L” level, the time measurement function of the first time measurement circuit 54 is initialized. Also, the START condition disappears and the non-inverted Q of the D flip-flop 6b for detecting the start condition is turned off.
When the level of the output terminal becomes “L” level, the time measurement function and the output function of the second time measurement circuit 56 are initialized, and the signal WDT_START becomes insignificant. SCL
At the first falling edge of the clock signal input upward, the significant state of the latch circuit 6d outputting the bus-free signal propagates to the D flip-flop 6e, and further at the next rising edge of the clock signal, To the flip-flop 6f.
The latch circuit 6c is reset by the output from the output terminal, the bus free signal becomes insignificant, and the control logic unit 7 starts operating at this time.

The device address information is first input from the master device, and the 8-bit shift register 8 driven by the operation signal SR8T output from the control logic unit 7
At the end of the 8-bit transfer, device address information is output to LDB <7: 0>. If the device address information output to LDB <7: 0> at this time matches the device address of the serial interface bus transmitting / receiving circuit, the control logic unit 7 operates the operation signal ACKOU.
At the same time as making T significant, the output selection circuit 10 is controlled by the operation signal DATAOUTEN, and an acknowledge is output to the output of the output selection circuit 10. As a result, the data signal line 1
ACK signal of 'L' level is output. On the other hand, if the device address information does not match the device address of the serial interface bus transmitting / receiving circuit, the control logic unit 7 does not make the operation signal ACKOUT significant and stops the internal operation. In the acknowledgment period, the master device monitors the acknowledgment signal output from the slave by releasing the data signal line 1.

When the acknowledgment signal at the "L" level is output and the LSB of the device address is "L", the data information write sequence starts. Sub address information is input to the data signal line 1 from the master device.
The bit shift register 8 stores the sub address information in LD
B <7: 0>. The control logic unit 7 operates the operation signal AC.
At the same time as making KOUT significant, the operation signal DATAOUT
The output selection circuit 10 is controlled by EN and the output selection circuit 10
An acknowledgment signal is output to the output of. At this time, the operation signal SALDC output from the control logic unit 7 simultaneously causes LD
B <7: 0> is loaded into the N-bit counter 9 with the value of the sub-address information, and LAB <N−1:
0> The sub address information that has been output upward is updated.

Next, write data information is input.
This write data information is stored at the end of the 8-bit transfer.
The data is output from the bit shift register 8 to LDB <7: 0>. The control logic unit 7 makes the operation signal ACKOUT significant and outputs an acknowledgment of “L” level to the data signal line 1, and at the same time, an operation signal (strobe signal) STRB for writing data information to the internal registers 13 and 15.
Make C significant. In the address decoders 12 and 14,
Only the address decoder corresponding to the sub address information output to LAB <N-1: 0> is operated by the operation signal ST.
A strobe signal is generated during the significant period of RBC, and LDB is generated.
The write data on <7: 0> is stored in the internal register 13 or the internal register 15.

Thereafter, the write data information continues to be 8
Every time a bit is input, the content of the N-bit counter 9 is updated by +1 by the operation signal SAEP output from the control logic unit 7. Then, the subaddress specified by the subaddress information output to LAB <N-1: 0> is updated, and the operation of updating the write data to the internal register is repeated.
Note that the write data update operation is completed by detecting the STOP condition or the re-start condition.

In the case where an acknowledgment signal for the device address information is output and the LSB of the device address is "H", the internal data read sequence starts. Immediately after outputting the acknowledgment signal at the “L” level, only the address decoder 16 or the address decoder 18 corresponding to the subaddress specified by the subaddress information output to LAB <N−1: 0> receives the operation signal (information selection). Period signal) The internal data is output on LQB <7: 0> during the significant period of LQBOEC. An operation signal P output from the control logic unit 7 generated at a timing at which the significant period of the operation signal LQBOEC sufficiently covers the operation signal P
The value of the internal data read into LQB <7: 0> is loaded into the 8-bit shift register 8 by the IDSC. For each operation signal SR8T output from the control logic unit 7 at the same timing as the rising edge of the clock signal input to the SCL, the 8-bit shift register 8 converts the internal data from parallel to serial, The output selection circuit 10 outputs the parallel-to-serial converted internal data in response to the operation signal DATAOUTEN output by. The output of the output selection circuit 10 is delayed by the delay circuit 11 according to the bus standard and is output to the data signal line 1.

After 8-bit output, the master device
When the upper signal level is operated by “L”, the internal state of the N-bit counter 9 is updated by “+1” by the operation signal SAEP output from the control logic unit 7 and LAB <N−1:
0> is updated, and the internal data output operation is repeated. When the master device operates the signal level on the SDA to “H” after outputting 8 bits, the internal operation is stopped while the data signal line 1 is released.

FIG. 2 shows the relationship between data input on SDA and S
9 is a timing chart showing a situation in which a conventional serial interface bus transmission / reception circuit in which a clock signal input to a CL simultaneously changes causes a malfunction. As shown in this timing chart, even if the clock signal on SCL and the data on SDA change simultaneously,
Both the stop condition detecting D flip-flop 6a and the start condition detecting D flip-flop 6b are reset by the "L" level of the upper clock signal, and the second time measurement circuit 56 is reset by the "L" level of the clock signal. Is done. For this reason, even if the stop condition is detected by the stop condition detecting D flip-flop 6a at the time when the clock signal on the SCL and the data on the SDA change simultaneously, the "L" level of the clock signal immediately follows the stop condition. The stop condition disappears, and the malfunction as shown in FIG. 8 can be prevented.

As described above, according to the first embodiment, the first time period measuring circuit 54 and the second time period measuring circuit 56
The time limit value set in (1) is used to identify whether the stop condition and start condition are data and a clock for the master device to generate, or whether the data is a clock or data from the acknowledgment output or read data output operation of the slave device. The signal for setting the latch circuit 6c for generating the bus-free signal is set to a value enabling the WDT_ST output from the first time measurement circuit 54.
OP and WDT_S output by the second time measurement circuit 56
TART. Data input on SDA and SCL
Under a situation where the conventional serial interface bus transmission / reception circuit in which the clock signal inputted thereto changes simultaneously, malfunctions, the non-inversion of the D flip-flop 6a for detecting the stop condition and the D flip-flop 6b for detecting the start condition is performed. An “H” level signal is output from the Q output for a short time. However, in the serial interface bus transmitting / receiving circuit of this embodiment, a time value that is sufficiently longer than the signal output period of the “H” level is set in the first time measurement circuit 54 and the second time measurement circuit 56. Therefore, the time corresponding to the time limit elapses and W
Before the output of DT_STOP or WDT_START, the signal of the “H” level disappears, and the D flip-flop 6a for detecting the stop condition, the D flip-flop 6b for detecting the start condition, and the first time measurement circuit 5
The fourth and second time measurement circuits 56 are reset by the clock signal level “L” on the SCL.

Therefore, among the plurality of slaves connected to the master device, there are some slaves that do not satisfy the timing constraint conditions that cause malfunction of the other slaves. The data input to the SDA and the data input to the SCL are not satisfied. A conventional serial interface bus transmission / reception circuit in which a clock signal changes simultaneously has the effect of providing a serial interface bus transmission / reception circuit that is less susceptible to a malfunction and has improved immunity to a malfunction. .

Embodiment 2 FIG. 3 shows the second embodiment.
3 is a circuit diagram showing a serial interface bus transmission / reception circuit. In FIG. 3, the same or corresponding parts as those in FIG. In the figure,
Reference numeral 200 denotes a stop / start condition generating circuit for generating a stop condition and a start condition, and 58 denotes a D flip-flop to which a set terminal and a reset terminal for outputting a bus free signal from an inverted Q # output terminal (initialization instruction signal generating means) ) And 59 indicate that both the stop condition which is the output of the non-inverted Q output terminal of the D flip-flop 6a for detecting the stop condition and the start condition which is the output of the non-inverted Q output terminal of the D flip-flop 6b for detecting the start condition are significant. Is an AND circuit which outputs an AND result of the output of the NOR circuit 6c and the output of the NAND circuit 59 as a reset signal for resetting the D flip-flop 6f. The configuration of the stop
This is the same as the start condition generation circuit 100.

Since the only difference between the operation of the second embodiment and the operation of the first embodiment is the difference in the operation of the stop / start condition generation circuit 200, the operation of the stop / start condition generation circuit 200 will be described. I do. In this stop / start condition generation circuit 200,
SD when the level of the clock signal on SCL is 'H'
A rising edge of the data supplied on A is detected,
Stop condition detection D flip-flop 6a is STOP
The condition detection output is output from the non-inverting Q output terminal. The non-inverted Q output terminal of the D flip-flop 6a for detecting the stop condition changes to "H", and the STOP condition is detected.
When the P condition detection output is output from the non-inverting Q output terminal, the first time measurement circuit 54 outputs the output signal W after a predetermined time.
Make DT_STOP significant. As a result, the NOR circuit 6
The D flip-flop 58 is set by the output of c, the bus free signal becomes significant, and the operation of the control logic unit 7 is initialized.

Subsequently, the start condition detecting D flip-flop 6b detects the falling edge of the data output to SDA when the level of the clock signal on SCL is "H", and outputs the TART condition detection output. Output from the non-inverted Q output terminal. The non-inverted Q output terminal of the start condition detecting D flip-flop 6b changes to "H" and ST
When an ART condition is detected and a START condition detection output is output from the non-inverting Q output terminal, the second time measurement circuit 56 makes the output signal WDT_START significant after a predetermined time period from when the START condition detection output is output. . Then, the output of the NOR circuit 6c is made significant, and the D flip-flop 58 is set again. Output signal WDT_ST
When the ART becomes significant, the output of the first time measuring circuit 54 is initialized by this changing edge, and the first time measuring circuit 5
The output signal WDT_STOP of No. 4 becomes insignificant. At this time, the bus free signal continues to initialize the operation of the control logic unit 7.

The serial transfer operation is started, and a negative polarity clock is input on SCL. The "L" of the first input negative polarity clock causes the D flip-flop 6a for detecting the stop condition and the D flip-flop 6b for detecting the start condition to be initialized.
The T condition disappears. When the STOP condition disappears and becomes “L”, the time measurement function of the first time measurement circuit 54 is initialized. When the START condition disappears and becomes “L”, the measurement function and the output function of the second time measurement circuit 56 are initialized, and the output signal WDT_ of the second time measurement circuit 56 is output.
START becomes non-significant.

At the first falling edge of the clock signal on the SCL, the significant state of the D flip-flop 58 generating the bus-free signal changes to the D flip-flop 6.
e at the next rising edge of the clock signal.
The state of the flip-flop 6e is the D flip-flop 6f
And the inverted Q # output of the D flip-flop 6f
The flip-flop 58 is reset. The bus free signal becomes insignificant at this point, and the control logic unit 7 starts operating.

Next, the circuit operation based on the bus operation specification at the time of the test will be described. The rising edge of the data on SDA when the level of the clock signal on SCL is "H" is detected, and the D flip-flop 6a for detecting the stop condition detects the STOP condition. As a result, if the falling edge of the data on the SDA when the clock signal on the SCL is “H” is detected during the time measurement by the first time measurement circuit 54, the D flip-flop 6 b for detecting the start condition is detected. Detects the START condition and sets the non-inverted Q output to the “H” level. At the rising edge to the “H” level, the D flip-flop 58 samples the STOP condition supplied to the data terminal, makes the bus free signal significant, and initializes the operation of the control logic unit 7.

A serial transfer operation is started, and a negative clock is input to SCL. The start condition detection D is determined by the first "L" of the negative polarity clock input to the SCL.
The flip-flop 6b is initialized and the START condition disappears, and the START condition disappears and becomes “L”, whereby the second time measurement circuit 56 is also initialized and the signal WDT_ST
ART continues to be insignificant. Further, the D flip-flop 58 maintains the output of the bus free signal. The significant state of the D flip-flop 58 propagates to the D flip-flop 6f at the first falling edge of the negative polarity clock on the SCL and further at the next rising edge, and the inverted Q # output of the D flip-flop 6f causes the D flip-flop 58 to output. Reset. The bus free signal becomes insignificant at this point, and the control logic unit 7 starts operating.

In the bus operation specification at the time of the test, the first
The serial transfer operation is started during the time measurement of both the time measurement circuit 54 and the second time measurement circuit 56. During this test, the stop condition detecting D flip-flop 6a
The OP condition is detected, and the non-inverted Q output is changed to the “H” level. Next, the D flip-flop 6b for detecting the stop condition detects the START condition, and outputs the non-inverted Q output to “H”.
Level, this rising edge causes D
The flip-flop 58 reads the "H" level non-inverted Q output of the stop condition detecting D flip-flop 6a supplied to the data terminal and outputs a bus-free signal. In the first embodiment, after the first time measurement circuit 54 makes the signal WDT_STOP significant, the second time measurement circuit 56 can start the serial transfer operation after a time that makes WDT_START significant. In the serial interface bus transmitting / receiving circuit of the second embodiment, D flip-flop 6a for detecting a stop condition
After detecting the OP condition and changing the non-inverted Q output to the “H” level, the stop condition detecting D flip-flop 6 b
Detects the START condition, the first time measurement circuit 54
The serial transfer operation can be started without waiting for the timed operation of the second timed measurement circuit 56.

As described above, according to the second embodiment, in addition to the effect of the first embodiment, a test can be performed without waiting for the timed operation of the first time measurement circuit 54 and the second time measurement circuit 56. Since it can be started, there is an effect that a serial interface bus transmission / reception circuit that can reduce the test time can be obtained.

Embodiment 3 FIG. 4 shows the third embodiment.
5 is a circuit diagram showing the serial interface bus transmitting / receiving circuit of FIG. 4. In FIG. 4, the same or corresponding parts as those in FIG. The serial interface bus transmission / reception circuit of the third embodiment is different from the first embodiment in that the STOP condition or the START
First time measurement circuit 5 whose operation is started when the condition is satisfied
The fourth time period measuring circuit 56 and the third time period measuring circuit (mutual input condition determining means) 70 capable of measuring the first time period and the second time period (first time period> second time period). The measurement circuit (mutual input condition determination means) 72 is replaced with the measurement result of the second time period of the third time measurement circuit 70 and the fourth time measurement circuit 72 as a bus status to the flag register (judgment result storage means) 74. The master device outputs a flag, and the master device reads the flag set in the flag register 74 by serial interface communication, so that a mutual input delay condition between data and clock can be determined in an actual operation state. In this case, the second time limit value is a value set in the internal register (determination data storage means) 13 from the master device.

In FIG. 4, reference numeral 300 denotes a stop / start condition generation circuit for generating a stop condition and a start condition, and reference numeral 70 denotes a third time period capable of measuring a first time period and a second time period.
A time measurement circuit, 72 is a fourth time measurement circuit capable of measuring the first time period and the second time period, and 74 is a bus status flag based on the operation signal LQBOEC output from the control logic unit (judgment result reading means) 7. This is a flag register for outputting to LDB <7: 0>. The other configuration of the stop / start condition generation circuit 300 is the same as that of the stop / start condition generation circuit 100 of the first embodiment.

Next, the operation will be described. The operation of the serial interface bus transmission / reception circuit of the third embodiment is substantially the same as the operation of the serial interface bus transmission / reception circuit of the first embodiment, except that in addition to the operation of the first embodiment, the third time measurement circuit Each of the second time measurement results from 70 and the fourth time measurement circuit 72 is set in the flag register 74 as a bus status. This flag register 74 is reset after the status reading operation of the bus of the master device.

The second time limit value sent from the master device is stored in the internal register 13. The second time value stored in the internal register 13 is set in the third time measurement circuit 70 and the fourth time measurement circuit 72, and the reset of the third time measurement circuit 70 and the fourth time measurement circuit 72 is released. After that, the time until the time corresponding to the second time value when the FLAG 2 is set to the third time measurement circuit 70 or the fourth time measurement circuit 72 elapses is defined. In a situation where the data and the clock signal which do not satisfy the mutual input delay condition between the data on the SDA and the clock signal on the SCL change simultaneously, the D flip-flop 6a for detecting the stop condition and the D flip-flop for detecting the start condition are used. From the non-inverted Q output of 6b, a signal of the "H" level may be outputted for a short period as a stop condition detection output and a start condition detection output. 'H' that may be output for a short time
The signal of the level releases the reset of the third time measuring circuit 70 and the fourth time measuring circuit 72. When such a short-time reset is released, as described in the first embodiment, the third time measuring circuit 70 and the fourth time measuring circuit 72 release the third signal. Time measurement circuit 70 and fourth time measurement circuit 72
Does not output the signals WDT_STOP and WDT_START, the latch circuit 6d does not make the bus-free signal significant.

However, the third time measuring circuit 70 and the fourth
The second time value set in the time measurement circuit 72 is output as the “H” level for a short period from the non-inverted Q output terminal of the D flip-flop 6a for detecting the stop condition or the D flip-flop 6b for detecting the start condition. During the signal output period, the FLAG2 terminal of the third time measuring circuit 70 or the fourth time measuring circuit 72 outputs the non-inverted Q of the stop condition detecting D flip-flop 6a or the start condition detecting D flip-flop 6b. At the timing when the output terminal changes from the “H” level to the “L” level, the “H” pulse FLAG2 is output, and the flag register 74 is set to the “H” level. Further, the second time limit value is the non-inverted Q of the stop condition detecting D flip-flop 6a and the start condition detecting D flip-flop 6b.
After the output period of the signal output as the "H" level from the output terminal for a short period, the stop condition detection D flip-flop 6a is output from the FLAG2 terminal of the third time measurement circuit 70 or the fourth time measurement circuit 72. At the timing when the H level changes from the “H” level to the “L” level from the non-inverting Q output terminal of the start condition detecting D flip-flop 6b, the “H” pulse-shaped FLAG 2 is not output, and the flag is also output to the flag register 74. It is not set. SDA
When a signal that satisfies the mutual input delay condition between the above data and the clock signal on the SCL is input, the non-inverted Q output terminals of the D flip-flop 6a for detecting the stop condition and the D flip-flop 6b for detecting the start condition are input. The period “H” that satisfies the first time limit as well as the second time limit as the stop condition detection output and the start condition detection output
A level signal is output. In this case, since the first time limit value has elapsed, WDT_STOP, WDT_S
The timing at which TART changes to “L” level from the “H” level from the non-inverted Q output terminal of the D flip-flop 6a for detecting the stop condition or the D flip-flop 6b for detecting the start condition when the TART becomes “H” level. In this case, the operation of outputting the FLAG2 in the form of an “H” pulse is not performed. Therefore, by operating the second time limit value to be gradually shortened, it is possible to determine in the actual operation state that the data and the clock signal that do not satisfy the mutual input delay condition change simultaneously.

In the third embodiment, only the second time value for the STOP condition and the second time value for the START condition can be commonly variably set. However, both the first time period and the second time period can be variably set. The configuration, and further, the time limit for the STOP condition and the time limit for the START condition may be independently and variably set.

As described above, according to the third embodiment, in addition to the effect of the first embodiment, the data on SDA and the clock signal on SCL which do not satisfy the mutual input delay condition change simultaneously. Thus, there is an effect that a serial interface bus transmitting / receiving circuit that can determine a situation in an actual operation state is obtained.

Embodiment 4 FIG. 5 shows the fourth embodiment.
5 is a circuit diagram showing a serial interface bus transmission / reception circuit. In FIG. 5, the same or corresponding parts as those in FIGS. 3 and 4 are denoted by the same reference numerals and description thereof is omitted. The serial interface bus transmitting / receiving circuit according to the fourth embodiment has a configuration in which both the features of the serial interface bus transmitting / receiving circuit described in the second embodiment and the serial interface bus transmitting / receiving circuit described in the third embodiment are used. A start condition generation circuit is provided.
In FIG. 5, reference numeral 400 denotes a stop / start condition generation circuit.

The operation of the serial interface bus transmission / reception circuit of the fourth embodiment is such that the third time measurement circuit 70 and the fourth time measurement circuit 72 both start the serial transfer operation during the time measurement in the bus operation specification at the time of the test. Therefore, the third time measurement circuit 70 and the fourth time measurement circuit 72 output the signal WDT.
The operation of the second embodiment in which the serial transfer operation can be started without the time for making _STOP and WDT_START significant, and the situation in which the data and the clock signal that do not satisfy the mutual input delay condition change simultaneously are described in the actual operating state. And the operation of the third embodiment can be determined.

Therefore, the fourth embodiment has an effect of obtaining a serial interface bus transmission / reception circuit realizing the effects of the second embodiment and the third embodiment.

[0067]

As described above, according to the first aspect of the present invention, the data input from the master device via the data signal line and the clock signal input from the master device via the clock signal line are used. Data transmission / reception stop / start detecting means for detecting the stop of data transmission / reception with the master device and the start of the data transmission / reception and outputting the detection result, and resetting by the signal level of the clock signal And a condition recognition signal timed output means for performing a timed operation based on the detection result by the data transmission / reception stop / start detection means and outputting a stop condition recognition signal and a start condition recognition signal after a set time has elapsed. The data input via the data signal line and the clock signal input via the clock signal line Even in a situation where the mutual input condition is not satisfied, that is, even when both signals change simultaneously, the stop condition recognition signal and the start condition recognition signal are output from the condition recognition signal timed output means. However, it is possible to improve the resistance to a malfunction that does not cause a malfunction and is not easily affected by the malfunction.

According to the second aspect of the present invention, the output of the condition recognition signal timed output means or the stop of data transmission / reception with the master device detected by the data transmission / reception stop / start detection means and the detection of the start of the data transmission / reception are detected. Based on the result, an initialization instruction signal generating means for generating and outputting an initialization instruction signal for instructing initialization for data transmission / reception is provided, so that the initialization is performed without passing through the condition recognition signal timed output means. Thus, it is possible to generate and output a conversion instruction signal, which has the effect of shortening the test time when testing the serial interface function.

According to the third aspect of the present invention, the determination data used for determining the mutual input condition between the data input through the data signal line and the clock signal input through the clock signal line is determined. Determination data storage means for storing, mutual input condition determination means for determining the mutual input condition based on the determination data stored in the determination data storage means, and determination for storing a determination result by the mutual input condition determination means Since the apparatus is provided with a result storage means and a judgment result reading means for reading the judgment result stored in the judgment result storage means from a master device, the data and the clock signal which do not satisfy the mutual input condition change simultaneously. There is an effect that a situation in which an error occurs can be determined in an actual operation state.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a serial interface bus transmitting / receiving circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing an operation of the stop / start condition generation circuit of the serial interface bus transmission / reception circuit according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a serial interface bus transmitting / receiving circuit according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of a serial interface bus transmitting / receiving circuit according to a third embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a serial interface bus transmitting / receiving circuit according to a fourth embodiment of the present invention.

FIG. 6 is a circuit diagram showing a configuration of a conventional serial interface bus transmitting / receiving circuit.

FIG. 7 is a timing chart showing the operation of the serial interface bus transmitting / receiving circuit.

FIG. 8 is a timing chart showing normal operation and abnormal operation in a stop / start condition generation circuit of a conventional serial interface bus transmission / reception circuit.

[Explanation of symbols]

1 data signal line, 2 clock signal line, 6a D flip-flop for detecting stop condition (data transmission / reception stop / start detection means), 6b D flip-flop for start condition detection (data transmission / reception stop / start detection means), 6d latch circuit ( Initialization instruction signal generation means), 6e, 6f D flip-flop (initialization instruction signal reset means), 7
Control logic unit (control means, judgment result reading means), 13 internal register (judgment data storage means), 54 first time measurement circuit (condition recognition signal time output means), 56 second time measurement circuit (condition recognition signal time output) Means), 58 D flip-flop (initialization instruction signal generating means), 70 third
Time period measuring circuit (mutual input condition judging means), 72 Fourth time measuring circuit (mutual input condition judging means), 74 Flag register (judgment result storing means).

Claims (3)

[Claims] 1. A master device connected to a master device via a data signal line and a clock signal line, and synchronized with a clock signal input from the master device via the clock signal line, via the data signal line. And a serial interface bus transmitting and receiving circuit for transmitting and receiving data serially, wherein the data input from the master device via the data signal line and the clock signal input from the master device via the clock signal line are also used. A data transmission / reception stop / start detecting means for detecting the stop of data transmission / reception with the master device and the start of the data transmission / reception and outputting the detection result, and being reset by the signal level of the clock signal; Detection result by the data transmission / reception stop / start detection means Performing a timed operation based on the condition recognition signal timed output means for outputting a stop condition recognition signal and a start condition recognition signal after a lapse of a set time, and an initialization instruction signal for instructing initialization for data transmission and reception. Initialization instruction signal generation means for generating and outputting based on the output of the condition recognition signal timed output means; and resetting the initialization instruction signal output by the initialization instruction signal generation means based on the clock signal. Initialization instruction signal reset means, for performing initialization for data transmission / reception based on the initialization instruction signal output from the initialization instruction signal generation means, and the initialization instruction signal reset means Control means for transmitting and receiving data to and from the master device in synchronization with the clock signal after resetting the clock signal. Le interface bus transceiver circuit. 2. An initialization instruction signal generating means for detecting the output of the condition recognition signal timed output means or the stop of data transmission / reception with the master device detected by the data transmission stop / start detection means, and the detection of the start of the data transmission / reception 2. The serial interface bus transmission / reception circuit according to claim 1, wherein an initialization instruction signal for instructing initialization for data transmission / reception is generated and output based on the result. 3. Determination data storage means for storing determination data used to determine a mutual input condition between data input via a data signal line and a clock signal input via a clock signal line; Based on the judgment data stored in the judgment data storage means,
Mutual input condition determining means for determining the mutual input condition; determination result storage means for storing a determination result by the mutual input condition determining means; determination result for reading the determination result stored in the determination result storage means from a master device 3. The serial interface bus transmitting / receiving circuit according to claim 1, further comprising a reading unit.