JPH1152031A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize an analog, digital mixed semiconductor integrated circuit which enables a test solely to a digital circuit. SOLUTION: A line-switching circuit 11 which is controlled by a test mode signal 103 and controls to switch supply of a source voltage VDD to an analog circuit 12, and a line-switching circuit 13 which is controlled by a test mode signal 104 and controls to switch a line connecting an input signal 101 directly to an output terminal of the analog circuit 12 are provided for the analog circuit 12 which is an analog circuit main body and outputs the signal 106 to an internal circuit including a digital circuit upon receipt of the input signal 101.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit including signal input means for enabling an independent test of a digital circuit in an analog / digital mixed semiconductor integrated circuit.

[0002]

2. Description of the Related Art Generally, in a semiconductor integrated circuit in which an analog circuit and a digital circuit are mixedly mounted, a power supply current in the analog circuit is much larger than a power supply current in the digital circuit. In testing a circuit, it is extremely difficult to measure the power supply current of only the digital circuit unless the analog circuit is shut off. In such a semiconductor integrated circuit in which an analog circuit and a digital circuit are mixedly mounted, a conventional example in which the analog circuit and the digital circuit are tested is disclosed in, for example, Japanese Patent Laid-Open No. 5-26982
A test signal input circuit disclosed in Japanese Unexamined Patent Publication (Kokai) No. H11-209686 is known. FIG. 3 is a block diagram showing the test signal input circuit. As shown in FIG. 3, in this conventional example, P-channel MOS transistors 31 and 3 correspond to analog signal input terminal 38 and test mode input terminal 39, respectively.
2 and N-channel MOS transistors 33 and 34
, A DC power supply 35, an analog circuit 36, and a digital circuit 37. The P-channel MOS transistors 31 and 32 and the N-channel MOS transistors 33 and 34 form a NAND circuit.

In FIG. 3, when testing the analog circuit 36, an analog signal is directly input to the analog circuit 36 from an analog signal input terminal 38. This is the same during the normal operation. Further, in the test mode of the digital circuit 37, in the test mode, the mode setting signal 107 of “H” level is input to the test mode input terminal 39, whereby the P-channel MOS transistor 32 is turned off, N-channel MOS transistor 33 is turned ON. In this state, the input to analog signal input terminal 38 is applied to P-channel MOS transistor 3
1 and a circuit including the N-channel MOS transistor 34 are formed as inverters. Therefore, when a digital signal is input to the analog signal input terminal 38, the digital signal is inverted via the inverter and directly input to the digital circuit 37 as a test signal 108.

[0006] During normal operation of the digital circuit 37, an “L” level mode setting signal 107 is input to the test mode input terminal 39. This allows P
The channel MOS transistor 32 turns on, and the N-channel MOS transistor 33 turns off. In this state, even when an intermediate potential is input to analog signal input terminal 38, a through current does not flow from DC power supply 35 to the ground point in a circuit formed by these MOS transistors. Further, since the P-channel MOS transistor 32 is in the ON state, the test signal 108 does not enter an undefined state and is kept at the “H” level. That is, in the conventional example, during normal operation, a fixed “H” level signal is input to the digital circuit 37 via the P-channel MOS transistor 32 in the ON state and is held.

[0005]

In the conventional analog / digital mixed semiconductor integrated circuit described above, even if an attempt is made to separate the digital circuit from the analog circuit and perform the test, the power supply current test of the digital circuit alone must be performed alone due to the circuit configuration. Has the disadvantage that it cannot be performed.

In the analog / digital hybrid semiconductor integrated circuit to be tested, most of the semiconductor integrated circuits often use the output of the analog circuit as the input of the digital circuit. However, when the test input level to the digital circuit remains fixed, there is a disadvantage that it becomes impossible to perform a functional operation test as a semiconductor integrated circuit that simultaneously operates the analog circuit and the digital circuit. Furthermore, in response to the drawback in the normal operation mode, when prohibiting the transmission of the test input level to the digital circuit in the normal operation mode to the next stage,
There is a disadvantage that an extra control circuit for prohibition needs to be added.

SUMMARY OF THE INVENTION It is an object of the present invention to enable an independent operation test of a digital circuit alone without an analog circuit as a test circuit for a digital circuit in an analog / digital mixed semiconductor integrated circuit. It is an object of the present invention to realize a semiconductor integrated circuit having a test function circuit capable of simplifying the operation and improving the defect detection rate with a minimum circuit configuration.

[0008]

In the semiconductor integrated circuit of the present invention, an analog circuit receiving an external signal input and an internal circuit including a digital circuit receiving an output signal of the analog circuit are mixed and mounted. In a semiconductor integrated circuit, during a normal operation of the semiconductor integrated circuit through a predetermined operation mode signal input from the outside, while maintaining the operation functions of the analog circuit and the digital circuit together, the digital circuit At the time of a test, the digital circuit is provided with a signal input unit that functions so as to stop the operation function of the analog circuit and execute a single test of the digital circuit.

The signal input means includes first line switching means functioning to control opening and closing of a power supply line for the analog circuit through a first operation mode signal input from the outside; The circuit is inserted and connected between the input terminal and the output terminal of the analog circuit, and controls the opening and closing of a line between the input terminal and the output terminal of the analog circuit via a second operation mode signal input from the outside. The second that works
And at least a line switching means, during normal operation, closing the first line switching means via the first operation mode signal to supply a power supply voltage to the analog circuit. Then, while maintaining the operation function, the second line switching means is opened via the second operation mode signal, and the line between the input terminal and the output terminal of the analog circuit is opened. In the test of the digital circuit,
The first line switching means is opened via the first operation mode signal, the power supply to the analog circuit is cut off, the operation function is stopped, and the operation is stopped via the second operation mode signal. The second line switching means is closed, and a line between the input terminal and the output terminal of the analog circuit is connected.

Further, the first circuit switching means includes:
A P-channel MOS having a source connected to the power supply voltage, a gate receiving the first operation mode signal, and a drain connected to a power supply voltage input terminal of the analog circuit;
The second circuit switching means is formed by a transistor, wherein the source is connected to the input terminal of the analog circuit, the drain is connected to the output terminal of the analog circuit, and the gate is included in the second operation mode signal. And a drain connected to a source of the P-channel MOS transistor, a source connected to a drain of the P-channel MOS transistor, and a gate connected to the gate. And an N-channel MOS transistor to which a second operation mode signal B included in the second operation mode signal is input.

Alternatively, as the first circuit switching means, a drain is connected to a ground terminal of the analog circuit, and the first operation mode signal is input to a gate,
The second circuit switching means is formed by an N-channel MOS transistor having a source connected to a ground point, the source being connected to an input terminal of the analog circuit, and the drain being connected to an output terminal of the analog circuit. A P-channel MOS transistor having a gate to which a second operation mode signal A included in the second operation mode signal is input, a drain connected to a source of the P-channel MOS transistor, and a source connected to the P-channel MOS transistor And an N-channel MOS transistor having a gate to which a second operation mode signal B included in the second operation mode signal is input.

Further, the analog circuit may be formed by an operational amplifier having a positive input terminal and a negative input terminal, and the positive input terminal may function as a test signal input terminal when testing the digital circuit. Alternatively, the digital circuit may be formed by an operational amplifier having a positive input terminal and a negative input terminal, and the negative input terminal may function as a test signal input terminal when testing the digital circuit.

[0013]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing only an input circuit portion according to an embodiment of the present invention. As shown in FIG.
This embodiment is an analog circuit main body, and an input signal 10
An analog circuit 1 which receives 1 as an input and outputs a signal 106 to an internal circuit (not shown) including a digital circuit
2, the line switching circuit 11 controlled by the test mode signal 103 to switch the supply of the power supply voltage V _{DD to} the analog circuit 12, and the input signal 101 controlled by the test mode signal 104 A line switching circuit 13 that controls switching of a line directly connected to the output terminal of the analog circuit 12 is provided.

In FIG. 1, during normal operation, the line switching circuit 11 is turned on under the control of the test mode signal 103, the power supply voltage V _DD is supplied to the analog circuit 12, and The device enters the operating state in response to the supply of the potential power supply voltage V _SB . On the other hand, under the control action of the test mode signal 104, the line switching circuit 13 is turned off, whereby the connection between the input terminal and the output terminal of the analog circuit 12 is cut off. In this state, the input signal 101 is input to the analog circuit 12, and the output signal 106 is input to an internal circuit (not shown) including a digital circuit. In a test mode for testing a digital circuit included in the internal circuit, the line switching circuit 11 is turned off under the control of the test mode signal 103, and the power supply voltage V _DD is supplied to the analog circuit 12. Is stopped. As a result, the operation function of the analog circuit 12 is completely stopped. Further, under the control of the test mode signal 104, the line switching circuit 13 is turned on, whereby the line connecting the input terminal and the output terminal of the analog circuit 12 becomes conductive, and the input signal 101 As a result, the test input signal input from the outside bypasses the analog circuit 12 and is directly input to the digital circuit.
This makes it possible to perform a single test on the digital circuit.

FIG. 2 is a circuit diagram showing only an input circuit portion according to one embodiment of the present invention. As shown in FIG. 2, this embodiment is an analog circuit main body, and corresponds to a comparator 22 which receives input signals 101 and 102 and outputs a signal 106 to an internal circuit (not shown) including a digital circuit. The P-channel MOS transistor 21 controlled by the test mode signal 103 to switch the supply of the power supply voltage V _DD to the analog circuit 22
And the P-channel MOS transistor 24 and the N-channel MOS transistor 25. The input signal 101 is directly connected to the output terminal of the analog circuit 22, that is, the internal circuit under the control of the test mode signals 104 and 105. And an analog switch 23 for controlling connection of the line to be connected.

In FIG. 2, during a normal operation, an external test mode signal 103 is input at "L" level and is gate-input to P-channel MOS transistor 21. As a result, the P-channel MOS transistor 21 is turned on, the power supply voltage V _DD is supplied to the comparator 22, and the comparator 22 is in an operation operable state. At this time, the test mode signal 104 is input as “H” level, and the test mode signal 105 is input as “L” level.
Is in the OFF state. Thereby, the connection between the input terminal and the output terminal of the comparator 22 is cut off. In this state, in the comparator 2, a predetermined comparator operation is performed in response to the input of the input signals 101 and 102, and the signal 106 as the comparison output is transmitted to the internal circuit, and the normal operation as the semiconductor integrated circuit is performed. Normal operation is performed.

In the test mode, the test mode signal 103 is input at the "H" level. In response to this, the P-channel MOS transistor 21 is turned off, and the power supply voltage V _DD is changed to the level of the comparator 22. , And the operation function of the comparator 22 is stopped. That is, the comparator 22 is in a non-operating state, and its output terminal is in a high impedance state. At that time, the test mode signal 104 becomes “L”.
The level and the test mode signal 105 are at the “H” level, whereby the analog switch 23 is in the ON state. In such a state, when an “H” level or “L” level test signal is input as an external input signal 101, the test signal bypasses the comparator 22 and passes through the analog switch 23. Is output to the internal circuit. That is, in the test mode, a test signal of “H” level or “L” level input from the outside as the input signal 101 can be directly input to the internal circuit as a test signal for the internal circuit. it can.

In the description of one embodiment,
In an input circuit including a comparator 22 forming an analog circuit main body, in a test mode, a test signal to an internal digital circuit can be directly input via a signal input terminal to the analog circuit main body as an example. Although described, the present invention provides, in a test mode, an input circuit including a digital circuit main body.
Via the signal input terminal to the digital circuit body,
It can be applied effectively even when the test signal to the internal analog circuit can be directly input. Further, when the digital circuit body and the analog circuit body are independent of each other, Needless to say, the present invention can be effectively applied to each input circuit in the same manner as described above.

[0020]

As described above, the present invention is applied to a semiconductor integrated circuit in which an analog circuit and a digital circuit are mixed, and turns off the analog circuit and performs a test through a bypass path. The signal can be directly transmitted to the digital circuit, so that the digital circuit can be performed separately from the analog circuit.

In a normal operation, the analog circuit and the digital circuit can be operated simultaneously since the analog circuit is bypassed and the bypass circuit that directly transmits the input signal to the digital circuit is cut off. Possible, including these analog and digital circuits,
There is an effect that a functional operation test as a semiconductor integrated circuit can be executed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing one embodiment of the present invention.

FIG. 3 is a circuit diagram showing a conventional example.

[Explanation of symbols]

11, 13 Line switching circuit 12, 23, 36 Analog circuit 21, 24, 31, 32 P-channel MOS transistor 22 Comparator 23, 36 Analog circuit 25, 33, 34 N-channel MOS transistor 35 DC power supply 37 Digital circuit 38 Analog signal input Terminal 39 Test mode input terminal

Claims (6)

[Claims] 1. A semiconductor integrated circuit in which an analog circuit receiving an external signal input and an internal circuit including a digital circuit receiving an output signal of the analog circuit are mounted and mixed, wherein a predetermined external input signal is provided. Through the operation mode signal, during the normal operation of the semiconductor integrated circuit, the operation functions of the analog circuit and the digital circuit are both maintained, and during the test of the digital circuit, the operation function of the analog circuit is performed. A semiconductor integrated circuit comprising: a signal input unit that functions to stop the digital circuit and perform an independent test of the digital circuit. A first operation mode signal input from the outside, wherein the signal input means functions to control opening and closing of a power supply line for the analog circuit.
And a line switching means, which is inserted between the input terminal and the output terminal of the analog circuit, and is connected between the input terminal and the output terminal of the analog circuit through a second operation mode signal input from the outside. And a second line switching means that functions to control the opening and closing of the line.
The first line switching means is closed via the first operation mode signal, a power supply voltage is supplied to the analog circuit, the operation function is maintained, and the analog circuit is maintained via the second operation mode signal. The second line switching means is open, and the line between the input terminal and the output terminal of the analog circuit is open. In the test of the digital circuit, the first operation is performed. The first line switching means is opened via a mode signal, the power supply to the analog circuit is cut off, its operation function is stopped, and the second line switching means is supplied via the second operation mode signal. 2. The semiconductor integrated circuit according to claim 1, wherein a line is connected between an input terminal and an output terminal of the analog circuit by using the means as a closed circuit. 3. The first circuit switching means has a source connected to the power supply voltage, a gate receiving the first operation mode signal, and a drain connected to a power supply voltage input terminal of the analog circuit. The second circuit switching means includes a source connected to an input terminal of the analog circuit, a drain connected to an output terminal of the analog circuit, and a gate connected to the second operation switch. A P-channel MOS transistor to which a second operation mode signal A included in the mode signal is input, a drain connected to a source of the P-channel MOS transistor, and a source connected to a drain of the P-channel MOS transistor; An N-channel MOS transistor whose gate receives a second operation mode signal B included in the second operation mode signal. 3. The semiconductor integrated circuit according to claim 2, formed by a transistor. 4. An N-channel circuit comprising: a first circuit switching means, wherein a drain is connected to a ground terminal of the analog circuit, a first operation mode signal is input to a gate, and a source is connected to a ground point. The second circuit switching means is formed by a MOS transistor, and has a source connected to an input terminal of the analog circuit, a drain connected to an output terminal of the analog circuit, and a gate connected to the second operation mode signal. A P-channel MOS transistor to which the included second operation mode signal A is input; a drain connected to the source of the P-channel MOS transistor; a source connected to the drain of the P-channel MOS transistor; N-channel MO to which second operation mode signal B included in second operation mode signal is input
3. The semiconductor integrated circuit according to claim 2, formed by an S transistor. 5. The digital circuit according to claim 1, wherein the analog circuit is formed by an operational amplifier having a positive input terminal and a negative input terminal, and the positive input terminal functions as a test signal input terminal when testing the digital circuit. Item 1,
5. The semiconductor integrated circuit according to claim 2, 3, 3, or 4. 6. The digital circuit according to claim 1, wherein the analog circuit is formed by an operational amplifier having a positive input terminal and a negative input terminal, and the negative input terminal functions as a test signal input terminal when testing the digital circuit. Item 1,
5. The semiconductor integrated circuit according to claim 2, 3, 3, or 4.