JPH1146189A - Clock phase synchronization circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the clock phase synchronization circuit by which phases of clock signals generated through frequency division at a clock control section such as a data transmission terminal station equipment of a dual system or the like are always synchronously with each other. SOLUTION: Clock pulses CP0, CP1 with 64 kHz of 0 and 1 systems are frequency-divided into 1/512 by synchronization counters 120 , 121 and clock signals CK0, CK1 with 125 kHz are outputted from respective output terminals Q9. On the other hand, counts CNT0, CNT1 of the synchronization counters 120 , 121 are given respectively to ANDs 130 , 131 and synchronizing signals SYN0, SYN1 are outputted when the value of the ANDs 130 , 131 reach 511. The synchronizing signals SYN0, SYN1 are given to selectors 140 , 141 and the synchronization counters 120 , 121 are reset by the synchronizing signals SYN0, SYN1 selected by a selection signal SEL.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock phase synchronizing circuit for synchronizing the phases of clock signals supplied from two clock supply units in a data transmission terminal device or the like constituted by a double system. Things.

[0002]

2. Description of the Related Art FIG. 2 is a system diagram showing an example of a clock supply system in a conventional dual data transmission terminal equipment. The data transmission terminal apparatus from the transmission signal TS0 sent through the transmission line _{1 0,} frame pulse F of the system clock SC0 and 8kHz of 2.048MHz
P0 is extracted and the extracted system clock S
C0 and divides has a clock control unit _{2 0} 0-system for generating a clock signal CK0 of 125 Hz. This data transmission terminal apparatus, from the transmission signal TS1 sent through the transmission line _{1 1,} extracts the frame pulse FP1 of the system clock SC1 and 8kHz of 2.048 MHz, the extracted system clock SC1 division To generate a 125 Hz clock signal CK1
And a clock control unit 2 ₁ system. 0-system and the clock control unit _{2 0} system clocks SC0 and frame pulse FP0 extracted with, the generated clock signal CK0
Are given to, for example, the signal processing unit 3 in the data transmission terminal station device. Meanwhile, the 1-system clock control section _{2 1} system clock SC1 and frame pulse FP1 extracted with, was also generated clock signal CK1,
Similarly, it is provided to the signal processing unit 3. In the signal processing section 3, one of the two clock control unit 2 _0, 2 ₁ signal supplied from, based on the specified by the selection signal SEL signal, and performs signal processing.

In such a data transmission terminal station device,
For example, towards the transmission line 1 ₀ is so if set higher priority than the transmission line 1 _1, the clock control unit 2 ₀ by the selection signal SEL is at all times be specified. Then, the signal processing section 3, a system clock SC0 given from the clock control unit _{2 0,} frame pulse FP0,
And signal processing based on the clock signal CK0. Here, if a failure occurs in the transmission path 1 ₀ or clock control unit 2 ₀ 0 system is changed specified to the clock control unit 2 ₁ of 1 system by the selection signal SEL, the signal processing section 3, the clock control system clock SC1 supplied from part _{2 1,} a frame pulse FP1, and the clock signal CK
1 to perform signal processing. In this manner, the signal processing unit 3 and the transmission line 1 _0, 1 _1, regardless of the clock control unit 2 _0, 2 ₁ of disorders, and is capable to continue the process.

[0004]

However, a conventional clock supply system such as a dual data transmission terminal equipment has the following problems. That is, the clock control unit 2
_{0, 2 1,} a system clock signal SC0, SC1 of 2.048MHz extracted respectively by dividing, independently 1
The clock signals CK0 and CK1 of 25 Hz are generated. Therefore, the start timing of the divided in the clock control section 2 _0, 2 _1, so do not match, usually, the two clock signals CK0, CK1 phase are different. Therefore, the signal processing unit 3, when the switching from the clock control unit 2 ₀ to the clock control unit 2 ₁ occurs, desynchronization occurs in the clock signal CK1, there is a problem that malfunction or data error occurs. The present invention, the prior art to solve the problems which had a double system of the data transmission terminal apparatus such as the clock control unit 2 _0, 2 ₁ clock signal generated by each division CK0, CK1, etc. And a clock phase synchronizing circuit capable of always synchronizing the phase of the clock phase.

[0005]

According to the present invention, there is provided a clock phase synchronization circuit comprising: a first and a second counting means; a first and a second counting determining means; , First and second selecting means. The first counting means includes a first counting means provided at a constant cycle.
Are sequentially counted from a fixed initial value, and the counting result is output. A first clock signal having a cycle that is a multiple of the fixed cycle is output based on the counting result, and a first reset is performed. When a signal is given, the counting result is reset to the constant initial value. First
Counting determination means is provided with the counting result of the first counting means, and when the counting result reaches a specific value,
Is output. The second counting means sequentially counts the second clock pulse given at the same constant cycle as the first clock pulse from the fixed initial value, outputs the counting result, and outputs the counting result based on the counting result. A second clock signal having the same cycle as the first clock signal is output, and when a second reset signal is applied, the counting result is reset to the constant initial value.

The second counting means is provided with the counting result of the second counting means, and outputs a second synchronizing signal when the counting result reaches the specific value. The first selector is provided with the first and second synchronization signals, selects the first or second synchronization signal based on the selection signal, and performs the first reset on the first counter. It is output as a signal. And
The second selector is provided with the first and second synchronization signals, selects the first or second synchronization signal based on the selection signal, and selects the second or the second synchronization signal with respect to the second counter. It is output as a reset signal. According to the present invention, since the clock phase synchronization circuit is configured as described above, the following operation is performed.

A first clock pulse applied at a constant period is applied to a first counting means, and the clock pulse is counted by the first counting means. First
The counting result of the counting means is given to the first counting and judging means, and when this counting result becomes a specific value, the first counting and judging means outputs the first synchronization signal. On the other hand, a second clock pulse having the same fixed period as the first clock pulse is given to the second counting means, and the clock pulses are counted by the second counting means. The counting result of the second counting means is given to the second counting judging means, and when the counting result becomes a specific value, the second counting judging means outputs the second synchronization signal. The first and second synchronization signals are both provided to the first and second selection means, and the first and second selection means receive the first or second synchronization signal based on the same selection signal. And outputs them as the first and second reset signals, respectively. The count result of the first counting means is reset to a constant initial value by a first reset signal output from the first selecting means. Also, the count result of the second counting means is reset to the same initial value by the second reset signal output from the second selecting means.

[0008]

FIG. 1 is a configuration diagram of a clock phase synchronization circuit showing an embodiment of the present invention. The clock phase synchronization circuit includes a clock control unit 10 ₀ 0 system, and a 1-system and the clock control unit 10 _1. These clock control unit ₁₀ 0, 10 _1, have the same configuration, the clock control unit 10 ₀ 0 system is 2.048 MHz
System clock SC0 and frame pulse FP0 of 8kHz of has a dividing counter 11 ₀ is given. Dividing counter 11 _0, the system clock SC0 and peripheral 1/32 binary, and generates a first clock pulse CP0 of 64kHz synchronized with the frame pulse FP0. The output side of the dividing counter 11 _0, first counting means connected to (e.g., synchronization counter) 12 ₀ of the clock terminal C. Synchronous counter 12 _0, for each rising edge of the clock pulse CP0 applied to the clock terminal C, and increases the binary count value CNT0 output to the output terminal Q1~Q9 by one. Further, the synchronous counter ₁₂₀ has a reset terminal R, and a reset signal RS applied to the reset terminal R.
When T0 is at the level "H", a function of resetting all the output signals of the output terminals Q1 to Q9 to the level "L" (that is, binary 0) in synchronization with the rise of the clock pulse CP0. ing. And the synchronization counter 12
_From the output terminal Q9 of ₀ , the clock pulse C of 64 kHz
A 125 Hz first clock signal CK0 obtained by dividing P0 by 1/512 is output.

[0009] In addition, the output terminal Q1 of the synchronous counter 12 ₀
~Q9 the first counting determination means (e.g., 9 input AND gate, hereinafter referred to as "AND") is connected to the input terminals of ₀ 13. AND13 output of _0, the first selection means (e.g., a selector) is connected to the input terminal A of 14 _0. The selector 14 ₀ has another input terminal B, the selection signal SE applied to the selection terminal S
When L is "H", the input signal on the input terminal A side is selected, and when the selection signal SEL is "L", the input signal on the input terminal B side is selected and output to the output terminal X. Output terminal X of the selector 14 _0, synchronous counter 12
₀ is connected to the reset terminal R. Similarly, 1-system clock control section 10 ₁ of the given frame pulse FP1 of the system clock SC1 and 8kHz of 2.048 MHz, the system clock SC1 and peripheral 1/32 binary, a second clock 64kHz and a dividing counter 11 ₁ Ruru to generate a pulse CP1. The output side of the dividing counter 11 _1, the second counting means is connected to (e.g., synchronization counter) 12 ₁ of the clock terminal C. Then, from the output terminal Q9 of the synchronous counter 121,
A 125 Hz second clock signal CK1 obtained by dividing the 64 kHz clock pulse CP1 by 1/512 is output.

[0010] In addition, the output terminal Q1 of the synchronous counter 12 ₁
To Q9 are second count determining means (for example, a 9-input AN
They are connected to respective input terminals of D13 _1. AND13 ₁
Output side is a second selection means (for example, a selector) 14
It is connected to _one input terminal B, and is connected to an input terminal B of the selector 14 ₀ in the clock controller 10 ₀ of the 0-system. Further, to the input terminal A of the selector 14 _{1, 0} AND13 in the clock controller 10 ₀ of the 0-system
Are connected to one another, and the selection signal SEL is given to the selection terminal S thereof. And selector 1
4 _first output terminal X is connected to the reset terminal R of the synchronous counter 12 _1. FIG. 3 is a time chart showing an operation sequence of the clock phase synchronization circuit of FIG.
Hereinafter, the operation of the clock phase synchronization circuit of FIG. 1 will be described with reference to FIG. For example, the selection signal SEL is set to level "H", the clock controller 10 ₀ of the 0-system are specified in the operating system.

[0011] of 64kHz generated by dividing counter 11 ₀ of the clock controller 10 ₀ of the 0-system clock pulse CP
0 is given to the clock terminal C of the synchronous counter 12 _0, for each rising edge of the clock pulse CP0, the count value CN of the counting result is output to the output terminal Q1~Q9
T0 increases by one sequentially from 0. Then, the count value CNT0 is 511, i.e., the output terminal Q1~Q9 all become "H", the synchronization signals SYN0 output from AND13 ₀ becomes "H". Synchronizing signals SYN0 is connected to the input terminal A of the selector 14 _0, the selection signal S
Since EL is set to level "H", the synchronization signal SYN0 is as a reset signal RST0, applied to the reset terminal R of the synchronous counter 12 _0. This allows
The synchronous counter ₁₂₀ is reset, and its count value C
NT0 is reset to the initial value 0. By such repetition, the clock pulse CP0 of 64 kHz becomes 1 /
512 is frequency division, the output terminal Q9 of the synchronous counter 12 ₀
Outputs a clock signal CK0 having a duty ratio of 50% and a frequency of 125 Hz.

Meanwhile, the 1-system input terminal A of the clock control section 10 ₁ of the selector 14 _1, the 0-system clock control unit 1
0 ₀ of AND13 ₀ of the synchronization signal SYN0 is given. The selection terminal S of the selector 14 _1, since the selection signal SEL of the level "H" is given, the synchronization signal SYN
0 reset signal RST1 is for synchronous counter 12 ₁
Is given and selected. Accordingly, the synchronous counter 12 ₀ 0 system, synchronous counter 12 ₁ of 1 system will be reset at the same timing by the synchronization signal SYN0. For this reason, the clock signals CK0 and CK1 are clock signals with a frequency of 125 Hz whose phases are synchronized.
Similarly, the synchronization signals SYN0 and SYN1 output from the ANDs 13 ₀ and 13 ₁ are signals whose timings match. Here, for example, it is assumed that a failure occurs in the system clock SC0 of the system 0 and the system is switched from the system 0 to the system 1 by the selection signal SEL. As a result, the input terminals B of the selectors 14 ₀ and 14 ₁ are selected, and this time, the synchronization signal SYN 1 is output to the synchronization counters 12 ₀ and 14 ₁ .
It is given as 12 ₁ of the reset signal RST0, RST1. At this time, since the synchronizing signals SYN0 and SYN1 have the same timing, the phases of the clock signals CK0 and CK1 do not change at all, and the supply of the stable clock signals CK0 and CK1 is continued.

[0013] Thus, in clock phase synchronization circuit of the present embodiment, the 0-system clock controller 10 ₀ and 1-system clock control section 10 ₁ of based on the same selection signal SEL, respectively the 0-system and 1 System synchronization signals SYN1, SY
From among N0, and a selector ₁₄ 0, 14 ₁ for selecting the reset signal RST0, RST1. As a result, the two clock control units 10 ₀ and 10 ₁ always output the synchronization signal SYN0 of the operation system specified by the selection signal SEL.
Alternatively, since the operation is forcibly synchronized with SYN1, the timing does not change even when the operation system is changed by the selection signal SEL, and the stable clock signal CK is obtained.
0, CK1 can be continuously supplied.

It should be noted that the present invention is not limited to the above embodiment, and various modifications are possible. For example, there are the following modifications (a) to (c). (A) The frequency of the system clocks SC0 and SC1,
The frequencies of the clock signals CK0 and CK1 generated by frequency division are not limited to the frequencies of the above-described embodiment, and can be applied to any combination of frequencies as long as the frequency is an integer frequency division ratio. Depending frequency (b) the system clock SC0, SC1, it is also possible to omit the dividing counter ₁₁ 0, 11 _1. (C) Separate selectors 14 ₀ , 14 _{1 for} system 0 and system ₁
, A common selector 14 is provided.
The reset signal RST selected in 4 may be commonly applied to the reset terminals R of the 0-system and 1-system synchronization counters 12 ₀ , 12 ₁ . Thus, the circuit configuration can be simplified.

[0015]

As described above in detail, according to the present invention, the first synchronization signal output from the first counting and judging means and the second synchronization signal output from the second counting and judging means. It has first and second selection means for selecting a signal with the same selection signal. Then, according to the first or second synchronization signal selected by the first and second selection means,
The first and second counting means are reset. As a result, the first and second counting means are always reset at the same time, so that a synchronized signal is always obtained as the first and second clock signals output from the first and second counting means. be able to.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a clock phase synchronization circuit according to an embodiment of the present invention.

FIG. 2 is a system diagram showing an example of a clock supply system in a conventional data transmission terminal device.

FIG. 3 is a time chart showing an operation sequence of FIG. 1;

[Description of reference numerals] 10 _0, 10 ₁ clock controller 12 _0, 12 ₁ synchronous counter 13 _{0, 13} 1 the AND ₁₄ 0, 14 ₁ selector CK0, CK1 clock signal CP0, CP1 clock pulse RST0, RST1 reset signal SEL selection signal SYN0, SYN1 Synchronous signal

Claims (1)

[Claims] A first clock pulse provided at a constant period, which is sequentially counted from a predetermined initial value, and a counting result is output; based on the counting result, a first clock pulse having a period that is a multiple of the predetermined period is obtained. 1 clock signal and the first
The first counting means for resetting the counting result to the constant initial value when the reset signal is given, and the counting result of the first counting means is given, and the counting result becomes a specific value. A first count judging means for outputting a first synchronizing signal when the second clock pulse given in the same fixed cycle as the first clock pulse is sequentially counted from the fixed initial value. Outputting a counting result, outputting a second clock signal having the same cycle as the first clock signal based on the counting result, and when the second reset signal is given, the counting result is set to the fixed value. A second counting means for resetting the count value to an initial value, and a second synchronization means for outputting a second synchronization signal when the counting result of the second counting means becomes the specific value. Judgment of counting Stage and said first and second synchronizing signal is provided, the first to select the first or the second synchronizing signal based on the selection signal
First selecting means for outputting as the first reset signal to the counting means, and the first and second synchronizing signals are provided, and the first or second synchronizing signal is selected based on the selecting signal. And a second selecting means for outputting as the second reset signal to the second counting means.