JPH1145988A - Light-receiving semiconductor device having built-in bicmos - Google Patents

Abstract

PROBLEM TO BE SOLVED: To constitute a vertical P-N-P transistor and an avalanche photodiode on the same P-type semiconductor substrate without damaging the characteristics of these transistor and avalanche photodiode by a method wherein P-type first and second semiconductor layers are formed onto an N-type first buried layer and used as an anode for the avalanche photodiode. SOLUTION: An avalanche photodiode(APD) is constituted while using a P-type first semiconductor layer 5 and a P-type second semiconductor layer 13 in the APD forming region as an anode and an N-type first buried layer 3 in the APD forming region as a cathode. The anode for the APD is separated by an N-type second buried region 7 brought into contact on the N-type first buried layer 3 of the APD forming region, while being formed as surrounding a P-type second buried layer 11 and an N-type sixth semiconductor region 42 formed while being brought into contact on the second buried region 7. Accordingly, a vertical type P-N-P transistor and the APD can be configured on the same P-type semiconductor substrate 1 without damaging the characteristics of these vertical type P-N-P transistor and APD.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a BiCMOS built-in light receiving semiconductor device, and more particularly to a vertical PNP transistor (vertical PNP-Tr), a MOS transistor, and a highly sensitive avalanche from ultraviolet to visible and near infrared regions. BiCMO with photodiode (APD)
The present invention relates to a semiconductor device incorporating S.

[0002]

2. Description of the Related Art Conventionally, most APDs have been formed as single elements. Therefore, in order to process the received signal, the APD has been used together with the signal processing integrated circuit, or assembled in the same package as the signal processing semiconductor device, and used as a hybrid integrated circuit (hybrid IC).

On the other hand, Japanese Patent Laid-Open No. 2-218160 proposes an example in which a CCD or a MOS transistor and an APD are formed. In this example, in an image sensor, an active element such as a transistor and an APD are monolithically configured.

When an APD is formed monolithically, the APD is generally used for high-speed applications, and therefore, a signal processing circuit also needs an element that can operate at a high speed and in a wide band.
As such an element, a high-speed NPN transistor (N
PN-Tr) and PNP transistor (PNP-T)
r) is conceivable. The NPN-Tr having a vertical structure suitable for high-speed operation can be easily formed. However, PNP
-Tr has a low speed and a narrow band because -Tr has a horizontal structure formed parasitically in the NPN-Tr manufacturing process.

[0005]

However, in the method of forming a hybrid IC, since the APD and the signal processing circuit are assembled in the same package, the structure of the assembly is complicated. In addition, since it is a hybrid IC, noise is easily generated by induction, and parasitic capacitance also increases. Further, it is difficult to arrange the APD together with the signal processing circuit in an array.

In the example described in Japanese Patent Application Laid-Open No. 2-218160, since a complicated manufacturing process such as selective epitaxial growth is required, the characteristics of the APD cannot be sufficiently obtained or the APD can be manufactured stably. Is difficult. Further, since the NPN transistor disclosed in this publication has a parasitic structure, parasitic resistance such as an emitter resistance, a collector resistance, and a base resistance is large. For this reason, the linearity and frequency characteristics of the transistor are not always sufficient to process the signal from the APD. In other words, to manufacture a high-performance APD capable of detecting a weak high-speed optical signal, there are severe restrictions on the conditions for forming the PN junction of the APD, and the characteristics depend on the element structure. On the other hand, integrated circuits such as bipolar transistors and MOS transistors have restrictions on manufacturing conditions in order to integrate these elements. For this reason, it is difficult to form them on the same substrate while deriving both characteristics.

On the other hand, to form a bipolar transistor, an epitaxial layer is grown on a substrate. However, although the epitaxial layer used for the bipolar transistor is relatively thin, the APD requires a relatively thick epitaxial layer in order to obtain high sensitivity up to the near infrared region. It is also difficult to meet this demand.

It is very convenient to use a vertical PNP-Tr in addition to a vertical NPN-Tr as an element used in an APD signal processing circuit. In order to configure a vertical NPN-Tr, it is preferable to use a P-type substrate. Therefore, vertical P
The NP-Tr must also be formed on a P-type substrate. However, in the case of a P-type substrate, the collector of the vertical PNP-Tr cannot be separated from the substrate, so that the collector is always grounded. Therefore, a vertical PNP-T suitable for a signal processing circuit
r cannot be obtained.

An object of the present invention is to provide a BiCMOS built-in light receiving semiconductor device in which the vertical PNP-Tr and the APD are formed on the same P-type semiconductor substrate without deteriorating the characteristics thereof.

[0010]

Therefore, the present invention has the following configuration.

In the BiCMOS built-in light receiving semiconductor device according to the present invention, an avalanche photodiode formation region (APD formation region) and a vertical PNP transistor formation region (vertical PNP-Tr formation region) on the upper surface layer of the P-type semiconductor substrate 1 are provided. The N-type first buried layer 3 formed on the P-type semiconductor substrate 1 and the N-type first buried layer 3
PD formation area, vertical PNP-Tr formation area, MOS P
Channel transistor formation region (PMOS-Tr formation region), MOS type N-channel transistor formation region (NM
The P-type first semiconductor layer 5 formed in the OS-Tr formation region) and the vertical NPN transistor formation region (vertical NPN-Tr formation region), and the P-type first semiconductor layer 5 in the PMOS-Tr formation region and the vertical NPN-Tr formation region. An N-type second buried region 7 formed in an upper surface layer in the first semiconductor layer 5;
On the N-type first buried layer 3 in the Tr formation region,
P-type first buried layer 9 formed in the upper surface layer in first type semiconductor layer 5 and N-type first buried layer 3 in the APD formation region
A P-type second buried layer 11 formed on the upper surface layer in the P-type first semiconductor layer 5;
P-type second semiconductor layer 13 formed on P-type first buried layer 9, P-type second buried layer 11 and N-type second buried region 7, and N-type second buried in vertical NPN-Tr formation region N-type first semiconductor layer 15 formed in contact with region 7
And the N-type second buried region 7 in the PMOS-Tr formation region
An N-type second semiconductor layer 17 formed in contact with the
An N-type third semiconductor layer 19 formed on the P-type first buried layer 9 in the NP-Tr formation region and an upper surface layer in the N-type first semiconductor layer 15 in the vertical NPN-Tr formation region. N
Type fourth semiconductor layer 25 and N in the vertical NPN-Tr formation region.
A P-type third semiconductor layer 27 which is formed on the upper surface of the first type semiconductor layer 15 and surrounds the bottom and side surfaces of the N-type fourth semiconductor layer 25; And a P-type fourth semiconductor layer 29 formed on the upper surface of the third semiconductor layer 19. The vertical PNP-Tr is a P-type first buried layer 9 in the vertical PNP-Tr formation region. , P
The n-type first semiconductor layer 5 and the p-type second semiconductor layer 13 are used as collectors, the n-type third semiconductor layer 19 is used as a base, and the p-type
The vertical NPN-
Tr uses the N-type second buried region 7 and the N-type first semiconductor layer 15 in the vertical NPN-Tr formation region as collectors, the P-type third semiconductor layer 27 as a base, and the N-type fourth semiconductor layer 25 as Tr. The APD is configured as an emitter,
The P-type first semiconductor layer 5 and the P-type second semiconductor layer 13 in the D formation region are used as anodes, and the N-type first buried layer 3 in the APD formation region is used as a cathode.
The collector of -Tr is in contact with the N-type first buried layer 3 in the vertical PNP-Tr formation region and surrounds the P-type first buried layer 9; An N-type fifth region formed in contact with second embedding region 7
An N-type second buried region 7 formed on the N-type first buried layer 3 in the APD formation region and surrounding the P-type second buried layer 11; It is separated from the N-type sixth semiconductor region 42 formed in contact with the N-type second buried region 7.

As described above, the P-type first semiconductor layer 5 and the P-type second semiconductor layer 13 are formed on the N-type first buried layer 3 to serve as the anode of the APD. The characteristics of the APD can be improved by the thickness. In addition, N-type second
The buried region 7 and the P-type first buried layer 9 are
Since the P-type second semiconductor layer 13 is formed on the semiconductor layer 5, the thickness of the P-type second semiconductor layer 13 is adjusted so that the vertical NPN-Tr and the vertical PNP-
The characteristics of Tr can be respectively improved. That is, if the thickness of the P-type first semiconductor layer 5 is changed according to the characteristics of the APD,
APD without affecting the characteristics of the bipolar transistor
The sensitivity to long wavelengths can be changed.

Since the N-type first buried layer 3 is formed on the P-type substrate 1 in the APD formation region, the cathode can be separated. Further, an N-type second buried region 7 formed around the P-type second buried layer 11 and an N-type sixth semiconductor region 4 formed on and in contact with the N-type second buried region 7
2 is provided in contact with the N-type first buried layer 3, and the P-type first semiconductor layer 5 and the P-type second semiconductor layer 13 are separated from the P-type substrate 1 by this separation region.
The anode can be separated. As described above, since the anode and the cathode are separated, the APD can be handled as an independent element. Further, since the P-type second buried layer 11 was formed in the upper layer on the surface of the P-type first semiconductor layer 5, A
Adjustment of PD characteristics becomes easy. That is, the avalanche breakdown voltage can be adjusted by the impurity profile of the P-type second buried layer 11.

Since the P-type first buried layer 9 is formed on the N-type first buried layer 3 in the vertical PNP-Tr formation region, the collector can be separated from the P-type substrate 1. Also, N
Providing the isolation region in contact with the first mold buried layer 3;
Type first semiconductor layer 5 and P-type second semiconductor layer 13
Since it is separated from the mold semiconductor layer, the collector can be separated. Further, since the P-type first buried layer 9 is formed on the P-type first semiconductor layer 5, the collector resistance can be reduced. In addition,
Since the N-type third semiconductor layer 19 is used as the base and the P-type fourth semiconductor layer 29 is used as the emitter, the formation of the base profile and the emitter junction can be controlled independently of other elements. That is, the current amplification factor, the early voltage, the frequency characteristics, and the like of the vertical PNP-Tr can be improved.

Since the N-type second buried region 7 is formed on the P-type first semiconductor layer 5 in the vertical NPN-Tr formation region, a low-resistance collector can be formed, and the collector is formed as the P-type substrate 1. Can be separated from In addition, since the P-type third semiconductor layer 27 is used as a base and the N-type fourth semiconductor layer 25 is used as an emitter, the junction between the base profile and the emitter can be controlled independently of other elements. In other words, vertical NP
The current amplification factor, the early voltage and the frequency characteristics of the N-Tr can be improved.

Since the NMOS-Tr formation region is provided on the upper surface layer of the P-type second semiconductor layer 13, the manufacturing process can be simplified.

Since the PMOS-Tr forming region is provided on the upper surface of the N-type second semiconductor layer 17 on the N-type second buried region 7, a parasitic PNP based on this N-type layer is provided.
The _hfe of the transistor can be reduced. Therefore, the latch-up resistance can be improved.

Since the isolation region is constituted by the N-type second buried region 7 and the N-type fifth semiconductor region 41 and the N-type sixth semiconductor region 42 formed thereon, element isolation can be achieved with a small isolation region. it can. As a result, the P-type first semiconductor layer 5 in the NMOS-Tr formation region can be separated from other element formation regions.

In the BiCMOS built-in light receiving semiconductor device according to the present invention, the N-type third semiconductor layer 19 which is the base of the vertical PNP-Tr may be formed in the same process as the N-type second semiconductor layer 17.

As described above, when the N-type third semiconductor layer 19 is formed by the same process as the N-type second semiconductor layer 17, the vertical P-type semiconductor layer 19 is formed.
Since the base of the NP-Tr and the N-type layer in the substrate gate portion of the PMOS-Tr can be formed simultaneously, the manufacturing process can be simplified.

The BiCMOS built-in light receiving semiconductor device according to the present invention includes a vertical PNP-Tr, a vertical NPN-Tr, and an NM.
The light-shielding film 37 may be provided on the OS-Tr and the PMOS-Tr, and the opening of the light-shielding film 37 may be provided on the anode of the avalanche photodiode.

As described above, the vertical PNP-Tr and the vertical NP
If the light-shielding film 37 is provided on the N-Tr, the NMOS-Tr, and the PMOS-Tr, these elements operate stably regardless of the amount of irradiated light. Further, if the light shielding film 37 has an opening on the anode, light can be introduced into the anode.

In the BiCMOS built-in light receiving semiconductor device according to the present invention, the N-type fifth semiconductor region 41 and the N-type sixth semiconductor region 42 are connected to at least one of the N-type first semiconductor layer 15 and the N-type second semiconductor layer 17. They may be formed by the same process.

As described above, the N-type fifth semiconductor region 41 and the N-type sixth semiconductor region 42 are formed in the same step as at least one of the N-type first semiconductor layer 15 and the N-type second semiconductor layer 17.
Is formed, the manufacturing process can be simplified.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings. In addition, the same portions are denoted by the same reference numerals, and overlapping description will be omitted.

FIGS. 1 to 4 are cross-sectional views showing the steps of manufacturing the BiCMOS built-in light receiving semiconductor device of the present invention. The manufacturing process of the BiCMOS built-in light receiving semiconductor device will be described using these.

As the semiconductor substrate, a P-type Si substrate 1 is used (FIG. 1A). The substrate 1 has an impurity concentration of 1 × 10 ¹⁴ c
m ^-3 or more and 2 * ¹⁰¹⁵ cm ^-3 or less is preferable, and (100) is preferably used as the plane orientation.

First, an N-type first buried layer 3 is formed on the upper surface layer of the substrate 1 (FIG. 1B). N-type buried layer 3
Is to form an Si oxide film on the substrate 1, remove a predetermined region of the oxide film by etching using a photolithography technique, and introduce an N-type impurity by thermal diffusion using the remaining Si oxide film as a mask. Form. The impurity is preferably antimony (Sb) or arsenic (As).

As shown in FIG. 1B, the N-type first buried layer 3 is formed in the APD formation region and the vertical PNP-Tr formation region. When formed in the APD formation region, it becomes a cathode. In order to lower the resistance of the cathode, the junction depth is preferably about 4 μm to 6 μm, and the surface concentration is 1 μm.
It is preferably from × 10 ¹⁹ cm ^{-3 to} 5 × 10 ¹⁹ cm ^-3 .
When formed in this manner, the cathode can be electrically separated from the substrate 1. When formed in the vertical PNP-Tr formation region, the collector is used as an N-type buried layer for electrically separating the collector from the substrate 1.

Next, a P-type first semiconductor layer 5 is formed on the entire surface of the wafer (FIG. 1C). This layer 5 is formed by a vertical NPN
-Tr formation region, NMOS-Tr formation region, PMOS-
Tr forming region, vertical PNP-Tr forming region and APD
It may be formed in the formation region. The P-type first semiconductor layer 5 is formed by epitaxial growth in order to form a relatively thick semiconductor layer having a uniform concentration. The thickness of the P-type semiconductor layer 5 is adjusted in a range where the N-type first buried layer 3 and the N-type second buried region 7 formed later are connected, and the depletion layer of the APD, operating voltage, incident wavelength, spectral Determined by sensitivity. Also, considering this layer 5 as a substrate, the NMOS-
Tr, PMOS-Tr, vertical NPN-Tr and vertical P
Since an NP-Tr is formed, the specific resistance and the impurity concentration are preferably the same as those of the substrate 1. In particular, the impurity concentration is 1
The range may be from × 10 ¹⁴ cm ^{-3 to} 1 × 10 ¹⁵ cm ^-3 .

Subsequently, an N-type second buried region 7 is formed in the upper surface layer of the P-type first semiconductor layer 5 (FIG. 2A). N
The mold second buried region 7 can be formed by the same method as the N-type first buried layer 3 using a photolithography technique. The impurities are antimony (Sb) or arsenic (A
s) is preferred. In order to reduce the collector resistance, the junction depth is preferably 4 μm to 6 μm, and the surface concentration is 1 × 1
It is preferably from 0 ¹⁹ cm ^{−3 to} 5 × 10 ¹⁹ cm ⁻³ . In FIG. 2A, the N-type first buried layer 3 is shown enlarged to the region of the P-type first semiconductor layer 5, but this is because
In the step of forming the second mold buried region 7, the first
This is because the impurities in the buried layer 3 diffuse into the P-type first semiconductor layer 5 and the N-type region expands. However, description of the same thing will be omitted below.

As shown in FIG. 2A, the N-type second buried region 7 includes a vertical NPN-Tr forming region, a PMOS-T
It is formed in the r formation region, the vertical PNP-Tr formation region, and the APD formation region. When the N-type second buried region 7 is formed in the vertical NPN-Tr formation region, the vertical NPN-Tr
And when it is formed in the PMOS-Tr formation region, it becomes a substrate gate portion (B in FIG. 4B). As described above, the collector and the substrate gate are connected to the P-type first semiconductor layer 5.
Since it is formed on the upper surface layer, the vertical NPN-Tr and PM
Regarding OS-Tr, each element can be configured by regarding the P-type first semiconductor layer 5 as a substrate. In the APD formation region and the vertical PNP-Tr formation region, the N-type second buried region 7 is formed on the N-type first buried layer 3 as an isolation region. When formed in this manner, the N-type second buried region 7 and the N-type first buried layer 3 overlap and are electrically connected. The isolation region is formed in a band-shaped closed region along the outer periphery on the N-type first buried layer 3. More specifically, in the vertical PNP-Tr formation region, the vertical PNP-Tr formation region is formed as a collector isolation region surrounding a P-type first buried layer 9 to be formed later. In the APD formation region, it is formed as a cathode separation region surrounding a P-type second buried layer 11 to be formed later.

Subsequently, the P-type first buried layer 9 is replaced with a vertical PN
It is formed in a P-Tr formation region (FIG. 2A). P type first
The buried layer 9 is preferably formed by ion implantation using a photolithography technique, and the impurity is preferably boron (B ⁺ ). The P-type first buried layer 9 is formed on the N-type first buried layer 3 and inside the previously formed N-type second buried region 7. In order to lower the collector resistance, the dose is 5 × 10 ¹³ cm ⁻² or more and 3 × 10 ¹⁴
cm ^-2 or less is preferable. Finally, the P-type first buried layer 9 has a peak concentration of 1 × 10 ¹⁷ cm ^{−3 to} 5 × 10 ¹⁷ cm ⁻³ .

Next, a P-type second buried layer 11 is formed in the APD formation region (FIG. 2A). The P-type second buried layer 11 is preferably formed by ion implantation using a photolithography technique, and the impurity is boron (B
⁺ ) Is preferred. The P-type second buried layer 11 is an N-type first buried layer.
It is formed on the buried layer 3 and inside the previously formed N-type second buried region 7. In order to improve the characteristics of the APD, the dose is 3 × 10 ¹¹ cm ⁻² or more and 3 × 10 ¹²
cm ^-2 or less, and ultimately, P-type second buried layer 11 has a peak concentration of 1 × 10 ¹⁵ cm ^-3 to 6 × 10 ¹⁵ cm ^-3. The characteristics of the APD can be adjusted by this impurity layer. That is, since the P-type second buried layer 11 is disposed on the upper surface layer of the P-type first semiconductor layer 5 so as to face the N-type first buried layer 3, the P-type second buried layer 11 has a different impurity profile from the N-type first buried layer 3. The extent of the depletion layer is controlled. Therefore, the avalanche breakdown voltage can be adjusted.

Prior to the formation of the N-type second buried region 7, the P-type first buried layer 9 and the P-type second buried layer 11 may be formed.

After forming these impurity layers, a P-type second semiconductor layer 13 is formed on the entire surface of the wafer (FIG. 2B).
Further, this layer 13 is formed as a vertical NPN-Tr formation region, NM
OS-Tr formation region, PMOS-Tr formation region, vertical P
It may be formed in the NP-Tr formation region and the APD formation region. The P-type second semiconductor layer 13 is formed by epitaxial growth in order to form a relatively thick semiconductor layer having a uniform concentration. The thickness of the epitaxial layer is 5 μm or more in order to sufficiently exhibit the characteristics of the bipolar transistor.
The thickness is preferably about 10 μm, and the impurity concentration is preferably about the same as that of the substrate 1. In the NMOS-Tr formation region, the P-type second
The semiconductor layer 13 is integrated with the already formed P-type first semiconductor layer 5 to form a substrate gate portion of the NMOS-Tr (FIG. 4).
(C part of (b)). In the APD formation region, the P-type first
Since the semiconductor layer 5 and the P-type second semiconductor layer 13 serve as light absorbing layers, the sensitivity on the long wavelength side is determined by the thickness of these two layers. Therefore, if the P-type first semiconductor layer 5 is made thicker to make the total light absorbing layer thicker, the long-wavelength sensitivity of the APD can be increased without changing the characteristics of the bipolar transistor.

Next, an N-type impurity is ion-implanted using a photolithography technique to form an N-type first semiconductor layer 15 (FIG. 2C). Since the N-type first semiconductor layer 15 is a semiconductor layer which is relatively deep and controlled to a low concentration, it is preferably formed by ion implantation, and the impurity is preferably phosphorus (P ⁺ ). In order to sufficiently exhibit vertical NPN-Tr characteristics, the dose amount is 3 × 10 ¹² cm ⁻² or more and 6 × 10 6
^It is preferably ¹² cm ^-2 or less.

The N-type first semiconductor layer 15 may be formed by the same process as the N-type sixth semiconductor region 42 in the APD formation region, as shown in FIG.

In the vertical NPN-Tr formation region, the N-type first
The semiconductor layer 15 is preferably formed in substantially the same shape on the N-type second buried region 7. When formed in this manner, the electrodes are overlapped and electrically connected by the diffusion of impurities, so that a collector having low resistance can be formed.

In the APD formation region, the N-type sixth semiconductor region 42 is formed in the anode isolation region. The isolation region is formed in a band-like closed region surrounding the anode and in contact with the N-type second buried region 7. When formed in this manner, they are mutually overlapped and electrically connected by diffusion of impurities. Further, since the anode can be separated in a small region, it is preferable that the anode is formed in substantially the same shape as the N-type second buried region 7.

Subsequently, an N-type second semiconductor layer 17 is formed in the same manner as the N-type first semiconductor layer 15 (FIG. 2C).
In order to sufficiently exhibit the PMOS-Tr characteristics, the dose is preferably from 6 × 10 ¹² cm ^{−2 to} 8 × 10 ¹² cm ⁻² .

As shown in FIG. 2C, the N-type second semiconductor layer 17 is formed by the same process as the N-type third semiconductor layer 19 and the N-type fifth semiconductor region 41 in the vertical PNP-Tr formation region. It may be formed.

In the PMOS-Tr formation region, the N-type second semiconductor layer 17 is formed on the N-type second buried region 7,
Preferably, they are formed in substantially the same shape. In this case, the substrate is overlapped with the N-type second buried region 7 by the diffusion of the impurity to form a substrate gate portion. Since the impurity concentration of the N-type base of the parasitic transistor is high and a thick layer is formed, the transistor operation is suppressed, and the latch-up resistance is improved. These are the P-type first semiconductor layer 5 and the P-type second semiconductor layer 5.
Since the side surface and the bottom surface are surrounded by the semiconductor layer 13, the substrate 1, the collector of the vertical NPN-Tr and other PMOS
-It is electrically separated from the gate portion of the Tr substrate.

In the vertical PNP-Tr formation region, the N-type fifth
The semiconductor region 41 is formed in the collector isolation region. The isolation region is formed in a band-like closed region surrounding the collector and in contact with the N-type second buried region 7. When formed in this way, they are overlapped and electrically connected by diffusion of impurities. Further, since the collector can be separated in a small region, it is preferable that the collector be formed in substantially the same shape as the N-type second buried region 7. The N-type third semiconductor layer 19 is
P-type second semiconductor layer 1 on P-type first buried layer 9
3 and serves as a base of the vertical PNP-Tr.

After the ion implantation of the N-type first semiconductor layer 15 and the N-type second semiconductor layer 17, it is preferable that the depth of the N-type layers 15 and 17 be 2 μm to 4 μm through a heat step of high-temperature drive.

Subsequently, LOCOS 21 is formed (FIG. 3)
(A)). The LOCOS 21 can be formed, for example, by the following method. When a silicon nitride film is deposited on the silicon oxide film on the wafer surface, and the silicon nitride film other than the active region is removed by etching using a photolithography technique and then oxidized in an oxidation furnace, the oxide film in a portion where the silicon nitride film does not exist is obtained. And the field oxide film 21 is formed in a region other than the active region. The field oxide film 21 is formed of a vertical PNP-Tr
Formation region, vertical NPN-Tr formation region, PMOS-Tr
The active region is formed between the active region in the formation region, the NMOS-Tr formation region, and the APD formation region. When formed in this manner, APD and NMOS-
Tr, PMOS-Tr, vertical PNP-Tr and vertical N
Each region of the PN-Tr can be separated by the field oxide film 21.

Thereafter, impurities are introduced by ion implantation into the channel region of the PMOS-Tr and the channel region of the NMOS-Tr, respectively.
The gate surface region of the OS-Tr has an appropriate impurity concentration. By this ion implantation, the PMOS-Tr and NM
The threshold voltage of OS-Tr is determined. Then, a gate oxide film is formed on the channel portion.

Subsequently, polysilicon is deposited by a CVD method, phosphorus is diffused to reduce the resistance, and then the polysilicon is patterned by using a photolithography technique.
Etching, NMOS-Tr and PMOS-Tr
The gate electrode 23 and the wiring are formed (FIG. 3A).

Next, a P-type third semiconductor layer 27 is formed as a base in the vertical NPN-Tr formation region.
(B)). The P-type third semiconductor layer 27 is formed on the upper surface layer in the N-type first semiconductor layer 15 so as to surround the side and bottom surfaces by the semiconductor layer 15. P-type third semiconductor layer 27
Is formed by ion-implanting a P-type impurity with low energy using a photolithography technique, and the impurity is B ⁺
Is used. In order to sufficiently exhibit the characteristics of the vertical NPN-Tr, the dose is 5 × 10 ¹³ cm ⁻² or more and 3 × 10 ¹⁴ c
m ^-2 or less is preferable. The depth of the junction after activation is vertical N
In order to increase the speed of PN-Tr, 0.5 μm to 0.7 μm
It is preferably about μm.

Subsequently, an N-type fourth semiconductor layer 25 is formed in the active region on the surface of the substrate (FIG. 3B). Since the N-type fourth semiconductor layer 25 has a shallow junction and a high concentration, it is preferable to use arsenic (As ⁺ ) as an impurity by ion implantation. In order to sufficiently exhibit the characteristics of the emitters of the NMOS-Tr and the NPN-Tr, the dose is 3 × 10
^The thickness is preferably ¹⁵ cm ^-2 or more and 10 × 10 ¹⁵ cm ^-2 or less, and the depth of the junction after activation is preferably 0.2 μm to 0.4 μm.

The N-type fourth semiconductor layer 25 is formed of a vertical PNP-T
It is formed in the r formation region, the vertical NPN-Tr formation region, the APD formation region, and the NMOS-Tr formation region. More specifically, when the N-type fourth semiconductor layer 25 is formed on the upper surface of the N-type second semiconductor layer 19 in the vertical PNP-Tr formation region, it becomes a base diffusion electrode. In the vertical NPN-Tr formation region, when formed on the upper surface layer in the P-type third semiconductor layer 27, it becomes an emitter, and when formed on the upper surface layer in the N-type first semiconductor layer 15, the diffusion electrode of the collector is formed. Become. AP
In the D formation region, when formed on the upper surface layer of the N-type first semiconductor layer 15 in the isolation region, it becomes a diffusion electrode for the isolation region. In the NMOS-Tr formation region, when formed adjacent to both sides of the gate electrode 23, it becomes the source / drain of the NMOS-Tr. Such a high concentration diffusion layer is used to form an ohmic contact between the N-type semiconductor layer and the metal electrode 33.

Next, a P-type fourth semiconductor layer 29 is formed in a surface active region such as an APD formation region (FIG. 3C). P
Since the junction of the type fourth semiconductor layer 29 is formed at a high concentration with a shallow junction, it is preferable to use B ⁺ as a P-type impurity by ion implantation. In order to sufficiently exhibit the characteristics of the emitters of the PMOS-Tr and PNP-Tr, the dose is 1 × 1.
0 ¹⁵ cm ^-2 to 5 × preferably 10 ¹⁵ cm ^-2 or less, the junction depth after activation, 0.2Myuemu～0.4Myuemu is preferred.

The P-type fourth semiconductor layer 29 is formed of a vertical PNP-T
It is formed in an r formation region, an APD formation region, a vertical NPN-Tr formation region, and a PMOS-Tr formation region. More specifically, the P-type fourth semiconductor layer 29 functions as an emitter when formed on the upper surface of the N-type third semiconductor layer 19 in the vertical PNP-Tr formation region, and the upper surface of the P-type second semiconductor layer 13. When formed on the surface layer, it becomes a diffusion electrode of the collector. In the APD formation region, a diffusion electrode of the anode is formed on the N-type first buried layer 3 inside the anode isolation region.
In the vertical NPN-Tr formation region, the third P-type diffusion layer 27 is formed.
Formed on the upper surface layer of the P-type diffusion layer serves as a base P-type diffusion electrode. In the PMOS-Tr formation region, when formed adjacent to both sides of the gate electrode 8, the source-source of the PMOS-Tr is formed.
Becomes a drain. Such a high concentration diffusion layer is used to form an ohmic contact between the P-type semiconductor layer and the metal electrode 33.

Next, a BPSG film 31 is grown on the entire surface by the CVD method (FIG. 4A). The BPSG film 31 is subjected to a heat treatment to improve the flatness of the wafer surface by reflow.

Then, the metal electrode 33, the diffusion electrode 25,
29 and gate polysilicon 23,
Via hole for contact is anisotropically etched to B
A hole is formed in the PSG film 31 (FIG. 4A).

Thereafter, metal is deposited on the entire surface of the wafer, patterned by photolithography, and etched to form a metal electrode 33 (FIG. 4A).
It is preferable to use aluminum as the metal because of easy processing. Also, because the step coverage is good,
The metal is preferably deposited by sputtering. When the metal electrode 33 is provided on the N-type diffusion electrode 25 and the P-type diffusion electrode 29, ohmic contact is obtained.

Subsequently, an interlayer insulating film 35 is formed on the entire surface of the wafer (FIG. 4B). Since the interlayer insulating film 35 is easy to form, a Si oxide film, a Si nitride film or a multilayer film thereof is preferable.

Next, a light-shielding film is deposited on the interlayer insulating film 35 (FIG. 4B). In order to prevent light from entering the area other than the anode of the APD, the light-shielding film in the area of the APD is removed using a photolithography technique. The light shielding film 37
Metals are preferred because of their good light-shielding properties. Aluminum is particularly preferable as the metal because it is easy to form and process the metal. The light-shielding film 37 includes a vertical PNP-Tr, a vertical NPN-
It is formed two-dimensionally so as to cover Tr, NMOS-Tr and PMOS-Tr, and has an opening of the light shielding film 37 on the anode. When the light-shielding film 37 is a metal film such as aluminum, the light-shielding film 37 can be used as a wiring connecting elements.

Further, a passivation film 39 is deposited on the entire surface of the wafer (FIG. 4B).

According to the method described above, the BiCMOS built-in light receiving semiconductor device (FIG. 4B) can be manufactured. That is, as shown in FIG. 4B, from the left side to the right side of the BiCMOS built-in light receiving semiconductor device, a vertical PNP-Tr formation region, a PMOS-Tr formation region, an NMOS-Tr formation region, and a vertical NPN-Tr formation region. And an APD formation region, an N-type first buried layer 3 formed on the upper surface of the P-type semiconductor substrate 1 in the APD formation region and the vertical PNP-Tr formation region, and the P-type semiconductor substrates 1 and N Type 1
On the buried layer 3, an APD formation region, a vertical PNP
-Tr formation region, NMOS-Tr formation region, PMOS-
The P-type first semiconductor layer 5 formed in the Tr formation region and the vertical NPN-Tr formation region, and the upper surface layer in the P-type first semiconductor layer 5 in the PMOS-Tr formation region and the vertical NPN-Tr formation region The N-type second buried region 7 formed and the P-type layer formed on the upper surface layer in the P-type first semiconductor layer 5 on the N-type first buried layer 3 in the vertical PNP-Tr formation region.
A first P-type buried layer 9, a P-type second buried layer 11 formed on the N-type first buried layer 3 in the APD formation region and on the upper surface layer in the P-type first semiconductor layer 5, First semiconductor layer 5, P-type first buried layer 9, P-type second buried layer 1
P-type second semiconductor layer 13 formed on 1 and N-type second buried region 7 and N-type first semiconductor formed on N-type second buried region 7 in the vertical NPN-Tr formation region A layer 15, an N-type second semiconductor layer 17 formed in contact with the N-type second buried region 7 in the PMOS-Tr formation region,
An N-type third semiconductor layer 19 formed on the P-type first buried layer 9 in the vertical PNP-Tr formation region;
An N-type fourth semiconductor layer 25 formed on the upper surface of the N-type first semiconductor layer 15 in the formation region, and an N-type fourth semiconductor layer 25 formed on the surface of the N-type first semiconductor layer 15 in the vertical NPN-Tr formation region; A P-type third semiconductor layer 27 formed so as to surround the bottom and side surfaces of the N-type fourth semiconductor layer 25, and a P-type layer formed on the surface of the N-type third semiconductor layer 19 in the vertical PNP-Tr formation region. Mold fourth semiconductor layer 29.

The vertical PNP-Tr is the same as the vertical PNP-Tr.
P-type first buried layer 9 in the NP-Tr formation region, P-type first buried layer 9
The semiconductor layer 5 and the P-type second semiconductor layer 13 are used as collectors, the N-type third semiconductor layer 19 is used as a base, and the P-type fourth semiconductor layer 29 is used as an emitter. Also, vertical NP
N-Tr is the N-type second of the vertical NPN-Tr formation region.
The buried region 7 and the N-type first semiconductor layer 15 are used as a collector, the P-type third semiconductor layer 27 is used as a base, and the N-type fourth semiconductor layer 25 is used as an emitter. Furthermore, APD
Are the P-type first semiconductor layers 5 and P in the APD formation region.
The second semiconductor layer 13 is used as an anode, and the first buried layer 3 in the APD formation region is used as a cathode.

Further, the collector of the vertical PNP-Tr contacts the N-type first buried layer 3 in the vertical PNP-Tr formation region and surrounds the P-type first buried layer 9.
-Type second buried region 7 and N-type second buried region 7
The anode of the APD is separated from the N-type fifth semiconductor region 41 formed on and in contact with the N-type fifth semiconductor region 41.
An N-type second buried region 7 formed on the first type buried layer 3 and surrounding the P-type second buried layer 11;
BiCMOS separated by N-type sixth semiconductor region 42 formed in contact with N-type second buried region 7
The built-in light receiving semiconductor device (FIG. 4B) can be manufactured.

Hereinafter, the planar configuration of the BiCMOS built-in light receiving semiconductor device of the present invention will be described. FIG. 5 is a plan view of the BiCMOS built-in light-receiving semiconductor device manufactured by the above-described manufacturing method, and FIG. 4B is a cross-sectional view taken along line aa ′ of FIG. The illustration of the metal electrode 33 and the light shielding film 37 is omitted so that the arrangement of each semiconductor layer can be clearly shown. In FIG. 5, a vertical PNP-Tr formation region, a PMOS-Tr formation region, an NMOS-Tr formation region, a vertical NPN-Tr formation region, and an APD formation region are arranged from the left side to the right side of the substrate 1.

In the vertical PNP-Tr formation region, the N-type fourth
The semiconductor layer 19 (base, B1) is provided so as to surround the P-type diffusion layer 29 (emitter, E1), and the P-type first buried layer 9, the P-type second semiconductor layer 13 (collector, C1)
Is provided so as to surround the base 19, so that PN
A structure made of P is formed. With this PNP structure,
The collector resistance is reduced by the P-type first buried layer 9,
In addition, a vertical PNP-Tr in which an amplification current flows in the vertical direction is formed. In addition, since the base profile and the formation of the emitter junction can be controlled independently of other elements, the current amplification factor,
Early voltage and frequency characteristics can be improved. Further, the N-type second semiconductor region 7 formed on the N-type first buried layer 3 and the N-type fifth semiconductor region 7 formed on the region 7 are formed.
A collector isolation region is constituted by the semiconductor region 41;
Moreover, since the P-type first buried layer 9 is surrounded by the band-shaped closed collector isolation region, the P-type first buried layer 9,
The P-type first semiconductor layer 5 and the P-type second semiconductor layer 13 are separated. Therefore, an independent potential can be given to the collector. The diffusion electrode 29 of the collector (C1)
Is preferably formed around the base (B1) in order to reduce the collector resistance.

In the PMOS-Tr formation region, an N-type diffusion layer 25 is also provided in a region in the N-type second semiconductor layer 17 in order to fix the potential of the substrate gate portion. By providing a large number of diffusion electrodes as described above, the potential of the substrate gate portion can be made uniform and stable. The source and the drain are composed of the P-type fourth semiconductor layer 29 formed in the active region divided into two by the gate electrode 23. Source and drain 29
Is preferably formed in a self-aligned manner.

In the NMOS-Tr formation region, a P-type diffusion layer 29 is provided also in a region in the P-type second semiconductor layer 13 in order to fix the potential of the substrate gate portion. By providing a large number of diffusion electrodes as described above, the potential of the substrate gate portion can be made uniform and stable. The source and the drain are formed of a fourth N-type diffusion layer 25 formed in the active region divided into two by the gate electrode 23. Source and drain 25
Is preferably formed in a self-aligned manner.

In the vertical NPN-Tr formation region, the P-type third
The semiconductor layer 27 (base, B2) is provided so as to surround the periphery of the N-type diffusion layer 25 (emitter, E2).
Since the semiconductor layer 15 (collector, C2) is provided so as to surround the base 27, a structure made of NPN is formed. With this NPN structure, a collector resistance is reduced by the N-type second buried region 7, and a vertical NPN-Tr in which an amplification current flows in the vertical direction is formed. Further, since the formation of the base profile and the emitter junction can be controlled independently of other elements, the current amplification factor, the early voltage, the frequency characteristics, and the like can be improved. Further, the N-type second buried region 7 and the N-type first semiconductor layer 15 are surrounded by the P-type first semiconductor layer 5 and the P-type second semiconductor layer 13, so that an independent potential can be applied to the collector. it can.
The diffusion electrode 25 of the collector (C2) is preferably formed so as to surround the base (B2) in order to reduce the collector resistance.

In the APD formation region, the P-type first semiconductor layer 5
A region composed of the P-type second semiconductor layer 13 and the P-type second semiconductor layer 13 is provided in the anode region as a light absorbing layer, and the P-type fourth semiconductor layer 29 provided on the upper surface layer in the P-type second semiconductor layer 13 serves as an anode (A). It becomes an electrode. Since the cathode (K) is composed of the N-type first buried layer 3 provided on the P-type substrate 1,
And is drawn out to the wafer surface by the cathode drawing-out area. This lead-out area is an N-type first
N-type second semiconductor region 7 formed in contact with buried layer 3 and N-type sixth semiconductor region 4 formed on this region 7
And 2. If the cathode extraction region is formed in a band-like closed region surrounding the anode (A) electrode 29 or the P-type second buried layer 11, the light absorption regions 5 and 13 contribute to the region which contributes as the light absorption region. It is separated as an area that does not. Thus, in addition to the cathode, the anode is also separated. That is, the cathode extraction region can also be used as the anode separation region. In addition,
In order to stabilize the potential around the cathode, it is preferable to surround the cathode with a guard ring composed of a P-type diffusion electrode 29.

The conditions for forming the N-type third semiconductor layer 19, which is the base of the vertical PNP-Tr of FIG.
In order to increase the speed of Tr, the conditions for forming the gate portion of the PMOS-Tr substrate may be changed. In this case, phosphorus (P ⁺ ) is used as the impurity, and the dose is preferably 3 × 10 ¹³ cm ⁻² or more and 3 × 10 ¹⁴ cm ⁻² or less. As described above, when the base is formed independently of the other steps, the characteristics of the vertical PNP-Tr can be controlled independently.

The N-type third semiconductor layer 19 is formed of an N-type first semiconductor layer.
The ion implantation for forming the semiconductor layer 15 and the ion implantation for forming the N-type second semiconductor layer 17 may be performed together. In this way, the partial ion implantation amount is increased, but the vertical type PNP-Tr of h _ef decreases breakdown voltage is increased, can be selected depending the purpose and situation.

Further, the N-type third semiconductor layer 19 is formed by performing ion implantation after a heat step of forming a vertical NPN-Tr and a PMOS-Tr, followed by a heat step of a base of the vertical NPN-Tr. Activation may also be performed in combination. In this way, a shallow junction of 0.5 μm to 1 μm is obtained,
A high-speed PNP-Tr with a small base width can be formed.

FIG. 6 is a plan view when two APDs are arranged. When an independent P-type fourth semiconductor layer 29 is provided on the upper surface layer of the P-type second semiconductor layer 13 and its periphery is surrounded by a cathode extraction region, a common cathode (K) and independent anodes (A1, A2) are formed. APD can be configured. If these are connected in parallel, the series resistance of the APD can be reduced. If a signal processing circuit is connected to each of the plurality of APDs, an arrayed light receiving semiconductor device can be configured.

FIG. 7 is a plan view showing a case where two APDs each having an independent cathode are arranged. P-type second semiconductor layer 1
3, an independent P-type fourth semiconductor layer 29 is provided on the upper surface layer of
When each periphery is surrounded by a cathode extraction region, independent cathodes (K1, K2) and independent anodes (A
1, A2). Multiple A
If a signal processing circuit is connected to each of the PDs, an arrayed light receiving semiconductor device can be configured. In addition, since there are independent cathodes, restrictions on circuit connection can be relaxed.
Furthermore, if the concentration of the P-type second buried layer 11 is different in each APD, APDs having different characteristics can be formed on the same substrate 1.

FIG. 8A is a plan view when two APDs are arranged, and FIG. 8B is a cross-sectional view taken along the line bb '. In FIG. 8A, a single rectangular P-type second buried layer 11 is provided at the interface between the P-type first semiconductor layer 5 and the P-type second semiconductor layer 13, and is located on the buried layer 11. , P-type second
Two rectangular separated P-type fourth semiconductor layers 29 are provided on the upper surface layer of the semiconductor layer 13 in proximity to each other. Further, the periphery of these elements is surrounded by a common cathode lead-out area, and the APD
Is configured. In such an APD, when a high voltage is applied between the anode and the cathode to completely deplete the P-type second semiconductor layers 5 and 13, the two P-type fourth semiconductor layers 29 are electrically depleted by the depletion layers. Is separated into Therefore, it operates as an APD having a common cathode and two electrically separated anodes. In this way, since a plurality of anodes can be arranged close to each other, a small APD having independent anodes can be configured.

As shown in the plan views of FIG. 5 to FIG. 7 and FIG. 8A, the semiconductor portion of the APD to which a high voltage is applied may have rounded corners. Is preferred. In this way, the electric field can be reduced,
The breakdown voltage of the APD can be improved.

Although not described with reference to the drawings, a vertical NPN
The emitter of -Tr may be formed in a step different from that of the source / drain 25 of the NMOS-Tr. This step is shown in FIG.
It can be performed in a step corresponding to (c). For example, removing the oxide film of the emitter portion, depositing polysilicon on the entire surface of the wafer, introducing impurities into the polysilicon, forming a pattern using photolithography technology, and further diffusing the impurities from the polysilicon. An emitter may be formed. The impurity is preferably introduced into the polysilicon by ion implantation using arsenic (As ⁺ ) and phosphorus (P ⁺ ). In this manner, a high-concentration N-type semiconductor layer having a shallow junction can be formed in the upper surface layer in the third P-type semiconductor layer 27. If this is used as an emitter, a high-performance vertical NPN-Tr can be formed. .

The emitter of the vertical PNP-Tr is P
It may be formed in a step different from that of the source / drain 29 of the MOS-Tr. Since this emitter can be formed by the same method as the emitter of the vertical NPN-Tr, the details are omitted.

[0078]

As described in detail above, according to the present invention, the anode and the cathode are separated, and the APD having high sensitivity from the near-infrared region to the visible region can be converted into the same PPD.
A light receiving semiconductor device with a built-in BiCMOS integrated on a mold substrate can be provided.

Further, according to the present invention, a vertical PNP-Tr having a collector separated from a substrate, having a large allowable current, having a small Early effect and a small collector resistance, and having improved frequency characteristics is provided. A vertical NPN-Tr having a collector can be provided on the same P-type substrate to provide a BiCMOS built-in light receiving semiconductor device.

Therefore, since a complementary circuit can be used in the signal processing circuit of the APD, the gain of the amplifier circuit can be increased and the speed can be increased, and the power supply voltage dependence of the circuit operation can be reduced.

Further, if the APD and its signal processing circuit are arranged in a pair and arranged in an array, it is possible to realize an arrayed APD with a high signal processing speed.

Further, if a BiCMOS circuit is used, an APD with temperature compensation can be realized.

That is, when the light receiving semiconductor device is used, an optical conversion element having an amplifier for converting an optical signal into an electric signal in an optical device, an optical system, communication, or the like, and a semiconductor capable of processing the signal by an analog / digital circuit Equipment can be provided.

[Brief description of the drawings]

FIGS. 1A to 1C are cross-sectional views in each step for describing a method of manufacturing a BiCMOS built-in light receiving semiconductor device.

FIGS. 2A to 2C are cross-sectional views in each step for describing a method for manufacturing a BiCMOS built-in semiconductor light receiving device.

FIGS. 3A to 3C are cross-sectional views in each step for explaining a method of manufacturing a BiCMOS built-in light receiving semiconductor device.

FIGS. 4A and 4B are cross-sectional views in each step for describing a method of manufacturing a BiCMOS built-in semiconductor light receiving device.

FIG. 5 is a plan view of the BiCMOS built-in light receiving semiconductor device corresponding to FIG. 4B.

FIG. 6 is a plan view of an APD having a different structure.

FIG. 7 is a plan view of an APD having a different structure.

FIG. 8A is a plan view of an APD having a different structure. FIG. 8B shows an APD having a different structure.
3 is a sectional view taken along the line bb ′ of FIG.

[Explanation of symbols]

Reference Signs List 1 ... P-type Si substrate, 3 ... N-type first buried layer, 5 ... P-type first semiconductor layer, 7 ... N-type second buried region, 9 ... P-type first buried layer, 11 ... P-type second buried layer Layers: 13: P-type second semiconductor layer, 15: N-type first semiconductor layer, 17: N-type second semiconductor layer, 19: N-type third semiconductor layer, 21: field oxide film, 23: gate polysilicon, 25 ... N-type fourth
Semiconductor layer, 27: P-type third semiconductor layer, 29: P-type fourth semiconductor layer, 31: BPSG film, 33: metal electrode, 35 ...
Interlayer insulating film, 37: light shielding film, 39: passivation film, 41: N-type fifth semiconductor region, 42: N-type sixth semiconductor region

Claims (4)

[Claims] An N-type first buried layer formed in an avalanche photodiode formation region and a vertical PNP transistor formation region on an upper surface layer in a P-type semiconductor substrate; the P-type semiconductor substrate and the N-type first burying On the layer, the avalanche photodiode formation region,
A P-type first semiconductor layer formed in the vertical PNP transistor formation region, a MOS N-channel transistor formation region, a MOS P-channel transistor formation region and a vertical NPN transistor formation region; and the MOS P-channel transistor formation region An N-type second buried region formed on a top surface layer in the P-type first semiconductor layer of the vertical NPN transistor formation region; and an N-type first buried layer of the vertical PNP transistor formation region. A P-type first buried layer formed on an upper surface layer in the P-type first semiconductor layer; and the P-type first semiconductor on the N-type first buried layer in the avalanche photodiode formation region. A P-type second buried layer formed on an upper surface layer in the layer; the P-type first semiconductor layer; the P-type first buried layer; A P-type second semiconductor layer formed on the N-type second buried layer and the N-type second buried region; and an N-type second semiconductor layer formed on the N-type second buried region in the vertical NPN transistor formation region. One semiconductor layer; an N-type second semiconductor layer formed in contact with the N-type second buried region of the MOS P-channel transistor formation region; and the P-type first buried layer of the vertical PNP transistor formation region. An N-type third semiconductor layer formed thereon, an N-type fourth semiconductor layer formed on an upper surface of the surface of the N-type first semiconductor layer in the vertical NPN transistor formation region, and a formation of the vertical NPN transistor A P-type third semiconductor layer formed on a surface of the region in the N-type first semiconductor layer and surrounding a bottom surface and a side surface of the N-type fourth semiconductor layer; N A P-type fourth semiconductor layer formed on an upper surface of the third semiconductor layer. The P-type first buried layer of the vertical PNP transistor forming region, A first semiconductor layer and the second P-type semiconductor layer serving as collectors; a third semiconductor layer serving as the N-type base;
The vertical NPN transistor is constituted by using the semiconductor layer as an emitter, and the N-type second buried region and the N-type first semiconductor layer in the vertical NPN transistor forming region are used as collectors, and the P-type third semiconductor layer is used as a collector. The avalanche photodiode is configured as a base, the N-type fourth semiconductor layer is used as an emitter, and the avalanche photodiode is configured such that the P-type first semiconductor layer and the P-type second semiconductor layer in the avalanche photodiode forming region are used as anodes. The N-type first buried layer in the photodiode forming region is configured as a cathode, and the collector of the vertical PNP transistor is in contact with the N-type first buried layer in the vertical PNP transistor forming region, and Said N-type second buried region formed surrounding said first buried layer; Of the N-type second
The anode is separated from an N-type fifth semiconductor region formed in contact with the buried region, and the anode is in contact with the N-type first buried layer in the avalanche photodiode formation region and forms the P-type second buried layer. A light receiving semiconductor with a built-in BiCMOS, which is separated by the N-type second buried region formed so as to surround and the N-type sixth semiconductor region formed in contact with the N-type second buried region. apparatus. 2. The built-in BiCMOS according to claim 1, wherein the N-type third semiconductor layer serving as a base of the vertical PNP transistor is formed in common with the N-type second semiconductor layer. Light receiving semiconductor device. 3. A light shielding film is provided on the vertical PNP transistor, the vertical NPN transistor, the MOS N-channel transistor and the MOS P channel transistor, and the light shielding film is provided on an anode of the avalanche photodiode. The light receiving semiconductor device with a built-in BiCMOS according to claim 1, further comprising an opening. 4. The N-type fifth semiconductor region and the N-type sixth semiconductor region include the N-type first semiconductor layer and the N-type fifth semiconductor region.
2. The BiCM according to claim 1, wherein the BiCM is formed in the same process as at least one of the mold second semiconductor layers.
Light-receiving semiconductor device with built-in OS.