JPH1145945A - Semiconductor integrated circuit and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To respond to reduction in reverse voltage Vt* by positioning a source/drain area of a part of transistors of a level shift circuit backward with intention to increase the ON resistance. SOLUTION: N-MOS 22 and P-MOS 15 of a high dielectric breakdown part 10 are formed on a substrate 12 and in a first N type well area 14. P-MOS 25 and N-MOS 18 of a low dielectric breakdown part 11 are formed in a second N type well area 16 and a P type well area 17. A source/drain area 21 of the N-MOS 22 in the high dielectric breakdown part 10 is positioned backward (by a CAD design) from the mask end for forming a selective oxide film 26 in such a way that the end of the diffusion area comes into contact with the second selective oxide film 26. In this way, an effective gate length is increased and a part of the thick second selective oxide film 26 functions as a part of a gate oxide film.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit having a built-in level shifter circuit for converting a low-voltage signal into a high-voltage signal, and a method of manufacturing the same.

[0002]

2. Description of the Related Art In an LCD driver IC or the like, a low voltage system (for example, 5 V) processed by a CPU or a video signal processing circuit is used.
Is converted into a high-voltage (for example, 40 V) signal by a level shift circuit, and an output signal for driving an LCD panel is output by the converted high-voltage signal. One level shifter circuit is required for each dot line of the LCD panel, and as the screen size increases, many level shift circuits are naturally replaced by one IC.
It is necessary to store it inside.

FIG. 9A is a diagram showing a configuration of the level shift circuit 1. As shown in FIG. In the figure, a MOS transistor Q
1, Q2, Q3, and Q4 are high-breakdown-voltage transistors, and Q5 and Q6 are low-breakdown-voltage transistors. Transistors Q5 and Q6 constitute inverter 2 for generating inverted signal * φ. VDD is the power supply voltage (+5 V), V
SS is the source potential (0 V) of the low breakdown voltage system, and VSSL
Is the source potential (−40 V) of the high breakdown voltage system.

[0004] The DC operation of this circuit is as follows.
Now, when the input signal φ is at the L level (0 V), the transistor Q1 turns on, the transistor Q2 to which the inverted signal * φ is applied turns off, the transistor Q3 turns off, and the transistor Q4 turns on. Since the transistor Q1 is ON, the potential of the output terminal a becomes VDD (5 V).
On the other hand, when the input signal φ is at the H level (+5 V), the transistor Q1 is turned off, the transistor Q2 to which the inverted signal * φ is applied is turned on, the transistor Q3 is turned on, and the transistor Q4 is turned off. Transistor Q3 is ON
Therefore, the potential of the output terminal OUT is VSSL (−4
0V).

Therefore, as shown in FIG. 9B, this circuit receives the input signal φ of the VDD / VSS system (+5 V / 0 V).
The signal waveform 3 of * φ is changed to the VDD / VSSL system (+5 V / −
An operation of converting the signal into an output signal 4 of 40 V) is performed. By the way, in order for the level shift circuit 1 to perform the inverting operation following the inverting operation of the inverter 2, for example, a value of about half of the output amplitude within the range of the output amplitude of the inverter 2 (1/2)
(VDD), the level shift circuit 1 needs to invert. For example, if the level shift circuit performs an inversion operation at −20 V, it becomes impossible to perform the inversion operation of the level shift circuit with input signals φ and * φ having amplitudes of 0 to +5 V.

Referring to FIG. 10A, the inverted voltage Vt * when the level shift circuit 1 performs the inverting operation has an output voltage (VDDL) when the input / output characteristics (Vin-Vout) of the circuit are drawn. −VSS) indicates the input voltage when the value becomes half of the value. Now, consider the case where the transistors Q1 and Q3 are replaced with simple resistors as shown in FIG. still,
r1 is the ON resistance of the transistor Q1, and r3 is the ON resistance of the transistor Q3. The voltage Vout at the output terminal OUT of this circuit can be expressed as follows: Vout = (VDD−VSSL) · r3 / (r1 + r3) (1)

For example, the inverted voltage Vt * when r1 = r3
Is assumed to be Vt * 1 in FIG. In order to move the input / output characteristics in the left direction (Vt * 2) in the drawing, the output voltage Vout may be immediately reduced with an increase in the input voltage Vin. Therefore, the ON resistances r1 and r3 may be used.
It can be understood that it is sufficient to design the relationship in accordance with the expression (2). r1 >> r3 (2) On the other hand, in order to move the inversion voltage in the direction (Vt * 3) on the right side of the drawing, the output voltage Vout almost decreases with the fluctuation of the input voltage Vin. Since it is sufficient that the ON resistances r1 and r3 are designed to satisfy the relation of the equation (3).

R1 << r3 (3) This means that the inversion operation is performed only by increasing the input voltage Vin to near the maximum amplitude value.
Although detailed calculations are omitted, designing the inversion voltage Vt * of the level shift circuit 1 in FIG. 9A to be half of (VDD−VSS), that is, about 2.5 V is equivalent to +5 V to −40.
When the potential difference is as large as V, the inverted voltage Vt * is changed to VDD (+
5V) means that the design is made very close to the side. Therefore, based on these considerations, in order for the level shift circuit 1 to operate stably, the ON resistance of the transistor Q1 << the ON resistance of the transistor Q3 in accordance with the equation (3) << (4) the ON resistance of the transistor Q2 << It is necessary to satisfy both the ON resistance of the transistor Q4 (5). Therefore, conventionally,
By adjusting the gate width / gate length (W / L) ratio of the transistor, the above equations (4) and (5) were satisfied.

[0009]

In order to satisfy the recent demands for higher speed and lower power consumption of electronic equipment, integrated circuits are required to have smaller design rules and lower operating voltages (5.
V → 3V). Therefore, the maximum amplitude of the input signal φ of the level shift circuit is also small. For example, in order to correspond to a power supply voltage VDD = 3 V system device, the inverted voltage Vt * of the level shift circuit 1 is increased from about 2.5 V to 1. It must be further reduced to about 5V. This means that the potential difference between the inversion voltage Vt * and the power supply potential VDD is further reduced (shifted to the power supply potential VDD side). Therefore, according to the above consideration, it is necessary to satisfy the equations (4) and (5). , The ON resistance of the transistors Q3 and Q4 must be further increased and the ON resistance of the transistors Q1 and Q2 must be further reduced.

However, gate width / gate length (W /
The method of changing the ratio L) has the disadvantage that the chip size of the IC increases because the transistor size increases in order to further increase the ratio. Especially for LCD driver applications, etc., many level shift circuits (1
Since it is integrated, the increase in the size of one transistor immediately results in a significant increase in the chip size.

[0011]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and it has been proposed that the ends of the source / drain regions of transistors Q3 and Q4 (more precisely, the ends of the mask on CAD data) should be formed. End of second selective oxide film (also CAD
By retreating from the mask edge on the data)
Increasing the substantial gate length of transistors Q3 and Q4,
In addition, the threshold value Vth is increased more than the gate length is increased.

The following shows the drain current Id of the MOS transistor. Id = μ · Vds · ε · W · (Vgs−Vth) / (L · tox) (6) where μ is the electron mobility, Vds is the source-drain voltage, and Vgs is the gate-source voltage. , Ε is a dielectric constant, W is a gate width, L is a gate length, and tox is a gate oxide film thickness.

The ON resistance r depends on the drain current Id and the source current.
Since it can be expressed by the drain-to-drain voltage Vds, after all, from equation (6), r = Vds / Id∝L (7) r = Vds / Id∝tox (8) That is, the ON resistance can be increased by increasing the gate length, and the ON resistance can be increased by increasing the gate oxide film thickness.

According to the present invention, the gate length can be substantially increased by retreating the source / drain region ends,
Moreover, since a part of the second selective oxide film functions as a gate oxide film, the thickness is substantially equal to the thickness of the gate oxide film. Therefore, the conditions of the expressions (4) and (5) can be satisfied without extremely increasing the ratio of gate width / gate length (W / L).

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a cross-sectional view showing a semiconductor integrated circuit in which a high breakdown voltage portion 10 and a low breakdown voltage portion 11 are integrated according to the present invention. In FIG.
Is a P-type silicon single crystal substrate, 13 is a first selective oxide film for isolating each element, and 14 is formed to constitute a P-channel MOSFET (hereinafter referred to as a P-MOS 15) of the high breakdown voltage section 10. N-type first well region, 1
Reference numeral 6 denotes an N-type second well region formed to constitute a MOSFET element of the low withstand voltage section 11, and 17 denotes a low withstand voltage section 1.
1 N-channel MOSFET (hereinafter referred to as N-MOS 18
, A P-type well region formed on the surface of the second well region 16, a polysilicon gate electrode 19, a P + source / drain region 20 of the P-MOS 15 of the high breakdown voltage portion 10, and 21. Is N + of an N-channel MOSFET (hereinafter referred to as N-MOS 22) of the high breakdown voltage portion 22.
A source / drain region, 23 is an N + source / drain region of the N-MOS 18, and 24 is a P + source / drain region of the P-channel MOSFET 25 (hereinafter referred to as P-MOS 25) of the low breakdown voltage section 11.

The elements 15 and 22 of the high withstand voltage section 10 employ a so-called offset drain structure in which the source / drain regions 20 and 21 are not self-aligned by gates but use diffusion regions with a low impurity concentration. Also,
A second selective oxide film 26 having a thickness of about 10,000 ° is provided at a boundary portion between the channel portion below the gate electrode 19 and each of the source / drain regions 20 and 21. This is a structure for increasing the breakdown voltage between the gate electrode 19 and the drain region by using the second selective oxide film 26, and has a different structure from the low breakdown voltage portion 11. The gate electrode 19 is
And a region having a small oxide film thickness in a region surrounded by the selective oxide film 26 becomes a substantial gate oxide film for forming a channel.

A minimum potential VSSL (for example, -40 V) which is output after being shifted in level is applied to the semiconductor substrate 12 as a substrate bias. The power supply potential VDD (for example, +3 V) is applied to the N-type first well region 14 of the high breakdown voltage section 10 as a back gate bias of the P-MOS 15. The N-type second well region 16 of the low-breakdown-voltage portion 11 also has a role of separating the potential from the high-breakdown-voltage portion 10, and also applies the power supply potential VDD as a bias for the P-MOS 25. Then, in the P-type well region 17 of the low breakdown voltage portion 11,
A power supply potential VSS (for example, 0 V) is applied as a bias for the N-MOS 18.

The low withstand voltage section 11 is designed to have a withstand voltage of about 5 V, and the gate oxide film 27 has a thickness (tox3) of about 400 to 500 °. On the other hand, the gate oxide film 28 of the high breakdown voltage portion 10 has a gate breakdown voltage (V
gs, Vgd), the film thickness (tox2) is 2
It is extremely thick, 000-3000３. FIG. 2 is an enlarged sectional view of the high withstand voltage section 1. A P + type contact region 30 is formed on the surface of the P type source / drain region 20, and an N + type contact region 31 is formed on the surface of the N type source / drain region 23. The P-MOS 15 is
The end 32 of the oxidation-resistant film on the CAD and the end 33 of the diffusion window of the source / drain region 20 on the CAD are formed so as to substantially coincide with each other, and the end of the source / drain region 20 extends to the gate oxide film 28. ing. In contrast, N-
The MOS 22 has the end 33 of the diffusion window of the source / drain region 20 on the CAD receded rearward by about 0.5 to 2 μ with respect to the end 32 of the oxidation-resistant film on the CAD. As a result, the source / drain region The end of 23 is A
Are formed in such a positional relationship as to come into contact with the second selective oxide film 26 at the point of the above.

Therefore, the effective gate length 34 of the N-MOS 22 becomes larger than the design on the CAD, and the ON resistance of the N-MOS 22 can be increased according to the equation (7). Furthermore,
The end of the source / drain region 23 is the second selective oxide film 26
, The gate oxide film 28 does not have a uniform thickness, and a part of the second selective oxide film 23 functions as a gate oxide film. Since the relationship between the thickness of the gate oxide film and the ON resistance is as shown by the equation (8), the ON resistance of the N-MOS 22 can be further increased. The amount of increase can be made larger (as long as the gate oxide film thickness is the same) than in a device simply designed with a substantial gate length of 34.

The circuit configuration of the level shift circuit 1 according to the present invention is the same as the level shift circuit described in the conventional example. Hereinafter, the correspondence between each element configured as described above and the level shift circuit 1 in FIG. 7A will be described. First, the N-MOS 18 and the P-MOS 25 of the low withstand voltage section 11 are elements for configuring main circuit functions inside the same IC.
Further, it is an element for configuring the transistors Q5 and Q6 of the inverter circuit 2 serving as an input unit of the level shift circuit 1. Since this is not a place where a high voltage is applied, the design withstand voltage is low.

The P-MOS 15 of the high breakdown voltage section 10 forms the transistors Q1 and Q2 of the level shift circuit 1. Similarly, the N-MOS 22 of the high breakdown voltage section 1 forms the transistors Q3 and Q4 of the level shift circuit 1. Since a high potential of about 40 V is applied between the gate and the drain, techniques such as disposing the second selective oxide film 26 and increasing the thickness of the gate oxide film 28 are employed. This also has the role of increasing the inversion voltage Vth (threshold) of the N-MOS 22 and increasing the ON resistance as compared with that of the low breakdown voltage section.

According to the present invention, the transistors Q3, Q4
As the source / drain region 23 is retracted by CAD design to increase the effective gate length 34 and the N-MOS 22 in which the ON resistance is further increased, the gate width / gate length (W / L) is satisfied without satisfying the expressions (4) and (5) without extremely increasing the ratio of the level shift circuit 1.
Can be operated stably. Therefore, the inversion voltage Vt * of the level shift circuit 1 can be reduced without greatly increasing the transistor size.

Hereinafter, a method of manufacturing the semiconductor integrated circuit shown in FIG. 1 will be described. First, referring to FIG. 3A, a P-type silicon semiconductor substrate 12 is prepared, and its surface is oxidized.
A selection mask is formed by a photoresist process and an etching process, phosphorus (P) is ion-implanted using the selection mask, and thermal diffusion is performed to form a first N of the high breakdown voltage portion 10.
Form a well region 14 and a second N-type well region 16 of the low breakdown voltage portion 11.

Referring to FIG. 3B, a diffusion mask is similarly formed by a photoresist step and an etching step.
Boron (B) is ion-implanted using a diffusion mask, and thermal diffusion is performed, so that the P-type well region 17 of the low breakdown voltage portion 11 is formed.
To form Referring to FIG. 4A, a resist mask is formed on substrate 12 by a photoresist process, phosphorus (P) is ion-implanted, and after the resist mask is changed, boron (B) is ion-implanted. Then, by heat diffusion, the source / drain regions 20 of the high withstand voltage portion 10,
21 are formed. In order to have an LDD structure, the high withstand voltage section 10
The impurity concentration of the source / drain regions 20 and 21 is lower than that of the low breakdown voltage portion 11.

Referring to FIG. 4B, a pad oxide film is formed by thermal oxidation after removing the oxide film on the surface of substrate 12, and a silicon nitride film is formed thereon by CVD. By patterning the silicon nitride film, the first selective oxide film 13 is formed.
Then, an oxidation-resistant mask 34 having an opening at the location of the second selective oxidation film 26 is formed. In the N-MOS 22, FIG.
The distance between the mask end 33 for forming the source / drain region 21 used in the step (A) and the mask end 32 when the silicon nitride film is patterned is adjusted by design on a CAD drawing. Specifically, the mask end 3 of the oxidation resistant film 34
2, the mask edge 33 of the source / drain region 21
Is retracted by about 0.5 to 1.5 μ. P-MOS
In a normal design such as 15 the direction in which the inversion voltage is desired to be reduced, the mask end 33 and the mask end 3
2 and 2. The pattern size of the oxidation-resistant mask 34 is equal to the designed gate width W.

Referring to FIG. 5A, the first selective oxide film 13 and the second selective oxide film 26 are formed on the surface of the substrate 12 not covered with the silicon nitride film 34 by thermally oxidizing the entire substrate. Is formed, and the oxidation-resistant film 34 is removed. NM
The source / drain region 21 of the OS 22 is
Is formed in such a positional relationship that the end of the diffusion region comes into contact with the second selective oxide film 26.

Referring to FIG. 5B, the whole is 1000
A gate oxide film 28 (first gate oxide film) having a thickness of 2000 to 3000 ° is formed in the active portion by performing thermal oxidation at 10 ° C. for about 10 hours. Referring to FIG. 6 (A), the high breakdown voltage portion 10 is covered with a photoresist film, and the oxide film is removed with hydrofluoric acid.
The silicon surface of the low breakdown voltage portion 11 is exposed so that the gate oxide film 28 is left.

Referring to FIG. 6B, the photoresist film is removed and the whole is thermally oxidized at 1000 ° C. for 1 to 2 hours, so that the exposed silicon surface has a film pressure of 400 to 500.
The gate oxide film 27 (second gate oxide film) of the low breakdown voltage portion 11 of about Å is formed. Referring to FIG. 7 (A), after ion implantation for threshold value adjustment is performed, gate polysilicon is deposited by a CVD method, and the polysilicon layer is etched using a photoresist to form gate electrode 1.
9 is formed.

Referring to FIG. 7B, a resist mask is formed on substrate 12, and boron (B) for forming P + source / drain regions 24 is ion-implanted. Ion implantation is also performed on the P-type source / drain region 20 of the high breakdown voltage portion 10 in a superimposed manner. Further, the resist mask is changed, and arsenic (As) for forming the N + source / drain regions 23 is ion-implanted. Ion implantation is also performed on the N-type source / drain region 21 of the high breakdown voltage portion 10 while overlapping. Then, an annealing process for activating the ion-implanted impurities is added. Thereafter, circuit connection between the elements is performed by forming an electrode wiring (not shown).

As described above, N- on the CAD drawing
Mask end 33 of source / drain region 21 of MOS 22
2 so that the end of the diffusion region of the source / drain region 21 becomes the second selective oxide film 26 as shown in FIG.
Can be manufactured in contact with In addition, it is ON according to the equation (8).
The resistance also depends on the gate oxide film thickness tox.
In order to satisfy the expression (5), one of the means is to reduce the ON resistance of the P-MOS 15. Therefore, the high withstand voltage section 1
By reducing the gate oxide film thickness tox of the P-MOS 15 of 0, the expressions (4) and (5) can be more easily satisfied. Therefore, after the steps of FIGS. 3 to 5, FIG.
Referring to FIG. 8, when the first gate oxide film 28 is selectively removed, the corresponding portion of the P-MOS 15 of the high withstand voltage portion 10 is also removed, and with reference to FIG. When the second gate oxide film 29 is formed, the thin gate oxide film can be given to the P-MOS 15 by forming the second gate oxide film 29 also at a corresponding portion of the P-MOS 15. Subsequent steps are the same as in FIG. The transistors Q1 and Q2, which are input stages of the level shift circuit 1, are not the places where a high voltage is applied, so that there is no problem with the withstand voltage caused by reducing the gate oxide film thickness. Further, a thin gate oxide film can be provided without adding a new process.

FIG. 11 shows another example of the level shift circuit 1. 9 is different from the level shift circuit of FIG. 9 in that transistors Q7 and Q8 are added, and is the same as the inverter circuit 2 and the like. The transistors Q7 and Q8 are
The source is connected to the power supply potential VSSL side, the drain is connected to the sources of the transistors Q3 and Q4, and the gate has input signals φ and * φ applied to the transistors Q1 and Q2.
Is applied. Further, it is constituted by the N-MOS 22 of the high breakdown voltage section 10 of FIG.

When the input signal φ is at the L level, the transistor Q1 turns on, the transistors Q3 and Q7 turn off, the transistor Q2 turns off, and the transistors Q4 and Q8 turn on. Therefore, the potential of the output terminal OUT becomes VDD. Conversely, when the input signal φ is at the H level, the transistor Q
1 is turned off, transistors Q3 and Q7 are turned on, transistor Q2 is turned on, and transistors Q4 and Q8 are turned off.
F. Therefore, the potential of the output terminal OUT becomes VSSL.

As described above, since the transistors Q7 and Q8 have the same ON / OFF state as the transistors Q3 and Q4, the drain current flowing to the transistors Q1 to Q3 to Q7 or the transistors Q2 to Q4 to Q8 is limited. It functions to assist the conduction / cutoff state of Q4. Therefore, the ON resistance of the transistor Q7 is connected in series to the ON resistance of the transistor Q3, and the ON resistance of the transistor Q8 is connected to the ON resistance of the transistor Q4.
Since the N resistors are connected in series, the "ON resistance of the transistor Q3" and the "ON resistance of the transistor Q4" on the right side in the above equations (4) and (5) become these series resistances, and the ratio of the right side to the left side is enlarged. This makes it possible to further stabilize the level shift operation and facilitate the design for reducing the inversion voltage Vt *.

Specifically, the W of the transistors Q1 and Q2
/ L ratio is 120/6, and W of transistors Q3 and Q4
By setting the / L ratio to 12/6 and the W / L ratio of the transistors Q7 and Q8 to about 16/50, the inversion voltage Vt * of the level shift circuit 1 can be reduced to about 1.2 V, and the input signal φ The amplitude of the output is VSSL to VDD (−40 V to 3 V) with respect to the amplitude (0 to 3 V) of FIG.

[0035]

As described above, according to the present invention, the source / drain regions 2 of the transistors Q3 and Q4 can be used.
With the configuration in which one end is simply in contact with the second selective oxide film 26, the effective gate length L is increased, and N−
This has the advantage that the ON resistance of the MOS 22 can be selectively increased. In addition, the ON resistance can be increased in the case of the present application as compared with the case where the gate length is designed to be the same as the effective gate length L. This is because the second selective oxide film 26, which is thicker than the second gate oxide film 26, functions as a part of the gate oxide film.

Therefore, it is easy to satisfy the expressions (4) and (5), and the inversion voltage Vt * of the level shift circuit can be reduced. Therefore, it is possible to cope with a reduction in the operating voltage of the electronic device. It has the advantage of being possible. Further, by increasing the ON resistance of the transistors Q3 and Q4, it becomes easier to obtain a relative ratio with the ON resistance of the transistors Q1 and Q2. Therefore, the overall ON resistance is designed to be small while satisfying the expressions (4) and (5). It becomes possible. Therefore, there is an advantage that the speed of the level shift circuit can be increased and the electronic device can be operated at a higher speed.

Further, it is not necessary to use an extremely large W / L ratio of the transistor, and there is an advantage that the chip size can be reduced. Also, the gate oxide film 2
9 is formed simultaneously with the gate oxide film 27 of the low-breakdown-voltage portion 11, so that no new process is added.
The manufacturing process can be simplified and streamlined.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining the present invention.

FIG. 2 is a cross-sectional view for explaining the present invention.

FIG. 3 is a cross-sectional view for explaining the present invention.

FIG. 4 is a cross-sectional view for explaining the present invention.

FIG. 5 is a cross-sectional view for explaining the present invention.

FIG. 6 is a cross-sectional view for explaining the present invention.

FIG. 7 is a cross-sectional view for explaining the present invention.

FIG. 8 is a cross-sectional view for explaining the present invention.

FIG. 9 is a cross-sectional view illustrating a level shift circuit.

FIGS. 10A and 10B are a circuit diagram and a characteristic diagram illustrating an operation of the level shift circuit. FIGS.

FIG. 11 is a circuit diagram for explaining another example of the level shift circuit.

Claims (2)

[Claims] 1. A one-conductivity channel type MOS having one of a source and a drain connected to a power supply potential VDD side and having an input signal φ and an inverted signal * φ applied to a gate, respectively.
One of the sources or drains of the transistors Q1 and Q2 and one of the sources or drains is connected to the other of the sources or drains of the MOS transistors Q1 and Q2. The other of the sources or drains is connected to the power supply potential VSSL side, A reverse-conducting channel type MOS transistor Q3, Q4 cross-connected to one of the drains; and a low-breakdown-voltage MOS transistor constituting an inverter circuit for outputting the inverted signal * φ. Signal φ and inverted signal * φ having an amplitude of between
In a semiconductor integrated circuit constituting a level shift circuit which outputs an output signal having an amplitude between the power supply potential VDD and VSSL by applying to the gates of the transistors Q1 and Q2, the opposite conductivity type MOS transistors Q3 and Q
4, as a reverse conductivity type source / drain region formed on the surface of the one conductivity type semiconductor substrate, a gate electrode formed above the semiconductor substrate, and a selective oxide film formed near an end of the gate electrode; A semiconductor integrated circuit, comprising: a transistor formed so that an end of the diffusion region of the source / drain region is in contact with the selective oxide film. 2. A step of forming first and second wells of opposite conductivity type on a surface of a semiconductor substrate of one conductivity type; and a well of one conductivity type on a surface of the second well of reverse conductivity type. Forming a region, forming a source / drain region of a reverse conductivity type constituting a first reverse conductivity type MOS transistor on a surface of the semiconductor substrate, and forming a source / drain region on the surface of the first reverse conductivity type well region; Forming a source / drain region of one conductivity type constituting a first MOS transistor of one conductivity type; a first selective oxide film for element isolation on the surface of the semiconductor substrate and the first reverse conductivity type; In forming an oxidation resistant film for forming a second selective oxide film of a MOS transistor, the mask edge of the source / drain region is set back with respect to the mask edge of the oxidation resistant film for the second selective oxide film. To
Forming the oxidation-resistant film; and selectively oxidizing a surface of the semiconductor substrate to form the first and second semiconductor substrates.
Forming a selective oxide film, forming a gate oxide film on a surface of a semiconductor substrate surrounded by the selective oxide film, forming a gate electrode, and forming the second one conductivity type and the opposite conductivity type. Forming a source / drain region of a MOS transistor.