JPH1145519A - Frequency demodulation circuit and optical disk device having the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute the demodulation processing of a frequency modulation signal a with simple constitution and to exactly demodulate digital data even if there is a deformation by a defect, etc., of a recording medium in the frequency modulation signal. SOLUTION: The address information ADM after bi-phase modulation is subjected to frequency modulation and is recorded as a groove wobble. A wobble signal SWB which is a reproducing signal of this groove wobble is modulated to a binary signal PWB. The wobble signal SWB has 4 waves at the time of a '1' and 3 waves at the time of a '0' in correspondence to the 1 bit (bi-phase 1 bit) of address information ADM. Demodulation processing is executed in a detecting circuit 67 by using a clock signal CK24 synchronized with the pulse signal PWB having a frequency of 24 times the bit frequency of the bi-phase. In this processing, the '1' and '0' are decided by utilizing the coincident number of the edge detection signal of the binary signal PWB and the window pulses relating to the patterns of the binary signals respectively corresponding to '1' and '0' of the digital data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a frequency demodulation circuit and an optical disk device having the same. More specifically, the digital data is demodulated by processing based on a clock signal having a frequency that is a common multiple of the frequency of the frequency modulation signal corresponding to the digital data "1" and "0", and window pulses are used. By performing demodulation processing, the frequency modulation signal can be demodulated with a simple configuration, and the digital data can be demodulated accurately even if the frequency modulation signal is deformed due to a defect in the recording medium or the like. It relates to a demodulation circuit and the like.

[0002]

2. Description of the Related Art Conventionally, magneto-optical recording is performed by frequency-modulating bi-phase modulated address information ADM, wobbling a groove portion corresponding to the modulated signal, and recording the modulated signal as a groove wobble. Discs have been proposed. In this case, the groove wobble is
As shown in FIG. 7, for example, when one bit (bi-phase one bit) of the address information ADM is “1”, 4.
It becomes 25 waves (a sine wave with 4.25 cycles), and when it is "0", it becomes a 3.75 wave (a sine wave with 3.75 cycles). In this case, the amplitude of the groove wobble is constant regardless of the frequency of the modulated signal. for that reason,
As shown in an enlarged manner in FIG. 27, the inclination before and after the zero cross point of the groove wobble corresponding to the junction of “1” and “0” of the address information ADM changes.

FIG. 28 shows a reproduction signal of a groove wobble,
That is, a configuration as a conventional example of the frequency demodulation circuit 300 for obtaining the address information ADM from the wobble signal SWB is shown. The frequency demodulation circuit 300 converts the wobble signal SWB from which the DC component has been cut with the threshold = 0 as a pulse signal (binary signal) P
And a comparator 302 for converting to WB.

Further, the frequency demodulation circuit 300 has a PLL
(Phase-locked loop) A voltage-controlled oscillator 303a constituting a circuit 303, an output signal of the voltage-controlled oscillator 303a, and a pulse signal P output from a comparator 302.
A phase comparator 303b for performing a phase comparison with the WB, and a low-pass filter 303c for extracting a low-frequency component of a phase error signal output from the phase comparator 303b and obtaining a control signal for supplying the voltage-controlled oscillator 303a And

The frequency demodulation circuit 300 includes a low-pass filter 304 for extracting a low-frequency component of the output signal of the low-pass filter 303c, a DC cut capacitor 305, and a low-pass filter in which the DC component is cut by setting the threshold to 0. The address information A is obtained from the output signal of the filter 304.
And a comparator 306 for obtaining DM.

The frequency demodulation circuit 300 includes an edge detector 30 for detecting a rising edge or a falling edge of the address information ADM output from the comparator 306.
7 and a monomultivibrator 308 that obtains a pulse signal of a predetermined width using the edge detection signal output from the edge detector 307 as a trigger signal.

The frequency demodulation circuit 300 compares the phase of a voltage control oscillator 309a constituting the PLL circuit 309 with the phase of the output signal of the voltage control oscillator 309a and the pulse signal output from the monomultivibrator 308. The phase comparator 309b and the phase comparator 309
and a low-pass filter 309c for obtaining a control signal for extracting a low-frequency component of the phase error signal output from b and supplying it to the voltage-controlled oscillator 309a.

The operation of the frequency demodulation circuit 300 shown in FIG. 28 will be described. The wobble signal SWB is supplied to a comparator 302 via a capacitor 301 and is converted into a pulse signal (binary signal) PWB. As described above, the address information ADM after the bi-phase modulation is frequency-modulated, and the signal after the modulation is recorded as a groove wobble on the magneto-optical disk. Therefore, as shown in FIG. 29A, the wobble signal SWB is, as shown in FIG. 29A, one bit (bi-phase one bit) of the address information ADM.
Corresponding to "1", it has 4.25 waves and "0"
In the case of, it has 3.75 waves. Therefore, a pulse signal PWB is obtained from the comparator 302 as shown in FIG. 29B.

A wobble signal SWB corresponding to "1"
Is different from the frequency of the wobble signal SWB corresponding to "0", the output signal of the low-pass filter 303c included in the PLL circuit 303 becomes as shown in FIG. 29C. Thus, the address information ADM is obtained. Then, the edge of the address information ADM is detected by the edge detector 307, and the edge detection signal is a pulse signal output from the monomultivibrator 308 as a trigger signal.
The reference signal is supplied to the LL circuit 309. Therefore, the voltage controlled oscillator 309 constituting the PLL circuit 309
From FIG. 29A, a clock signal ACK synchronized with the address information ADM is obtained as shown in FIG. 29E.

[0010]

As described above, FIG.
The frequency demodulation circuit 300 shown in FIG. 8 has two systems of PLL circuits 303 and 309 and has a complicated configuration.

Therefore, according to the present invention, a frequency demodulation signal can be demodulated with a simple configuration, and even when the frequency modulation signal is deformed due to a defect of a recording medium or the like, the frequency demodulation can be accurately demodulated. It is intended to provide a circuit or the like.

[0012]

According to a first aspect of the present invention, there is provided a frequency demodulation circuit, comprising: a waveform shaping unit for obtaining a binary signal from a frequency modulation signal representing digital data; A clock signal generating unit for generating a clock signal having a frequency which is a common multiple of a frequency of a signal and a frequency of a frequency modulation signal corresponding to "0" of digital data, and a process based on the clock signal for the binary signal And a detector that obtains digital data by performing the following. The detection unit detects an edge of the binary signal and outputs an edge detection signal. The detection unit includes a first detection unit that detects an edge of the binary signal and outputs a first detection signal corresponding to digital data “1” and “0”. And a window pulse generation unit for generating a second window pulse, and a first coincidence detection for outputting a first coincidence pulse when the output timing of the edge detection signal coincides with the output timing of the first window pulse A second coincidence detection unit that outputs a second coincidence pulse when the output timing of the edge detection signal coincides with the output timing of the second window pulse, and a count value of the first and second coincidence pulses And a determination unit for determining whether the digital data is "1" or "0".

According to a fourth aspect of the present invention, there is provided an optical disk drive for driving an optical disk in which address information is frequency-modulated and a signal after modulation is recorded as a groove wobble. It comprises a wobble signal reproducing means for reproducing a signal, and a frequency demodulating means for obtaining address information by frequency demodulating the wobble signal.

In the present invention, digital data, for example, a signal obtained by frequency-modulating address information is shaped by a waveform shaping unit and converted into a binary signal. Further, a frequency of a common multiple of the frequency of the frequency modulation signal corresponding to digital data “1” and the frequency of the frequency modulation signal corresponding to digital data “0” is generated by a clock signal generation unit, for example, a PLL circuit or a frequency divider. Is generated.

On the basis of this clock signal, a binary signal corresponding to digital data "1" has a pattern consisting of "1" and "0" for the first clock, and digital data "0". Has a pattern consisting of "1" and "0" for the second clock. In the detector, digital data is demodulated by processing based on the clock signal.

In this process, the edge of the binary signal is detected to obtain an edge detection signal, and the first and second patterns related to the binary signal pattern corresponding to digital data "1" and "0". Is generated, and the digital data is set to “1” or “0” based on the number of coincidences between the output timing of the edge detection signal and the output timings of the first and second window pulses.
Is determined.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration of a magneto-optical disk device 10 as an embodiment.

First, the magneto-optical disk 11 driven by the magneto-optical disk device 10 will be described. FIG. 2 shows a layout of sectors on the magneto-optical disk 11. Tracks 0 to n are spirally formed on the magneto-optical disk 11 from the inner circumference toward the outer circumference. The magneto-optical disk 11 is zoned. Each track in the inner zone X1 includes a sector of 0 to m1 in the circumferential direction, and each track in the outer zone X2 is in the circumferential direction. 0 to m2 sectors are included.

3A to 3D show a sector (wobble address frame) format. As shown in FIG. 3A, groove portions 12G and land portions 12L are alternately formed in the radial direction on the magneto-optical disk 11, and data is recorded in one or both of the groove portions 12G and the land portions 12L. You. One side of the groove 12G is wobbled according to, for example, the address information ADM after the biphase modulation.

In this case, the address information ADM is frequency-modulated (FM), and the groove 12G is wobbled so as to correspond to the modulated signal. That is, the modulated signal is recorded as a groove wobble.
Since one side of the groove portion 12G is wobbled, one side of the land portion 12L is also wobbled in accordance with the address information ADM.

The address information ADM is obtained after the bi-phase modulation. However, the use of the bi-phase modulation of the address information to obtain and use the address information ADM is to prevent generation of a DC component as is well known. (DC free). Here, one bit of the address information before performing the bi-phase modulation corresponds to two bits of the bi-phase modulation.

The groove wobble is, as shown in FIG.
For 1 bit of the address information ADM (1 bit of biphase), when it is “1”, 4 waves (4 cycle sine waves)
When "0", there are three waves (sine waves of three periods). In addition, the amplitude of the groove wobble is changed according to the frequency of the signal after modulation.
As shown in the enlarged view, the inclination before and after the zero cross point of the groove wobble corresponding to the junction of "1" and "0" of the address information ADM is not changed.

Here, the groove wobble in the period of one sector (one wobble address frame) is address information (data) before bi-phase modulation and has, for example, 42 bits of data. This 42-bit data is shown in FIG.
As shown in FIG. 7, 4-bit synchronization signal data, 24-bit frame address data, and 14-bit CRC (cycling)
ic redundancy check) code.

As shown in FIG. 3B, one sector is
For example, it is composed of 42 segments. At the boundary position of each segment, as shown in FIG. 3A, a clock mark CM is multiplexed into a groove wobble and preformatted. As shown in FIG. 3C, a 60-byte data area is provided in each segment,
A fixed pattern area of 6 bytes is provided corresponding to the boundary position of each segment. At the time of data writing, NRZI data is recorded in the data area as described later, but a fixed pattern signal having a length of 2T synchronized with the NRZI data is recorded in the fixed pattern area (T is a data bit interval). . This fixed pattern signal is used to control the phase of the data clock signal when reading data.

Here, in the magneto-optical disk 11, one sector is composed of 42 segments, and the clock mark CM is preformatted at the boundary position of each segment. Becomes 2. In the magneto-optical disk 11,
Since a 60-byte data area is provided in each segment and a 6-byte fixed pattern area is provided corresponding to the boundary position of each segment, the number of channel bits n between adjacent clock marks is 528.

Returning to FIG. 1, the disk drive 10
Has a spindle motor 13 for driving the magneto-optical disk 11 to rotate. The magneto-optical disk 11 is driven to rotate at a constant angular velocity during recording and reproduction. A frequency generator 14 for detecting a rotation speed of the spindle motor 13 is attached to a rotation shaft of the spindle motor 13.

The disk drive 10 includes a magnetic head 15 for generating an external magnetic field, a magnetic head driver 16 for controlling the generation of a magnetic field of the magnetic head 15, a semiconductor laser,
Optical head 17 composed of an objective lens, a photodetector, etc.
And a laser driver 18 for controlling the light emission of the semiconductor laser of the optical head 17. Magnetic head 15
And the optical head 17 are arranged to face each other with the magneto-optical disk 11 therebetween.

The laser driver 18 is supplied with a laser power control signal SPC from a servo controller 41 to be described later via a D / A converter 19, and the power of the laser beam output from the semiconductor laser of the optical head 17 is used during recording. It becomes the recording power PW, and at the time of reproduction, the recording power PW
It is controlled so as to have a lower reproduction power PR.

At the time of data writing (at the time of recording), the recording data Dr and the fixed pattern signal SFP are supplied to the magnetic head driver 16 as described later, and the magnetic head 15 supplies a magnetic field corresponding to the recording data Dr and the fixed pattern signal SFP. Is generated, the recording data Dr is recorded in the data area of the magneto-optical disk 11 in cooperation with the laser beam (laser light) from the optical head 17, and the recording area corresponds to the data area in which the recording data Dr is recorded. A fixed pattern signal SFP is recorded in the fixed pattern area.

FIG. 6 shows the configuration of the optical system of the optical head 17. The optical head 17 includes a semiconductor laser 31 for obtaining a laser beam LB, a collimator lens 32 for shaping the laser beam LB output from the semiconductor laser 31 into a parallel light from a divergent light, and a laser light for transmitting a laser beam. A beam splitter 33 for splitting the reflected light into two, a reflection mirror 34 for changing the optical path of the laser beam, and an objective for irradiating the recording surface (recording film) of the magneto-optical disk 11 with the laser beam LB. A lens 35.

The optical head 17 has a Wollaston prism (polarization plane detection) for separating the laser beam reflected by the reflection surface 33b of the beam splitter 33 and emitted to the outside into three laser beams depending on the polarization direction. (A prism) 36, a condenser lens 37 for condensing three laser beams (parallel light) output from the Wollaston prism 36, and three laser beams emitted from the condenser lens 37 are irradiated. And a multi-lens 38 disposed between the condenser lens 37 and the photodetector 39.

The multi-lens 38 comprises a combination of a concave lens and a cylindrical lens. The use of the cylindrical lens is for obtaining the focus error signal by a well-known astigmatism method. As shown in FIG. 7, the photodetector 39 includes a four-division photodiode unit 39m and two photodiode units 39i and 39j.

FIG. 8 shows a configuration example of the Wollaston prism 36. The prism 36 is configured by joining right-angle prisms 36a and 36b made of a uniaxial crystal, for example, quartz. In this case, the optical axis Axb of the prism 36b is set to be inclined by 45 ° with respect to the optical axis Axa of the prism 36a.

In such a configuration, the quartz has two different refractive indices in relation to the plane of polarization of the incident light.
For this reason, the prism 36a has 45 degrees with respect to its optical axis Axa.
When linearly polarized light La having a polarization plane Ppo inclined by ゜ is incident, the prism 36a has a polarization component Lb1 having a polarization plane perpendicular to the optical axis Axa and a polarization component having a polarization plane parallel to the optical axis Axa, as shown in FIG. The component is separated into Lb2. Further, in the prism 36b, the polarization component Lb1 is separated into a polarization component Lc1 having a polarization plane parallel to the optical axis Axb and a polarization component Lc2 having a polarization plane perpendicular to the optical axis Axb. A polarization component Lc3 having a plane of polarization parallel to and a polarization component L having a plane of polarization perpendicular to the optical axis Axb
Separated into c4.

Here, the polarization components Lc1 and Lc2 are
6a has a polarization plane perpendicular to the optical axis Axa, and the amount of each light is 1/4 of the linearly polarized light La. On the other hand, the polarization components Lc3 and Lc4 have a plane of polarization parallel to the optical axis Axa of the prism 36a, and the amount of each light is 1/4 that of the linearly polarized light La. And the polarization component Lc
2, Lc3 have the same exit angle from the prism 36b, and consequently the prism 36b, and thus the Wollaston prism 3
From No. 6, three laser beams Li, Lm and Lj are obtained separately.

The operation of the optical system of the optical head 17 shown in FIG. 6 will be described. The laser beam LB as divergent light emitted from the semiconductor laser 31 is shaped into parallel light by the collimator lens 32 and is incident on the beam splitter 33. The optical path of the laser beam transmitted through the multilayer film 33 a of the beam splitter 33 is changed at a right angle by the reflection mirror 34, and is applied to the recording surface of the magneto-optical disk 11 via the objective lens 35.

The laser beam reflected on the recording surface of the magneto-optical disk 11 is incident on the beam splitter 33 via the objective lens 35 and the reflection mirror 34. Then, the laser beam Lr reflected by the multilayer film 33a of the beam splitter 33 is further reflected by the reflection surface 33b of the beam splitter 33, emitted outside, and made incident on the Wollaston prism 36.

As described above, the laser beam Lr related to the reflection on the recording surface of the magneto-optical disk 11 is incident on the Wollaston prism 36.
Is set to be inclined by 45 ° with respect to the optical axis Axa when there is no rotation (Kerr rotation) of the polarization plane on the recording surface of FIG. Axis A
xa). Thus, the linearly polarized light La
Is incident, the Wollaston prism 36
From the laser beam Lr to three laser beams L
i, Lm and Lj are obtained separately.

Here, the polarization plane of the laser beam Lr slightly rotates clockwise or counterclockwise according to the direction of magnetization of the recording film of the magneto-optical disk 11, and the laser beam Lr
A magnitude relationship is generated between the light amounts of i and Lj according to the direction of magnetization of the recording film of the magneto-optical disk 11. Therefore, a reproduction signal corresponding to magneto-optically recorded data (signal) can be obtained by detecting the light amounts of the laser beams Li and Lj and taking the difference. Note that the light amount of the laser beam Lm is constant even when the polarization plane of the laser beam Lr rotates.

As described above, the Wollaston prism 36
The three laser beams Li, Lm, Lj emitted from the laser beam enter a photodetector 39 via a condenser lens 37 and a multi-lens 38. As shown in FIG. 7, laser beams Li and L are respectively applied to photodiode portions 39i, 39m and 39j constituting the photodetector 39.
Spots SPi, SPm and SPj are formed by m and Lj.

In this case, the four-division photodiode section 39
m, the detection signals of the four photodiodes Da to Dd are denoted by Sa to Sd, respectively.
When the detection signals of the photodiodes Di and Dj constituting 9i and 39j are Si and Sj, the following calculation is performed in the amplifier circuit unit (not shown) of the optical head 17, and the reproduction signals SMO and An astigmatic focus error signal SFE and a push-pull signal SPP are generated.

SMO = Si-Sj SFE = (Sa + Sc)-(Sb + Sd) SPP = (Sa + Sb)-(Sc + Sd)

Returning to FIG. 1, the disk device 10
A servo controller 41 having a U (central processing unit) is provided. The focus error signal SFE generated by the optical head 17 is supplied to the servo controller 41 via the A / D converter 42. Also, a push-pull signal SPP generated by the optical head 17
Is the tracking error signal STE by the push-pull method
A wobble signal (FM signal) SWB corresponding to the groove wobble of the magneto-optical disk 11;
And the clock mark reproduction signal SCM corresponding to the clock mark CM. Here, the signals STE, SWB,
The SCMs are in different frequency bands. Therefore,
From the push-pull signal SPP, signals STE, SWB, and SCM can be respectively extracted using a low-pass filter or a band-pass filter.

The tracking error signal STE extracted by the low-pass filter 43 from the push-pull signal SPP is supplied to the servo controller 41 via the A / D converter 44. The servo controller 41 is further supplied with a frequency signal SFG output from the frequency generator 14 described above.

The operation of the servo controller 41 is controlled by a system controller 51 described later. The servo controller 41 controls an actuator 45 including a tracking coil, a focus coil, and a linear motor for moving the optical head 17 in the radial direction, performs tracking and focus servo, and controls the radius of the optical head 17. The movement in the direction (radial direction) is controlled. Further, the spindle motor 13 is controlled by the servo controller 41, so that the magneto-optical disk 11 is controlled to rotate at a constant angular velocity during recording and reproduction as described above.

The disk device 10 includes a system controller 51 having a CPU and a data buffer 52.
(Small Computer System Interface) for sending and receiving data and commands to and from the host computer
rface) 53. System controller 5
1 is for controlling the whole system.

The disk device 10 adds an error correction code to write data supplied from the host computer through the SCSI 53 and performs error correction on output data of a data demodulator 59 described later. ECC (error correction code) circuit 54
Then, the write data to which the error correction code is added by the ECC circuit 54 is transmitted to the NRZI (Non Return to Zero Inverte).
d) The data modulator 5 which converts the data into data to obtain the recording data Dr and generates the above-mentioned fixed pattern signal SFP.
5 is provided.

Also, the disk device 10 includes the optical head 1
7, an equalizer circuit 56 for compensating for the frequency characteristics of the reproduced signal SMO, an A / D converter 57 for converting an output signal of the equalizer circuit 56 into a digital signal, and an A / D converter 57 A data discriminator 58 for digitally performing data discrimination processing on output data to obtain reproduction data Dp;
A data demodulator 59 for performing NRZI inverse conversion on the reproduction data Dp output from 8 to obtain read data
And The data discriminator 58 includes a binarizing circuit, a Viterbi decoder, and the like.

Also, the disk device 10 includes the optical head 1
7. An ADIP (Address In Pre-g) for obtaining the frame synchronization signal FD and the frame address data FAD from the wobble signal SWB included in the push-pull signal SPP generated in Step 7.
roove) The decoder 60 and the clock mark reproduction signal SCM included in the push-pull signal SPP and the reproduction signal SMO corresponding to the fixed pattern area of the magneto-optical disk 11
Using a data clock reproducer 70 for obtaining a pulse signal PCM and a data clock signal DCK indicating the timing of the 0 cross point of the reproduced signal SCM, and using a frame synchronization signal FD, frame address data FAD, a pulse signal PCM and a data clock signal DCK. And a timing generator 90 for generating a timing signal necessary for each part of the system such as a read gate signal and a write gate signal. The frame address data FAD is also supplied to the servo controller 41, and the data clock signal DCK is supplied to the A / D converter 57 as a sampling clock.

FIG. 10 shows the configuration of the ADIP decoder 60. The ADIP decoder 60 includes a band-pass filter 61 for extracting the wobble signal SWB from the push-pull signal SPP, and a DC cut capacitor 62.
And the wobble signal SWB as a pulse signal (2
Value signal) PWB.

The ADIP decoder 60 outputs a voltage controlled oscillator 64a constituting the PLL circuit 64 and a clock signal CK24 output from the voltage controlled oscillator 64a to one.
A frequency divider 64b that divides the frequency to / 24, a phase comparator 64c for comparing the phase of the pulse signal PWB output from the comparator 63 with the output signal of the frequency divider 64b, and an output from the phase comparator 64c. And a low-pass filter 64d for obtaining a control signal for extracting a low-frequency component of the phase error signal to be supplied to the voltage-controlled oscillator 64a.

The ADIP decoder 60 performs demodulation processing on the pulse signal PWB output from the comparator 63 using the clock signal CK24 output from the voltage controlled oscillator 64a to obtain address information ADM, and obtains this address. Clock signal A synchronized with information ADM
A detection circuit 67 for obtaining CK, and a clock signal ACK for the address information ADM output from the detection circuit 67
And an address converter 68 for performing synchronization detection, bi-phase demodulation, error detection, and the like to obtain a frame synchronization signal FD and frame address data FAD.

Next, the ADIP decoder 60 shown in FIG.
Will be described. The wobble signal SWB is extracted from the push-pull signal _SPP by the band pass filter 61. Then, the wobble signal SWB is supplied to the comparator 63 via the capacitor 62 and is converted into a pulse signal PWB. As described above, the address information ADM after the bi-phase modulation is frequency-modulated on the magneto-optical disk 11,
The modulated signal is recorded as a groove wobble. Therefore, the wobble signal SWB has the address information A as shown in FIG.
In correspondence with one bit of DM (one bit of biphase),
"1" has four waves, and "0" has three waves. Therefore, the comparator 63 outputs a pulse signal (binary signal) P as shown in FIG. 11B.
WB is obtained. Note that the amplitude of the wobble signal SWB is proportional to the amplitude of the groove wobble of the magneto-optical disk 11.

Wobble signal SWB corresponding to bit "1"
Is fa and the frequency of the wobble signal SWB corresponding to bit "0" is fb, the oscillation frequency of the voltage-controlled oscillator 64a changes near a frequency that is a common multiple of fa and fb (= 6fa = 8fb). Is set to Therefore, the voltage-controlled oscillator 64a outputs the signal shown in FIG.
As shown in C, a clock signal CK24 having a frequency of fc = 6fa = 8fb, that is, 24 times the bi-phase bit frequency, and synchronized with the pulse signal PWB is obtained. Although not described above, the clock signal CK24 is a clock signal for oversampling of the biphase bit, and the oversampling value s of the biphase bit is
Is 24 clocks.

With reference to this clock signal CK24,
Pulse signal P corresponding to bi-phase 1 bit = "1"
The WB (for one cycle) has a 6T pattern consisting of a value of "1" for three clocks and a value of "0" for three clocks, and the pulse signal PWB corresponding to one bit of bi-phase = "0" is four clocks. It has an 8T pattern consisting of a minute value "1" and a value "0" for four clocks.

The detection circuit 67 calculates 8T from the pulse signal PWB.
When detecting the continuation of the pattern, the clock signal ACK
11D, “0” is output in the next bi-phase 1 bit period, while 6T is output from the pulse signal PWB.
When detecting the continuation of the pattern, the clock signal ACK
And outputs "1" in the next bi-phase 1 bit period.

That is, in the detection circuit 67, the pulse signal PWB
A demodulation process is performed on the clock signal ACK from the detection circuit 67 and the address information ADM corresponding to the groove wobble in synchronization with the clock signal ACK.
Is output (shown in FIG. 11E). In addition, FIG.
The reproduction signal SCM of the clock mark CM is shown.

The address information ADM is supplied to the address converter 68. In the address converter 68, synchronization detection, biphase demodulation, error detection, and the like are performed on the address information ADM, and a frame synchronization signal FD and frame address data FAD are obtained. Thus, the address converter 68 outputs the frame synchronization signal F
Along with D, frame address data FAD obtained from the address information ADM is output.

FIG. 12 shows the configuration of the detection circuit 67. Using the clock signal CK24, the detection circuit 67 detects a break (change) between the bi-phase bits "1" and "0" by determining the pattern of the pulse signal PWB, and generates a clock signal CKBP having a bi-phase bit cycle. A bi-phase cycle detection circuit 102 for obtaining the clock signal CKBP is supplied as a reset signal, and a 5-bit counter 103 is supplied with a clock signal CK24 as a clock signal for counting.

The detection circuit 67 generates a window pulse PW0 for the biphase bit “0” and a window pulse PW1 for the biphase bit “1” based on the count output of the 5-bit counter 103. And a window pulse generating circuit 104. Here, the window pulse PW0 is a pulse output corresponding to the rising edge and the falling edge of the pulse signal PWB of the regular 8T pattern, and six pulses are generated in a biphase 1 bit period. . Similarly, the window pulse PW1 is a pulse output corresponding to the rising edge and the falling edge of the pulse signal PWB of the regular 6T pattern, and eight pulses are generated in the bi-phase 1 bit period. .

The detection circuit 67 outputs the clock signal CK
24, an edge detection circuit 110 that detects a rising edge and a falling edge of the pulse signal PWB and outputs an edge detection pulse Pe.

FIG. 13 shows the configuration of the edge detection circuit 110. The edge detection circuit 110 includes two-stage D flip-flop circuits 111 and 112 operated by a clock signal CK24 and an exclusive OR circuit 113.
It is composed of The pulse signal PWB is supplied to the data terminal D of the D flip-flop circuit 111, and the signal obtained at the non-inverting output terminal Q of the D flip-flop circuit 111 is applied to the data terminal D of the D flip-flop circuit 112.
Supplied to Then, the D flip-flop circuit 11
Signals obtained at the non-inverting output terminals Q of the first and the 112 are supplied to the input side of the exclusive OR circuit 113, and the edge detection pulse Pe is output from the output side of the exclusive OR circuit 113.

Returning to FIG. 12, the detection circuit 67
AND gates 121 and 122 function as a coincidence detection circuit by gating the edge detection pulse Pe using the window pulses PW0 and PW1 generated by the window pulse generation circuit 104 as gate signals, and AND gates 121 and 122.
Are compared with the edge pulse counters 123 and 124 for counting the edge detection pulses Pe respectively gated in the above, and the count values x and y of the edge pulse counters 123 and 124 counted in the previous bi-phase 1-bit period.
A comparison circuit 125 outputs address information ADM based on the comparison result in the next bi-phase 1 bit period.

Here, the edge pulse counters 123, 1
The clock signal CKBP having a bi-phase bit cycle is supplied to the reference signal 24 as a reset signal. Also,
This clock signal CKBP is also supplied to the comparison circuit 125 as a timing signal. In the comparison circuit 125, x>
When y, bit “0” is output as address information ADM, and when x <y, bit “1” is output as address information ADM.

The detection circuit 67 outputs the clock signal CK
24 is divided into 1/24, and the clock signal ACK synchronized with the address information ADM is referred to with reference to the clock signal CKBP.
(See FIG. 11D).

The operation of the detection circuit 67 shown in FIG. 12 will be described. The pulse signal PWB is supplied to the biphase period detection circuit 102.
And a clock signal CK24, and a clock signal CKBP having a biphase bit cycle is obtained. Also, 5
The clock signal CKBP is supplied to the bit counter 103 as a reset signal, and the clock signal C
K24 is supplied as a clock signal for counting. As a result, the 5-bit counter 103 is reset first in each bit cycle of the bi-phase, and thereafter performs a counting operation using the clock signal CK24.
It is counted from "0" to "23" in the 0-ary system.

The count output of the 5-bit counter 103 is supplied to a window pulse generating circuit 104, and based on the count output of the 5-bit counter 103, a window pulse PW0 for a bi-phase bit "0" and a bi-phase bit A window pulse PW1 for "1" is generated and supplied as a gate signal to AND gates 121 and 122, respectively.

On the other hand, the pulse signal PWB and the clock signal CK24 are supplied to the edge detection circuit 110, the rising edge and the falling edge of the pulse signal PWB are detected, and an edge detection pulse Pe is obtained. The signals are supplied to AND gates 121 and 122. Then, the edge detection pulses Pe gated by the AND gates 121 and 122 are supplied to edge pulse counters 123 and 124, respectively, and are counted in each biphase 1-bit period.

Then, the comparison circuit 125 compares the count values x and y of the edge pulse counters 123 and 124 counted in the previous bi-phase 1-bit period, and in the next bi-phase 1-bit period, The address information ADM based on the address information is output.

For example, when the wobble signal SWB in a certain bi-phase 1-bit period corresponds to a bi-phase bit "0" as shown in FIG.
The (binary signal) PWB is obtained by repeating the 8T pattern three times as shown in FIG. 14B, and an edge detection pulse Pe is obtained as shown in FIGS. 14D and 14D '. FIG. 14C
Indicates a clock signal CK24.

Since the window pulse PW0 supplied to the AND gate 121 is formed as shown in FIG. 14E, the gate output P00 as a coincidence pulse supplied to the edge pulse counter 123 is as shown in FIG. 14F. And x = 6. On the other hand, the window pulse PW1 supplied to the AND gate 122 is formed as shown in FIG.
The gate output P01 as a coincidence pulse supplied to the
4F ', and y = 2. Therefore,
The comparison circuit 125 outputs bit “0” as the address information ADM in the next biphase 1 bit period.

When the wobble signal SWB in a certain bi-phase 1-bit period corresponds to the bi-phase bit "1" as shown in FIG. 15A, the pulse signal (2
Value signal) PWB is 4 for the 6T pattern as shown in FIG.
The edge detection pulse Pe is obtained as shown in FIGS. 15D and 15D ′. FIG. 15C shows the clock signal CK24.

Since the window pulse PW0 supplied to the AND gate 121 is formed as shown in FIG. 15E, the gate output P00 supplied to the edge pulse counter 123 becomes as shown in FIG. = 2. On the other hand, since the window pulse PW1 supplied to the AND gate 122 is formed as shown in FIG. 15E ', the gate output P01 supplied to the edge pulse counter 124 becomes as shown in FIG. It becomes 8. Therefore, bit “1” is output from comparison circuit 125 as address information ADM in the next biphase 1 bit period.

Next, in the case where the magneto-optical disk 11 has a defect (defect) such as a scratch, the wobble signal S
The case where the WB is deformed will be described.

For example, when the wobble signal SWB in a certain bi-phase 1-bit period corresponds to the bi-phase bit "0" and there is a deformation due to a defect as shown in FIG. 16A, a pulse signal (binary signal) PWB is obtained as shown in FIG. 16B, and an edge detection pulse Pe is obtained as shown in FIGS. 16D and 16D '. FIG. 16C
Indicates a clock signal CK24.

Since the window pulse PW0 supplied to the AND gate 121 is formed as shown in FIG. 16E, the gate output P00 supplied to the edge pulse counter 123 becomes as shown in FIG. = 6. On the other hand, since the window pulse PW1 supplied to the AND gate 122 is formed as shown in FIG. 16E ', the gate output P01 supplied to the edge pulse counter 124 becomes as shown in FIG. It becomes 3. Therefore, bit “0” is output from comparison circuit 125 as address information ADM in the next biphase 1 bit period.

When the wobble signal SWB in a certain bi-phase 1-bit period corresponds to the bi-phase bit "1" and there is a deformation due to a defect as shown in FIG. 17A, a pulse signal (binary signal) PWB Fig. 1
7B, and an edge detection pulse Pe is obtained as shown in FIGS. 17D and 17D '. FIG. 17C shows the clock signal CK24.

Since the window pulse PW0 supplied to the AND gate 121 is formed as shown in FIG. 17E, the gate signal P00 supplied to the edge pulse counter 123 becomes as shown in FIG. = 1. On the other hand, since the window pulse PW1 supplied to the AND gate 122 is formed as shown in FIG. 17E ', the gate output P01 supplied to the edge pulse counter 124 becomes as shown in FIG. It becomes 6. Therefore, bit “1” is output from comparison circuit 125 as address information ADM in the next biphase 1 bit period.

As described above, in the detection circuit 67 shown in FIG. 12, even if the wobble signal SWB is deformed due to a defect as shown in FIGS. 16A and 17A, the wobble signal SWB is not deformed due to the defect. As in the case, the address information ADM can be obtained well.

By the way, when there is a deformation due to a defect as shown in FIGS. 16A and 17A, the difference between x and y becomes large as described above. Even if bit "1" is determined, address information ADM can be obtained correctly.
However, when there is not much difference between x and y, the bit “0”
It may be difficult to determine whether or not to determine the bit "1".

For example, when the wobble signal SWB in a certain biphase 1-bit period is modified as shown in FIG. 18A, the pulse signal (binary signal) PWB becomes as shown in FIG. 18B, and FIG. (FIG. 18E = FIG. 18E ')
As shown in the figure, an edge detection pulse Pe is obtained. FIG.
C indicates the clock signal CK24.

Since the window pulse PW0 supplied to the AND gate 121 is formed as shown in FIG. 18F, the gate output P00 supplied to the edge pulse counter 123 becomes as shown in FIG. = 4. Assuming bit "0", x = 6.

On the other hand, since the window pulse PW1 supplied to the AND gate 122 is formed as shown in FIG. 18F ', the gate output P01 supplied to the edge pulse counter 124 becomes as shown in FIG. 18G'. , Y = 6
Becomes Assuming bit "1", y = 8.

Therefore, for a simple comparison, x <y
Therefore, it is determined that the bit is “1”. However, it cannot be immediately determined that the bit is "1". This is because each of them has the same error in that the count is 2 short in comparison with the number to be detected.

Therefore, a more accurate determination can be made by further adding conditions to the window and detecting the rising edge and the falling edge separately.

FIG. 19 shows a detection circuit 67A having another configuration, in which a rising edge and a falling edge are detected separately. This FIG.
In the figure, parts corresponding to those in FIG. 12 are denoted by the same reference numerals.

The detection circuit 67A outputs the clock signal CK
24, a biphase cycle detection circuit for detecting a break (change) between biphase bits "1" and "0" by pattern determination of the pulse signal PWB and obtaining a clock signal CKBP having a biphase bit cycle. 102
And a 5-bit counter 103 to which the clock signal CKBP is supplied as a reset signal and the clock signal CK24 is supplied as a clock signal for counting.

Further, based on the count output of the 5-bit counter 103, the detection circuit 67A outputs the window pulses PW0u and PW0d for the bi-phase bit “0” and the window pulses PW1u and PW1u for the bi-phase bit “1”. PW1
and a window pulse generating circuit 104A for generating d and d.

Here, the window pulse PW0u is a pulse that is output in response to the rising edge of the pulse signal PWB of the regular 8T pattern, and three pulses are generated in one biphase bit period. Window pulse P
W0d is a pulse that is output in response to the falling edge of the pulse signal PWB of the regular 8T pattern, and three pulses are generated in one biphase bit period.

The window pulse PW1u is a pulse output in response to the rising edge of the pulse signal PWB of the regular 6T pattern, and is output during the biphase 1 bit period.
Pulses are generated. The window pulse PW1d is a pulse that is output in response to the falling edge of the pulse signal PWB of the regular 6T pattern, and four pulses are generated in one biphase bit period.

The detection circuit 67A outputs the clock signal C
The rising edge detection circuit 130 detects the rising edge of the pulse signal PWB using K24 and outputs the edge detection pulse Peu, and similarly detects the falling edge of the pulse signal PWB using the clock signal CK24. ,
An edge detection circuit 140 that outputs an edge detection pulse Ped
And

FIG. 20 shows the rising edge detection circuit 13.
0 is shown. This edge detection circuit 130
It is composed of two-stage D flip-flop circuits 131 and 132 operated by the clock signal CK24 and an AND circuit 133. The pulse signal PWB is supplied to the data terminal D of the D flip-flop circuit 131, and the signal obtained at the non-inverting output terminal Q of the D flip-flop circuit 131 is supplied to the data terminal D of the D flip-flop circuit 132. Then, the signal obtained at the non-inverted output terminal Q of the D flip-flop circuit 131 and the signal obtained at the inverted output terminal Q bar of the D flip-flop circuit 132 are supplied to the input side of the AND circuit 133.
Output an edge detection pulse Peu.

FIG. 21 shows the configuration of the falling edge detection circuit 140. This edge detection circuit 14
0 is a two-stage D flip-flop circuit 141, 142 operated by the clock signal CK24, and an AND circuit 143.
It is composed of The pulse signal PWB is supplied to the data terminal D of the D flip-flop circuit 141, and the signal obtained at the non-inverting output terminal Q of the D flip-flop circuit 141 is applied to the data terminal D of the D flip-flop circuit 142.
Supplied to Then, the D flip-flop circuit 141
And the signal obtained at the non-inverted output terminal Q of the D flip-flop circuit 142 are supplied to the input side of the AND circuit 143, and the edge detection pulse Ped is output from the output side of the AND circuit 143. Is output.

Returning to FIG. 19, the detection circuit 67A
Are AND gates 151 and 152 which gate edge detection pulses Peu and Ped, respectively, using the window pulses PW0u and PW0d generated by the window pulse generation circuit 104A as gate signals, and function as coincidence detection circuits; There are AND gates 153 and 154 that gate edge detection pulses Peu and Ped, respectively, using the window pulses PW1u and PW1d generated by the circuit 104A as gate signals and function as a coincidence detection circuit.

The detection circuit 67A includes an AND gate 1
An edge pulse counter 15 for counting the edge detection pulses Peu and Ped gated at 51 and 152, respectively.
5, 156; edge pulse counters 157, 158 for counting the edge detection pulses Peu, Ped gated by the AND gates 153, 154; an adder 159 for adding the count values of the edge pulse counters 155, 156; And an adder 160 for adding the count values of the pulse counters 157 and 158.

The detection circuit 67A calculates the total value (the output value of the adder 159) x of the count values of the edge pulse counters 155 and 156 counted in the previous bi-phase 1-bit period, similarly to the previous bi-phase. The sum of the count values of the edge pulse counters 157 and 158 counted in one bit period (the output value of the adder 160) y is compared with the address information based on the comparison result in the next biphase one bit period. Comparison circuit 16 for outputting ADM
And 1.

Here, the edge pulse counters 155 to 1
To 58, a clock signal CKBP having a bi-phase bit cycle is supplied as a reset signal. Also,
This clock signal CKBP is also supplied to the comparison circuit 161 as a timing signal. In the comparison circuit 161, x>
When y, bit “0” is output as address information ADM, and when x <y, bit “1” is output as address information ADM.

The detection circuit 67A outputs the clock signal C
K24 is divided into 1/24, and the clock signal ACK synchronized with the address information ADM is referred by referring to the clock signal CKBP.
(See FIG. 11D).

The operation of the detection circuit 67A shown in FIG. 19 will be described. The pulse signal P is supplied to the biphase period detection circuit 102.
WB and the clock signal CK24 are supplied, and a clock signal CKBP having a biphase bit cycle is obtained. Also,
The 5-bit counter 103 includes the clock signal CKBP
Is supplied as a reset signal, and a clock signal CK24 is supplied as a clock signal for counting.
Thereby, in the 5-bit counter 103, in each bit cycle of the bi-phase, the reset is performed first, and thereafter, the counting operation by the clock signal CK24 is performed.
It is counted from "0" to "23" in decimal notation.

The count output of the 5-bit counter 103 is supplied to a window pulse generating circuit 104A,
Based on the count output of the bit counter 103, window pulses PW0u, PW for the bi-phase bit "0"
0d and window pulses PW1u and PW1d for the bi-phase bit “1” are generated, and
It is supplied to 51 to 154 as a gate signal.

On the other hand, the pulse signal PWB and the clock signal CK24 are supplied to the rising edge detection circuit 130,
The rising edge of the pulse signal PWB is detected to obtain an edge detection pulse Peu, and the edge detection pulse Peu is supplied to the AND gates 151 and 153, respectively. Similarly, the pulse signal P is supplied to the falling edge detection circuit 140.
WB and the clock signal CK24 are supplied, and the pulse signal P
The falling edge of WB is detected and the edge detection pulse P
ed is obtained, and the edge detection pulse Ped is supplied to the AND gates 152 and 154, respectively.

The edge detection pulses Peu and Ped gated by the AND gates 151 and 152 are supplied to edge pulse counters 155 and 156, respectively.
It is counted for each bit period. Similarly, edge detection pulses Peu, gated by AND gates 153, 154
Ped is supplied to edge pulse counters 157 and 158, respectively, and is counted in each biphase 1 bit period.

In the comparison circuit 161, similarly to the total value x of the count values of the edge pulse counters 155 and 156 counted in the previous bi-phase 1-bit period, the edge pulse counted in the previous bi-phase 1-bit period The total value y of the count values of the counters 157 and 158 is compared, and address information ADM based on the comparison result is output in the next biphase 1-bit period.

In the detection circuit 67A shown in FIG. 19, the wobble signal SWB in a certain bi-phase 1-bit period is
A description will be given of a case where the image is deformed as shown in FIG. 18A. In this case, the pulse signal (binary signal) PW
B becomes as shown in FIG. 22B, and FIG.
E '), an edge detection pulse Peu corresponding to the rising edge is obtained, and FIG. 22G (= FIG. 22).
As shown in G '), an edge detection pulse Ped corresponding to the falling edge is obtained. FIG. 22C shows the clock signal C.
FIG. 22D shows an edge detection pulse Peu,
An edge detection pulse Pe obtained by adding Ped is shown.

Since the window pulses PW0u and PWOd supplied to the AND gates 151 and 152 are formed as shown in FIGS. 22F and 22H, gates as coincidence pulses supplied to the edge pulse counters 155 and 156 are provided. The outputs A0u and A0d are as shown in FIG. 22I, and x = 1. On the other hand, the window pulses PW1u and PW1d supplied to the AND gates 153 and 154 are formed as shown in FIGS.
Gate outputs A1u and A1d as coincidence pulses supplied to 57 and 158 are as shown in FIG. 22I ', and y = 6. In this case, since the difference between x and y is sufficiently large,
Even if the comparison result is used as it is, a correct detection result is obtained.

Therefore, in comparison circuit 161, x, y
Is used as it is, and during the next biphase 1 bit period, the bit “1” is used as the address information ADM.
Is output.

As described above, by taking into account not only the window pulse but also the edge information of the pulse signal PWB, there is an advantage that a more accurate determination can be made.

Now, the ADIP decoder 60 shown in FIG.
Has a PLL circuit 64, and has a relatively complicated circuit configuration.

As described above, the number a of bi-phase bits between adjacent clock marks is 2, and the number n of channel bits between adjacent clock marks is 528.
And the oversampling value s of the biphase bit is 24 clocks. As will be described later, the data clock regenerator 70 multiplies the reproduction signal SCM of the clock mark CM by n = 528 to obtain the data clock signal DCM.
CK is obtained. In this case, the data clock signal DCK
And the frequency of the bi-phase bit oversampling clock signal CK24 have an integer ratio relationship. That is, the frequency of the data clock signal DCK is fdck, and the frequency of the clock signal CK24 is f24.
Then, fdck = 11 × f24. Therefore, it is possible to generate the clock signal CK24 by dividing the frequency of the data clock signal DCK.

FIG. 23 shows an ADIP decoder 6 of another configuration.
0A indicates that the clock signal CK24 is obtained by dividing the frequency of the data clock signal DCK. This figure 2
In FIG. 3, portions corresponding to those in FIG. 10 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The ADIP decoder 60A outputs the data clock signal DC reproduced by the data clock reproducer 70.
A frequency divider 69 is provided to divide K by 1 / M to generate a clock signal CK24 for oversampling of bi-phase bits. Here, M = n / (a · s), and in the present embodiment, M = 528 / (2 · 24) = 1.
It is one. The clock signal C generated by the frequency divider 69
K24 is used in the detection circuit 67 (67A). FIG. 24A
C show the timing relationship between the reproduction signal SCM of the clock mark CM, the data clock signal DCK, and the clock signal CK24.

The other structure of ADIP decoder 60A shown in FIG. 23 is the same as ADIP decoder 60 shown in FIG. Therefore, although detailed description is omitted, ADIP
The decoder 60A is the ADIP decoder 60 shown in FIG.
, And the address converter 68 obtains the frame address data FAD and the frame synchronization signal FD.

As described above, the ADIP decoder 60A shown in FIG. 23 does not require a PLL circuit to obtain the clock signal CK24, and has the advantage of a simpler circuit configuration than the ADIP decoder 60 shown in FIG. is there.

FIG. 25 shows a data clock regenerator 7.
0 is shown. This data clock regenerator 70
Is a band-pass filter 71 for extracting the clock mark reproduction signal SCM from the push-pull signal SPP, a DC cut capacitor 72, and an edge for obtaining a pulse signal PCM indicating the timing of the 0 cross point of the clock mark reproduction signal SCM. And a detector 73.

The data clock regenerator 70 includes a capacitor 74 for cutting off the DC component of the reproduced signal SMO, and a pulse signal (binary signal) P
A comparator 75 for converting the pulse signal into a signal MO;
A pulse signal PFP corresponding to the reproduction signal SMO in the fixed pattern area of the magneto-optical disk 11 using the fixed pattern gate signal SGo supplied from the timing generator 90
And an AND circuit 76 that gates In this case, as shown in FIG. 3D, the fixed pattern gate signal SG
“o” is “1” during a period in which the reproduction signal SMO of the fixed pattern area is obtained, and “0” during other periods.

The timing generator 90 is supplied with a pulse signal PCM indicating the timing of the 0 cross point of the clock mark reproduction signal SCM. The timing generator 90 generates the fixed pattern gate signal SGo by counting the data clock signal DCK using the pulse signal PCM as a timing reference.

Further, the data clock regenerator 70 has a PL
A voltage-controlled oscillator 77 constituting an L circuit; a frequency divider 78 for dividing the data clock signal DCK output from the voltage-controlled oscillator 77 into 1 / N (here, N = n = 528); Pulse signal P output from the detector 73
A phase comparator 79 for comparing the phase of the output signal of the frequency divider 78 with the CM, and a low-pass filter 80 for extracting a low-frequency component of the phase error signal output from the phase comparator 79
And

The data clock regenerator 70 outputs the pulse signal PFP output from the AND circuit 76 and the frequency divider 78
Phase comparator 81 for comparing the phase with the output signal of
And a high-pass filter 82 for extracting a high-frequency component of the phase error signal output from the phase comparator 81, an output signal of the low-pass filter 80, and an output signal of the high-pass filter 82 supplied via the connection switch 83. And an adder 84 for obtaining a control signal to be supplied to the voltage controlled oscillator 77. The connection switch 83 is supplied with a switch control signal SW from the system controller 51. As a result, the connection switch 83 is turned off at the time of data writing (at the time of recording) and turned on at the time of data reading (at the time of reproduction).

Next, the operation of the data clock regenerator 70 shown in FIG. 25 will be described. A clock mark reproduction signal SCM (shown in FIG. 26A) is extracted from the push-pull signal SPP.
Is supplied to the edge detector 73 via Then, a pulse signal PCM (shown in FIG. 26B) indicating the timing of the 0 cross point of the clock mark reproduction signal SCM is obtained from the edge detector 73.

The reproduced signal SMO output from the optical head 17 (see FIG. 1) is supplied to a comparator 75 via a capacitor 74 and converted into a pulse signal (binary signal) PMO. Then, in the AND circuit 76, the pulse signal (binary signal) PFP corresponding to the reproduction signal SMO in the fixed pattern area of the magneto-optical disk 11 is converted from the pulse signal PMO by the fixed pattern gate signal SGo (shown in FIG. 26C).
(Illustrated in FIG. 26D).

At the time of data writing (at the time of recording), the connection switch 83 is turned off, so that the voltage-controlled oscillator 77, the frequency divider 78, the phase comparator 79, and the low-pass filter 80 constitute a PLL circuit. The phase error signal output from the phase comparator 79 is supplied to the voltage controlled oscillator 77 as a control signal through a low-pass filter 80. Therefore, from the voltage controlled oscillator 77,
A data clock signal DCK whose phase is controlled by the phase information of the clock mark reproduction signal SCM is obtained.

At the time of data reading (at the time of reproduction),
Since the connection switch 83 is turned on, the PLL is controlled by the voltage controlled oscillator 77, the frequency divider 78, the phase comparators 79 and 81, the low-pass filter 80, and the high-pass filter.
The voltage control oscillator 77 includes a phase comparator 7
An addition signal of the low-frequency component of the phase error signal output from 9 and the high-frequency component of the phase error signal output from the phase comparator 81 is supplied as a control signal. Therefore, from the voltage controlled oscillator 77, the data clock signal DC whose phase is controlled by the phase information of the clock mark reproduction signal SCM and the phase information of the reproduction signal SMO in the fixed pattern area.
K is obtained. FIG. 26E shows the data clock signal DCK.

Next, the magneto-optical disk drive 10 shown in FIG.
Will be described. When a data write command is supplied from the host computer to the system controller 51, data writing (recording) is performed. In this case, the ECC circuit 54 adds an error correction code to the write data from the host computer received by the SCSI 53 and stored in the data buffer 52, and further converted by the data modulator 55 into NRZI data. Is performed. Then, the recording data Dr and the fixed pattern signal SFP are supplied from the data modulator 55 to the magnetic head driver 16, and the recording data Dr is recorded in the data area as the target position of the magneto-optical disk 11, and the recording data Dr is recorded. The fixed pattern signal SFP is recorded in a fixed pattern area corresponding to the data area to be processed.

When a data read command is supplied from the host computer to the system controller 51, data reading (reproduction) is performed. In this case, the reproduction signal SMO is obtained from the data area as the target position on the magneto-optical disk 11 and the fixed pattern area corresponding to the data area. The frequency characteristics of the reproduced signal SMO are compensated for by an equalizer circuit 56, converted into a digital signal using a data clock signal DCK by an A / D converter 57, and thereafter, data is discriminated by a data discriminator 58 to be reproduced. Data Dp is obtained. Then, the reproduced data Dp is subjected to NRZI inverse conversion in the data demodulator 59, and error correction is further performed in the ECC circuit 54 to obtain read data. Then, the read data is temporarily stored in the data buffer 52, and thereafter transmitted to the host computer via the SCSI 53 at a predetermined timing.

In writing and reading data, the magnetic head 15 and the optical head 17 are sought to the target position by the servo controller 41. In this case, the seek operation is performed with reference to the frame address data FAD output from the ADIP decoder 60. At the time of writing data (at the time of recording), the data clock reproducer 70 outputs the clock mark reproduced signal SCM.
As a result, a data clock signal DCK whose phase is controlled by the low-frequency component of the phase information held by is obtained, and data is written in synchronization with the data clock signal DCK. On the other hand, at the time of data reading (at the time of reproduction), the phase of the low-frequency component of the phase information of the clock mark reproduction signal SCM and the high-frequency component of the phase information of the reproduction signal SMO of the fixed pattern area are output from the data clock reproducer 70. Is obtained, and data is read out in synchronization with the data clock signal DCK.

In the disk device 10 shown in FIG.
At the time of data reading (at the time of reproduction), the data clock reproducer 70 obtains a data clock signal DCK whose phase is controlled by the phase information of the clock mark reproduction signal SCM and the phase information of the reproduction signal SMO of the fixed pattern area. (See FIG. 25), and even if the amplitude of the clock mark reproduction signal SCM is small and the S / N is poor, a clock signal synchronized with the reproduction data with high accuracy can be obtained.
The processing accuracy of data reading can be improved.

Further, the amplitude of the groove wobble of the magneto-optical disk 11 is changed according to the frequency of the signal after modulation, and the amplitude of the groove wobble corresponding to the junction of "1" and "0" of the address information ADM. The inclination before and after the zero cross point does not change (see FIG. 5).
Therefore, the jitter in the time axis direction of the wobble signal SWB corresponding to the junction of "1" and "0" of the address information ADM can be reduced, and the ADIP decoder 60 (see FIG. 10) can obtain the address information ADM in a satisfactory manner. it can. In the present embodiment, as described above, the address information AD
The wave numbers of the groove wobbles corresponding to “1” and “0” of M are integers, respectively.
This is particularly effective because the junctions of the groove wobbles corresponding to "1" and "0" are all zero cross points.

In the ADIP decoder 60, a clock signal having a frequency fc (= 6fa = 8fb) which is a common multiple of the frequencies fa and fb of the wobble signal SWB corresponding to the data "1" and "0" of the address information ADM, respectively. The address information ADM is obtained by a demodulation process using CK24 (see FIG. 10). Therefore, if the PLL circuit is 1
There is an advantage that the configuration can be realized only by having a system and the configuration of the ADIP decoder 60 is simplified.

In this case, the wave numbers of the groove wobbles corresponding to "1" and "0" of the address information ADM are respectively integers, and correspond to the data "1" and "0" of the address information ADM, respectively. Comparator 63
Since the output pulse signal PWB always has the same shape, demodulation processing using the clock signal CK24 in the detection circuit 67 can be easily performed.

Also, the frequency of the data clock signal DCK and the frequency of the clock signal CK24 for oversampling the biphase bit are in an integer ratio, and the frequency of the data clock signal DCK is divided to oversample the biphase bit. By obtaining the clock signal CK24 for use, the configuration of the ADIP decoder 60A (see FIG. 23) can be simplified (see FIG. 23).

The detection circuit 6 of the ADIP decoder 60
In No. 7, since the detection of the bit “0” and the bit “1” is performed using the window pulse, even if the wobble signal SWB is deformed due to the defect,
As in the case where there is no deformation, the address information ADM can be obtained well.

In the above-described embodiment, the case where only one side of the groove portion 12G of the magneto-optical disk 11 is wobbled is shown.
May be wobbled on both sides.

In this embodiment, the clock mark CM is preformatted on the wobbled side of the groove portion 12G. However, the clock mark CM is preformatted on the non-wobbled side. Also, the clock mark CM on both sides
May be preformatted.

In the above-described embodiment, the wave numbers of the groove wobbles corresponding to "1" and "0" of the address information ADM are "4" and "3", respectively. Absent.

In the above-described embodiment, the fixed pattern area of the recording area is provided in one-to-one correspondence with the recording position of the clock mark CM, but it is not always necessary to make it correspond. For example, the number of fixed pattern areas may be smaller than the number of clock marks CM.

In the above-described embodiment, the fixed pattern signal of 2T is recorded in the fixed pattern area of the magneto-optical disk 11. However, 1T or 3T is recorded.
The above fixed pattern signal may be recorded. However, when the pattern interval becomes short, the MTF (Modu
(Translation Transfer Function) causes the amplitude of the reproduced signal SMO to be small and the S / N to be deteriorated. Conversely, when the pattern interval becomes longer, in order to obtain the same number of edges for phase comparison, it is necessary to increase the fixed pattern area, and the data area in which data is recorded becomes narrower.

In the above embodiment, the ADIP
In the decoders 60 and 60A, the frequency fc of a common multiple of the frequencies fa and fb of the wobble signal SWB corresponding to the data "1" and "0" of the address information ADM, respectively.
(= 6fa = 8fb), the demodulation process using the clock signal CK24 having the frequency f
Similar demodulation processing can be performed using clock signals having other common multiple frequencies of a and fb.

[0138]

According to the present invention, digital data,
For example, digital data is obtained by a demodulation process based on a clock signal having a frequency which is a common multiple of the frequency of the frequency modulation signal corresponding to the data "1" and "0" of the address information. Signal demodulation can be performed.

In the demodulation processing, the edge of the binary signal is detected to obtain an edge detection signal, and the first and second patterns related to the binary signal patterns corresponding to the digital data “1” and “0”. And the output timing of the edge detection signal and the first and second
Of digital data "1" or "0" based on the number of coincidences with the output timings of the respective window pulses. When the frequency modulation signal is deformed due to a defect of the recording medium or the like, Can accurately demodulate digital data. In this case, a more accurate determination can be made by taking into account the edge information of the binary signal.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a magneto-optical disk device as an embodiment.

FIG. 2 is a diagram showing a layout of sectors of a magneto-optical disk.

FIG. 3 is a diagram for explaining a sector (wobble address frame) format.

FIG. 4 is a diagram showing address information of one sector (wobble address frame) before bi-phase modulation.

FIG. 5 is a diagram showing a configuration example of a groove wobble.

FIG. 6 is a diagram showing an optical system of the optical head.

FIG. 7 is a diagram showing a configuration of a photodetector constituting an optical system of the optical head and a spot formed thereon.

FIG. 8 is a diagram illustrating a configuration example of a Wollaston prism constituting the optical system of the optical head.

FIG. 9 is a diagram illustrating a state of separation of light rays by a Wollaston prism.

FIG. 10 is a block diagram illustrating a configuration of an ADIP decoder.

FIG. 11 is a timing chart for explaining the operation of the ADIP decoder.

FIG. 12 is a block diagram illustrating a configuration of a detection circuit.

FIG. 13 is a block diagram illustrating a configuration of an edge detection circuit.

FIG. 14 is a waveform chart for explaining the operation of the detection circuit.

FIG. 15 is a waveform chart for explaining the operation of the detection circuit.

FIG. 16 is a waveform chart for explaining the operation of the detection circuit.

FIG. 17 is a waveform chart for explaining the operation of the detection circuit.

FIG. 18 is a waveform chart for explaining the operation of the detection circuit.

FIG. 19 is a block diagram illustrating another configuration of the detection circuit.

FIG. 20 is a block diagram illustrating a configuration of a rising edge detection circuit.

FIG. 21 is a block diagram illustrating a configuration of a falling edge detection circuit.

FIG. 22 is a waveform chart for explaining the operation of the detection circuit.

FIG. 23 is a block diagram showing another configuration of the ADIP decoder.

FIG. 24 is a timing chart for explaining a clock used in the ADIP decoder.

FIG. 25 is a block diagram showing a configuration of a data clock regenerator.

FIG. 26 is a timing chart for explaining the operation of the data clock regenerator.

FIG. 27 is a diagram showing a configuration example of a conventional groove wobble.

FIG. 28 is a block diagram illustrating a configuration of a conventional frequency demodulation circuit.

FIG. 29 is a timing chart for explaining the operation of the frequency demodulation circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Magneto-optical disk device, 11 ... Magneto-optical disk, 12G ... Groove part, 12L ... Land part, 15 ... Magnetic head for generating an external magnetic field, 16 ...
・ Magnetic head driver, 17 ・ ・ ・ Optical head, 18 ・
..Laser drivers, 41 ... servo controllers,
51: System controller, 55: Data modulator, 58: Data discriminator, 59: Data demodulator, 60, 60A: ADIP decoder, 64:
PLL circuit, 67, 67A ... detection circuit, 68 ...
Address converter, 69: frequency divider, 70: data clock regenerator, 90: timing generator

Claims (7)

[Claims] 1. A waveform shaping unit for obtaining a binary signal from a frequency modulation signal representing digital data, a frequency of the frequency modulation signal corresponding to "1" of the digital data, and a frequency corresponding to "0" of the digital data. A clock signal generation unit that generates a clock signal having a frequency that is a common multiple of the frequency of the frequency modulation signal, and a detection unit that obtains the digital data by processing the binary signal based on the clock signal. An edge detection unit that detects an edge of the binary signal and outputs an edge detection signal; and a detection unit that detects an edge of the binary signal and outputs an edge detection signal. A window pulse generator that generates the first and second window pulses; and the edge of the output timing of the first window pulse. A first coincidence detection unit that outputs a first coincidence pulse when the output timing of the detection signal coincides, and a second coincidence detection unit that outputs the first coincidence pulse when the output timing of the edge detection signal coincides with the output timing of the second window pulse A second coincidence detection unit that outputs a coincidence pulse; and a determination unit that determines whether the digital data is “1” or “0” based on the count values of the first and second coincidence pulses. Characteristic frequency demodulation circuit. 2. The method according to claim 1, wherein the window pulse generation unit converts the first window pulse into a third window pulse relating to a rising edge of the binary signal and a fourth window pulse relating to a falling edge of the binary signal. And separating the second window pulse into a fifth window pulse relating to a rising edge of the binary signal and a sixth window pulse relating to a falling edge of the binary signal. A signal separation unit that separates the edge detection signal into a first edge detection signal related to a rising edge and a second edge detection signal related to a falling edge. Wherein the first coincidence detection unit outputs the first edge detection signal at an output timing of the third window pulse. The first coincidence pulse is output when the timing matches, and the first coincidence pulse is output when the output timing of the second edge detection signal coincides with the output timing of the fourth window pulse. The second coincidence detection unit outputs the second coincidence pulse when the output timing of the first edge detection signal coincides with the output timing of the fifth window pulse, and outputs the sixth coincidence pulse. 2. The frequency demodulation circuit according to claim 1, wherein the second coincidence pulse is output when the output timing of the second edge detection signal coincides with the output timing of the window pulse. 3. The frequency demodulation circuit according to claim 1, wherein the wave numbers of the frequency modulation signals corresponding to the digital data “1” and “0” are integers, respectively. 4. An optical disk drive for driving an optical disk in which address information is frequency-modulated and a signal after modulation is recorded as a groove wobble, wobble signal reproducing means for reproducing a wobble signal corresponding to the groove wobble from the optical disk. Frequency demodulation means for frequency-demodulating the wobble signal to obtain the address information, the frequency demodulation means comprising: a waveform shaping section for obtaining a binary signal from a frequency modulation signal representing digital data; A clock signal generation unit that generates a clock signal having a frequency that is a common multiple of the frequency of the frequency modulation signal corresponding to “1” of the digital data and the frequency of the frequency modulation signal corresponding to “0” of the digital data; Subjecting the binary signal to processing based on the clock signal. A detector for detecting the edge of the binary signal and outputting an edge detection signal; and "1" and "0" of the digital data. A window pulse generating unit for generating first and second window pulses according to a pattern of a binary signal corresponding to the above, and an output timing of the edge detection signal coincides with an output timing of the first window pulse. A first coincidence detection unit that outputs a first coincidence pulse, and a second coincidence pulse that outputs a second coincidence pulse when the output timing of the edge detection signal matches the output timing of the second window pulse. A coincidence detection unit; and a determination unit for determining whether the digital data is “1” or “0” from the count values of the first and second coincidence pulses. Optical disc apparatus according to claim. 5. The method according to claim 5, wherein the window pulse generating unit converts the first window pulse into a third window pulse relating to a rising edge of the binary signal and a fourth window pulse relating to a falling edge of the binary signal. And separating the second window pulse into a fifth window pulse relating to a rising edge of the binary signal and a sixth window pulse relating to a falling edge of the binary signal. A signal separation unit that separates the edge detection signal into a first edge detection signal related to a rising edge and a second edge detection signal related to a falling edge. Wherein the first coincidence detection unit outputs the first edge detection signal at an output timing of the third window pulse. The first coincidence pulse is output when the timing matches, and the first coincidence pulse is output when the output timing of the second edge detection signal coincides with the output timing of the fourth window pulse. The second coincidence detection unit outputs the second coincidence pulse when the output timing of the first edge detection signal coincides with the output timing of the fifth window pulse, and outputs the sixth coincidence pulse. 5. The optical disk device according to claim 4, wherein the second coincidence pulse is output when the output timing of the second edge detection signal coincides with the output timing of the window pulse. 6. The address information “1” and “0”
5. The optical disk device according to claim 4, wherein the wave numbers of the groove wobbles corresponding to the data of (a) and (b) are integers, respectively. 7. The optical disk device according to claim 4, wherein the address information is a signal after bi-phase modulation.