JPH1141491A - Two-dimensional noise reducing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the circuit scale of an adding means and to minimize performance deterioration resulting form simplified processing. SOLUTION: A synchronizing means 1 generates a signal block consisting of pixels on the basis of a video signal inputted from an input terminal 11. Differences between signals of peripheral pixels around a pixel to be processed and the pixel to be processed are obtained at sibstracters 21 to 2n . Correlation detectors 31 to 3n detect the correlations of the object pixel with the peripheral pixels from the outputs of the substracters 21 to 2n , and outputs a detected signal to a counting means 4. The counting means 4 counts pixels having high correlations and outpours the result to a selecting means 5 and a subtracting means 7. The selecting means 5 selects only the pixels having the high correlations according to the output of the counting means 4 and inputs them to a 1st adding means 6. The subtracting means 7 subtracts the output of the 1st adding means 6 according to the output of the counting means 4. A 2nd adding means 8 adds the output of the dividing means 7, which is the mean value obtained simply from the difference data, to the process object pixel outputted form the synchronizing means 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a two-dimensional noise reduction circuit used for video equipment such as a television and a video.

[0002]

2. Description of the Related Art A conventional two-dimensional noise reduction circuit for high image quality in video equipment will be described. The two-dimensional noise reduction circuit is roughly classified into two types: a non-linear filter such as a median filter and a spatial low-pass filter (LPF). The latter is described here.

[0003] The two-dimensional spatial LPF performs filtering in the horizontal and vertical directions of a video signal to reduce noise having a spatially high frequency component.
If filter processing is simply performed, high-frequency components are attenuated in an edge portion and a detail portion of an image, so that image quality degradation such as edge dullness and resolution degradation occurs.

A two-dimensional adaptive LPF described below has been considered to prevent such image quality deterioration. FIG.
It is an example of a dimension adaptive LPF. The synchronizing means 1 forms a two-dimensional signal block composed of a plurality of pixels based on the video signal input from the input terminal 11. FIG. 2 shows an example of such a signal block. FIG. 2 shows a case where a signal block is formed from 13 pixels, and a subscript at the lower right of a indicates a position. Here, a _i , _j is the pixel to be processed, a _i , _j
The other pixels are called peripheral pixels around the processing target pixels a _i , _j .

FIG. 3 shows an example of the synchronizing means necessary for forming the signal block shown in FIG. In FIG. 3, 13 ₁ , 1
3 ₂ IH (H: horizontal scanning period) delay element, 14 _1-14
Reference numeral ₁₄ denotes a 1T (T: horizontal sampling period) delay element.

[0006] subtraction means 2 ₁ to 2 _n processing target pixel a _i of (in the case of the signal blocks in FIG. 2 n = 12) in FIG. 2, the processing from the values of the peripheral pixels other than the _j pixel a _i, the value of _j Is output.

[0007] correlation detector 3 _1, to 3 _n subtracter 2 ₁ to 2 _n
Compared to the given output in advance threshold, it is determined if the threshold value or less target pixel a _{i, j} and the processing target pixel a _i, and there correlation with peripheral pixels other than _j "1 , And “0” otherwise.

The counting means 4 counts the number of "1" appearing in the outputs of the correlation detectors 3 _{1 to} 3 _n , that is, the number of peripheral pixels judged to be correlated with the pixels a _i , _j to be processed, and calculates the average value. Finds and outputs the divisor in the processing. Further counting means 4
In this case, position information of peripheral pixels determined to have a correlation with the processing target pixels a _i , _j is also output. As a specific example using the signal block of FIG. 2, for example, a _i−1 , _j , a _i , _j−1 ,
a _{i, j + 1,} a i _{+ 1,} 4 pixels are processed pixels a _i of _j, if it is determined that correlated with _j is high, the target pixel a _{i, j} and this peripheral pixels a _{i- Since} it is necessary to perform averaging of 5 pixels for convenience of 4 pixels of ₁ , _j , a _i , _j−1 , a _i , _{j + 1} , a _{i + 1} , _j , the counting means 4 uses the divisor “5”. And the peripheral pixels a _i−1 , _j ,
The position information of each of _ai , _j-1 , _ai , _{j + 1} , and _{ai + 1} , _j is output.

According to the position information of the peripheral pixels correlated with the pixels a _i , _j to be processed, which is the output of the counting means 4, the selecting means 5 selects the peripheral pixels determined to be correlated with the pixels a _i , _j to be processed. All are selected and input to the adding means 6 as they are. The adding means 6 calculates the sum of the pixels to be processed a _i , _j and the peripheral pixels determined to be correlated, which is the output of the selecting means 5, and inputs the sum to the dividing means 7.

The dividing means 7 divides the sum output from the adding means 6 by a divisor "5" output from the counting means 4 to obtain an average value of all pixel values output from the selecting means 5. Ask.

With the above configuration, the two-dimensional adaptive LP
In F, the average of the values of the pixel to be processed and the peripheral pixels having a correlation with the pixel to be processed can be obtained. According to this processing, edge dullness and detail deterioration can be reduced. This is shown in FIG.

FIG. 8 shows a case where the two-dimensional adaptive LPF processing is at an edge portion. FIG. 8 (a) shows a case of a horizontal edge, and FIG. 8 (b) shows a case of a vertical edge. In the figure, the shaded portion indicates a low luminance portion, and the other portion indicates a high luminance portion. Now, the difference, that the horizontal edges of the high luminance portion and a low luminance portion of the figure, the contrast in the vertical edge is sufficiently larger than the threshold value in the correlation detector 3 ₁ to 3 _n of FIG. 7, superimposed on each pixel Assuming that the level of the noise is smaller than the above threshold value, in the case of FIG. 8A, the five pixels a _i−1 , _j , a _i , _j−3 , a _i , _{j− 2} ,
The _ai , _j-1 and _{ai + 1} , _j-1 are excluded from the averaging process, and the average value of only the remaining eight pixels existing in the high-luminance part is obtained, so that edge dulling does not occur. The same applies to the case of FIG. In the detail section, details larger than the threshold value are excluded from the averaging process, so that the details are not lost. However, in the above-described two-dimensional adaptive LPF, a division process is required to obtain an average of correlated pixels. However, the division unit 7 generally has a large circuit scale. Therefore, it is conceivable to reduce the circuit scale of the dividing means 7 by the following simplification processing.

FIG. 9 shows a numerical value generating means 10 provided between the counting means 4 and the dividing means 7 to reduce the circuit scale of the dividing means 7 by limiting the division in the dividing means 7 to a power of two. is there. Synchronizing means 1 in FIG. 9, since the subtraction means 2 ₁ to 2 _n, the correlation detector 3 ₁ to 3 _n and the counting means 4 are of exactly the same as FIG. 5, the description thereof is omitted.

The selecting means 5 is output from the counting means 4.
It operates according to the following algorithm according to the divisor of the averaging process.

"If the divisor is not a power of 2, the gain is applied to the pixel to be processed so that the total order is a power of 2 and the result is input to the adding means 6." When the divisor output from 4 is “5”, that is, when there are four peripheral pixels determined to have correlation, the pixel to be processed is quadrupled and output, and the output of the adding means 6 is on the order of eight pixels. So that

The numerical value generating means 10 outputs “the minimum power of 2 exceeding the divisor” according to the divisor output from the counting means 4. If the divisor is "5", it is "8".

The dividing means 7 divides the output of the adding means 6 by the output of the numerical value generating means 10.

With the above configuration, the number of pixels added by the adding means 6 is always a power of two. Therefore, in the digital processing circuit, the configuration of the dividing means 7 is only a bit shift, which is very simple.

[0019]

However, in the above configuration, since the number of pixels input to the adding means 6 is 13 at the maximum, the number of bits of the adding means becomes large. Assuming that each pixel value is 8-bit data, the output of the adding means 6 requires 12 bits. Further, the adding means 6 is generally configured in a tree shape by a plurality of adders as shown in FIG. That is, one 12 bit, 11 bit 2
, 10 bits, 3 bits, 9 bits, 6 bits, for a total of 118 bits, resulting in a considerable circuit scale.

Further, in the simplification processing as shown in FIG. 9, the noise reduction performance is deteriorated as compared with the strict processing as shown in FIG. This is shown below. Consider an average processing of data b _{1 to} b _n (n> 2) on which noises of levels c _{1 to} c _n and a mean square value c ² are superimposed. The exact processing is as shown in Equation 1.

[0021]

(Equation 1)

By the processing of the equation 1, the noise level becomes 1 / n ^1/2 as shown in the equation 2.

[0023]

(Equation 2)

Here, when the value of the pixel to be processed, b _1, is multiplied by m (m> 1) and added, and the total data number is (m + n), the noise level is

[0025]

(Equation 3)

## EQU1 ## As is apparent from Equation 3, since the noise level is higher than when averaging different (m + n) data, the noise reduction effect is reduced.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a noise reduction circuit capable of reducing the circuit size of an adding means and further minimizing the performance deterioration due to the simplification processing.

[0028]

According to a first aspect of the present invention, there is provided a method for calculating an average value of a difference between a pixel to be processed and its surrounding pixels and adding the average value to the pixel to be processed. It is.

Further, in order to solve this problem, a second aspect is provided.
According to the invention, when calculating the average value of the difference between the pixel to be processed and its surrounding pixels, even if the divisor generated by the counting means is not a power of two, the input to the dividing means is a power of two. It was done.

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention according to claim 1 of the present invention provides a signal block forming means for forming a two-dimensional signal block composed of a plurality of pixels based on an input video signal,
A plurality of subtraction means for calculating a difference between a value of a pixel to be processed at a specific position among a plurality of pixels constituting the signal block and values of peripheral pixels around the pixel to be processed; and The magnitude of the means output is compared with a predetermined level,
A plurality of comparators for outputting a comparison result signal, and counting the number of comparison result signals indicating that the comparison result signal is smaller than a predetermined level among the plurality of comparator outputs, a signal indicating the result, and the plurality of subtraction means. Counting means for respectively outputting a signal that specifies a value smaller than a predetermined level, and selecting means for selecting and outputting only the output specified by the counting means output from the plurality of subtracting means outputs, First adding means for adding a plurality of outputs of the selecting means, dividing means for dividing the first adding means output by the counting means output, and adding the value of the pixel to be processed and the dividing means output A second adding means for outputting an output of the second adding means, and averaging only a plurality of outputs of the subtracting means which are smaller than a predetermined level to output the output of the processing means. An effect that is added to the pixel.

According to a second aspect of the present invention, there is provided a signal block forming means for forming a two-dimensional signal block consisting of a plurality of pixels based on an input video signal, and a plurality of pixels forming the signal block. A plurality of subtraction means for calculating a difference between a value of a pixel to be processed at a specific position and values of peripheral pixels around the pixel to be processed, and a magnitude comparison between outputs of the plurality of subtraction means and a predetermined level A plurality of comparators that output a comparison result signal, and among the plurality of comparator outputs, count the number of comparison result signals indicating that the comparison result signal is smaller than a predetermined level, a signal indicating the result, and the plurality of A counting means for outputting a signal for specifying a signal which outputs a value smaller than a predetermined level among the subtracting means; and selecting only an output specified by the counting means output from the plurality of subtracting means outputs. Selecting means for outputting, first adding means for adding a plurality of outputs of the selecting means, numerical value generating means for generating a numerical value according to the count result outputted from the counting means, and outputting the first adding means. Division means for dividing by the output of the numerical value generation means, and second addition means for adding the value of the pixel to be processed and the output of the division means,
Outputting the output of the second adding means,
Among the outputs of the plurality of subtraction means, only an output smaller than a predetermined level is averaged and added to the pixel to be processed.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram showing a noise reduction circuit according to Embodiment 1 (corresponding to claim 1) of the present invention. In FIG. 1, 1 is a synchronizing means as signal block forming means, 2 ₁ to 2 _n are subtracting means, 3 _{1 to} 3 _n are correlation detectors as comparators, 4 is a counting means, 5 is a selecting means,
6 is a first adding means, 7 is a dividing means, 8 is a second adding means, 11 is an input terminal, and 12 is an output terminal. The synchronizing means 1 forms a two-dimensional signal block composed of a plurality of pixels as shown in FIG. 2 based on the video signal input from the input terminal 11 and outputs the signal block. FIG. 3 shows an example of the synchronizing means 1 necessary for forming the signal block of FIG.

In the subtraction means 2 _{1 to} 2 _n (n = 12 in the case of the signal block in FIG. 2), the values of the pixels a _i , _j to be processed are calculated from the values of the peripheral pixels other than the pixels a _i , _{j to be} processed in FIG. Is subtracted, and the difference is clipped to the upper limit and lower limit levels that can be compared by the correlation detectors 3 _{1 to} 3 _n and output. Correlation detector 3 ₁ -
3 compared to _n in the given output of the subtraction means 2 ₁ to 2 _n in advance threshold, it is determined that the surrounding pixels if a threshold below the target pixel a _i, and there correlated with _j " Otherwise, it determines that the surrounding pixels have no correlation with the processing target pixels a _i , _j and outputs “0”. The number of the counting means 4 at the output of the correlation detector 3 ₁ to 3 _n "1", i.e., the processing target pixel a _i, counts the number of peripheral pixels is determined that there correlate with _j, the averaging process divisor Output the numerical value that should be. The counting means 4 also outputs the position information of the peripheral pixels determined to have a correlation with the processing target pixels a _i , _j .

The selection means 5, the processing target pixel a _i outputted from the counting means 4, according to the position information of the peripheral pixel having the correlation with _j, of the output of the subtraction means 2 ₁ to 2 _n, the processing target pixel a _i , _j and all the differences between the values of the peripheral pixels determined to have a correlation and the values of the processing target pixels a _i , _j are selected and input to the first adding means 6 as they are. As a specific example using the signal block of FIG. 2, for example, _ai-1 , _j , _ai , _j-1 , _ai , _{j + 1} ,
When it is determined that the four peripheral pixels of a _{i + 1} , _j are correlated with the processing target pixel a _i , _j , (a _i−1 , _j− a _i , _j ), (a _i ,
_j−1 −a _i , _j ), (a _i , _{j + 1} −a _i , _j ), (a _{i + 1} , _j −
a _i , _j ) because it is necessary to average the four differences
The selection means 5 outputs each of the four differences to the first addition means 6.

The first addition means 6 calculates the sum of the outputs of the four differences from the selection means 5 and inputs the sum to the division means 7. The dividing means 7 divides the total output of the first adding means 6 by a numerical value which is an output of the counting means 4 and which is to be a divisor of the averaging process, thereby obtaining an average value of a difference between the peripheral pixel and the processing target pixel. .

The second adding means 8 adds the average value of the difference between the peripheral pixel and the processing target pixel which is the output of the dividing means 7 to the value of the processing target pixel a _i , _j from the synchronizing means 1.

With the above configuration, processing equivalent to the configuration of FIG. 7 can be performed. This is shown below.

By transforming equation (1), equation (4) is obtained.

[0040]

(Equation 4)

The number 4 is averaging process b ₁ ~b _n have shown that the average value of the difference between b ₁ and b ₂ ~b _n is equivalent to adding a b _1. Here b1 value of the target pixel, the b ₂ ~b _n is a value of the peripheral pixels having the correlation therewith. With this configuration, the circuit scale of the first adding means 6 can be reduced. If the data b ₁ ~b _n is assumed to 8 bits. Since the difference level to determine that there is a correlation in the correlation detector 3 ₁ to 3 _n in the 8-bit data is at most about 3-bit absolute value, subtraction means 2 ₁ -
4 bits is sufficient for each output of 2 _n . Number of data n is 1
If it is 3, the number of bits required for the output of the first adding means 6 is 8 bits. Even if this is considered in a tree-shaped adder configuration as shown in FIG. 5, there are only 8 bits, 7 bits, 1 bit, 3 bits, 6 bits, and 6 bits, for a total of 63 bits. Since the output of the second adding means 8 is the final output, the required number of bits is 8 bits, so even if this is added, it is 71 bits, and the circuit size of the adder can be reduced to 60%. In an actual circuit, a flip-flop is inserted between adders as needed, so that the difference in circuit scale is considered to be further increased.

In the above description, the shape of the signal block formed by the synchronization means 1 and the pixel to be processed are shown in FIG.
Has been described, but other shapes can be similarly implemented. Therefore, the internal configuration of the synchronization unit 1 is not limited to the circuit shown in FIG.

Further, by performing the difference averaging process as described above, another effect is produced. This is shown below.

For example, assuming a case where the sum of n data is divided by a power of 2 k (k ≠ n) different from n as shown in Expression 5,

[0045]

(Equation 5)

This is an order of n / k times. However, considering the case of calculating the average value of the difference as in Equation 6,

[0047]

(Equation 6)

Thus, a gain of n / k is applied to the average difference value. Here, since only the peripheral pixels having correlation are selected and the difference is obtained, the average difference value is also added to the data b ₁ . It is only small enough. Therefore, the output order does not change.

This means that the degree of freedom in selecting the divisor can be increased by performing the difference averaging process. Therefore, the following configuration is conceivable.

(Embodiment 2) FIG. 4 is a block diagram showing a noise reduction circuit according to Embodiment 2 (corresponding to claim 2) of the present invention. In FIG. 4, 1 is a synchronizing means as a signal block forming means, 2 ₁ to 2 _n are subtraction means, 3 _{1 to} 3 _n are correlation detectors as comparators, 4 is a counting means, 5 is a selection means, and 6 is a selection means. First addition means, 7 is division means, 8 is second addition means, 10 is numerical value generation means, 11 is an input terminal, and 12 is an output terminal.

The synchronizing means 1, subtraction means 2 ₁ to 2 _n, the correlation detector 3 ₁ to 3 _n, the counting means 4, the selection means 5 and the first addition means 6, exactly the same as the first embodiment Therefore, the description is omitted.

The numerical value generating means 10 outputs an appropriate value of a power of 2 according to the divisor output from the counting means 4. FIG.
2 shows an example of the input / output characteristics of the numerical value generating means 10. As described above, the output value does not necessarily need to be larger or smaller than the input value, and can be freely determined.

The dividing means 7 divides the output of the first adding means 6 by the output of the numerical value generating means 10 to obtain the average value of the difference between the peripheral pixel and the pixel to be processed.

The second adding means 8 adds the output of the dividing means 7 to the value of the pixel to be processed outputted from the synchronizing means 1.

With this configuration, not only can the circuit size of the first adding means 6 be reduced, but also the input / output characteristics of the numerical value generating means 10 can be freely adjusted so that the noise reduction effect is maximized. It is possible to determine, and as a result, it is possible to minimize the deterioration of the noise reduction performance due to the simplification processing.

In the above description, the shape of the signal block formed by the synchronization means 1 and the pixels to be processed are shown in FIG.
Has been described, but other shapes can be similarly implemented. Therefore, the internal configuration of the synchronization unit 1 is not limited to the circuit shown in FIG. The input / output characteristics of the numerical value generating means 10 are not limited to the characteristics shown in FIG.

[0057]

As described above, according to the first aspect of the present invention, the circuit scale of the adding means can be reduced by adding the average value of the difference between the peripheral pixel and the processing target pixel to the processing target pixel. The effect is obtained.

According to the second aspect of the present invention, not only the circuit scale of the adding means can be reduced, but also the degree of freedom in determining the input / output characteristics of the numerical value generating means can be increased, so that the deterioration of the noise reduction performance due to the simplification processing is minimized. The effect is obtained that it can be minimized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a noise reduction circuit according to a first embodiment of the present invention.

FIG. 2 is a schematic diagram showing an example of a signal block formed in the synchronization unit 1;

FIG. 3 is a block diagram showing a specific configuration example of the synchronization unit 1;

FIG. 4 is a block diagram illustrating a configuration of a noise reduction circuit according to a second embodiment of the present invention;

FIG. 5 is a block diagram showing a configuration example of a first adding means 6;

FIG. 6 is a chart showing an example of an input / output relationship of the numerical value generating means 10;

FIG. 7 is a block diagram showing a configuration of a conventional noise reduction circuit.

FIG. 8 is a schematic diagram for explaining the operation of the two-dimensional adaptive average filter.

FIG. 9 is a block diagram showing a configuration of a conventional noise reduction circuit.

FIG. 10 is a block diagram showing a configuration example of an adding unit 6 in FIGS. 7 and 9;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 synchronization means (signal block forming means) 2 subtraction means 3 correlation detector (comparator) 4 counting means 5 selecting means 6 first adding means 7 dividing means 8 second adding means 10 numerical value generating means

Claims (3)

[Claims] 1. A signal block forming means for forming a two-dimensional signal block composed of a plurality of pixels based on an input video signal, and a processing target at a specific position among a plurality of pixels constituting the signal block A plurality of subtraction means for calculating a difference between a value of a pixel and a value of a peripheral pixel around the pixel to be processed; a magnitude comparison between outputs of the plurality of subtraction means and a predetermined level; and a comparison result signal output. A plurality of comparators, of the plurality of comparator outputs, counting the number of comparison result signals indicating a value smaller than a predetermined level, a signal indicating the result, and a value smaller than a predetermined level among the plurality of subtraction means. Counting means for respectively outputting a signal specifying the output of the counting means; selecting means for selecting and outputting only the output specified by the counting means output from the plurality of subtraction means outputs; First adding means for adding a plurality of outputs of the selecting means, dividing means for dividing the output of the first adding means by the output of the counting means, and adding the value of the pixel to be processed and the output of the dividing means. A two-dimensional noise reduction circuit, comprising: a second addition unit. 2. A signal block forming means for forming a two-dimensional signal block composed of a plurality of pixels based on an input video signal, and a processing target at a specific position among a plurality of pixels constituting the signal block A plurality of subtraction means for calculating a difference between a pixel value and a value of a peripheral pixel around the processing target pixel; a plurality of subtraction means for comparing the output of the plurality of subtraction means with a predetermined level to output a comparison result signal; And counting the number of comparison result signals indicating smaller than a predetermined level among the plurality of comparator outputs, and outputting a signal indicating the result and a value smaller than a predetermined level among the plurality of subtraction means. Counting means for respectively outputting a signal specifying the selected one; selecting means for selecting and outputting only an output specified by the counting means output from the plurality of subtracting means outputs; First adding means for adding a plurality of outputs of the stages, numerical value generating means for generating a numerical value according to the counting result from the counting means, and dividing means for dividing the output of the first adding means by the numerical value generating means output And a second adding means for adding the value of the peripheral target pixel and the output of the dividing means, and a two-dimensional noise reduction circuit. 3. An input / output characteristic of said numerical value generating means, wherein a maximum power of 2 not exceeding the value of the input signal is output if the value of the input signal is not a power of 2. 3. A two-dimensional noise reduction circuit according to claim 2, wherein when the value of the signal block forming means is equal to the number of pixels of the signal block forming means, a minimum power of 2 exceeding the value of the input signal is output.