JPH1141489A - Video signal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the occurrence of a luminance difference caused by luminance degradation even when the video signal of equal aspect ratio as that of a display screen is displayed by making the level of luminance degradation on a fluorescent body or the like uniform between a frame signal display section and a video signal display section by controlling the luminance level of a frame signal to be inserted corresponding to the calculated result of an average luminance level for each field or frame. SOLUTION: When displaying the video signal of an aspect ratio different from that of the display screen on the display screen while inserting the frame signal, an inputted digital luminance signal is interpolated by an interpolation circuit 211 corresponding to the number of effective pixels in the digital image and synthesized with on-screen display information by a synthesizing circuit 212 and afterwards, the average luminance level for each field or frame is calculated by an average luminance level calculation circuit 213. A level setting circuit 217 sets the luminance level of the frame signal based on the output of the level calculation circuit 213 and a frame signal generating circuit 216 generates the frame signal and outputs it through a changeover switch 220 synchronously with a synchronizing signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal display device, and more particularly, to a program for selecting and displaying one program from a plurality of types of video signals having a plurality of image formats having different aspect ratios, such as digital broadcasting. Video signal display device or, for example, a high definition television signal (hereinafter, referred to as
The present invention relates to a video signal display device capable of switching and displaying a plurality of types of video signals having different aspect ratios, such as HDTV signals) and video signals of current terrestrial broadcasting.

[0002]

2. Description of the Related Art Currently, terrestrial broadcasting such as the NTSC system has an aspect ratio of a video signal of 4: 3.
On the other hand, the video signal of the HDTV signal has an aspect ratio of 1
The image is 6: 9. For this reason, for example, HDTV
When displaying a current NTSC video signal on a signal display and displaying an HDTV signal on an NTSC display, on the other hand, for example, the Journal of the Institute of Television Engineers of Japan, Vol. 47, no. 7, pp9
49 to 952 (1993), a video signal conversion process is required.

[0003]

As described in the above-mentioned literature, FIG. 3 shows a display screen having an aspect ratio of, for example, 16: 9. When displaying a video signal having an aspect ratio of 4: 3 in the NTSC system, the upper and lower portions of the original video signal (d) are appropriately cut out and the remaining portion is enlarged as shown in FIG. (B)
As shown in (1), there is a method of inserting a frame signal (shaded portion) on the left and right of the original video signal (d) and displaying it on the display screen. In addition, as shown in FIG.
May be expanded in the horizontal direction and displayed as a video signal having an aspect ratio of 16: 9.

However, the method shown in (a) has a disadvantage that the entire screen of the original video signal (d) cannot be visually recognized. Further, in the method shown in (c), the entire portion of the original video signal (d) is visible, but the aspect ratio is changed by extending the video signal in the horizontal direction. There is a problem that the signal is distorted with respect to the original video signal (d). In contrast to the above method, in the method shown in (b), the entire screen of the original video signal can be visually recognized without distortion. For example, a display screen having an aspect ratio of 16: 9, such as the current NTSC system, is used. Aspect ratio 4:
In order to display the third video signal, it is desirable to use the video signal conversion processing method according to (b).

However, the method shown in FIG.
When a video signal having an aspect ratio of 4: 3 is displayed on a display screen having an aspect ratio of 16: 9 by inserting frame signals on the left and right sides thereof, the following problem occurs.

That is, when a video signal is displayed by inserting a frame signal, a display device, for example, a cathode ray tube, is displayed on the display screen at a portion where the frame signal is displayed and a portion where the video signal is displayed. Have different luminance levels. Therefore, when such display of the video signal and the frame signal is continued for a long time, the degree of luminance deterioration of the phosphor of the CRT greatly differs. Next, when a video signal is displayed without inserting a frame signal, that is, when a video signal having an aspect ratio equal to the aspect ratio of the display screen is displayed on the display screen, the phosphor is displayed on the same screen. Causes a luminance difference due to the difference in the degree of luminance deterioration of the
That is the problem. This problem is particularly noticeable in a projection television (hereinafter, referred to as a PTV).

In particular, for example, a video signal display device capable of displaying both a so-called high-definition broadcast and a terrestrial NTSC broadcast in Japan, and a digital broadcast which will be started in the near future, such as a digital broadcast, which supports a plurality of image display formats. In the video signal display device for receiving the video signal, a countermeasure for the above problem is required in the display device.

An object of the present invention is to provide a video signal display device which inserts a frame signal into a video signal having an aspect ratio different from that of the display screen and displays the video signal on the display screen. Thus, even if the degree of luminance deterioration of the display device, that is, the phosphor of the cathode ray tube, is made uniform, and a video signal having the same aspect ratio as that of the display screen is displayed on the display screen, the difference in the degree of luminance deterioration of the phosphor is obtained. It is an object of the present invention to provide a video signal display device which does not cause a luminance difference caused by the above.

[0009]

In order to achieve the above object, the present invention provides a frame signal inserting means for inserting a signal into a video signal to adjust the aspect ratio of a display device, and for each field or frame of the video signal. Average brightness level calculating means for calculating the average brightness level of the frame signal, and brightness level setting means for controlling the brightness level of the frame signal to be inserted according to the calculation result of the average brightness level calculating means. And

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a video signal display device according to the present invention. As an example of the video signal display device of this embodiment, for example, a video signal subjected to data compression by the MPEG2 method is used. In the case of a PTV capable of receiving a digital broadcast having a plurality of image display formats, displaying a video signal obtained by decoding digital data, and displaying a video signal of the current NTSC broadcast, Will be described.

In FIG. 1, reference numeral 101 denotes an input terminal of a digital broadcast reception signal, 102 denotes an input terminal of an NTSC video signal and an audio signal, and 103 denotes an AC power supply for inputting a power supply of 100 V AC in Japan, for example. An input terminal 110 is a decoder mainly for decoding video signals and audio signals compressed by the MPEG2 system, 111 is a digital broadcast tuner, 112 is a demodulation circuit, 112 is an error correction circuit, and 114 is a data correction circuit. Multiplexer, 115, audio data buffer, 116, audio decoder, 117, video data buffer, 118
Is a video decoder, 119 is a system data buffer,
120 is a system decoder, 121 is a time control counter, 122 is a system clock generation circuit for generating a main clock of the decoder 110, 123 is an oscillator, 124
Is a first control circuit, such as a microprocessor, for mainly controlling each section of the decoder 110, and 125 is a read-only memory (hereinafter, referred to as ROM) that stores basic control information of each section of the decoder 110. ), 126 are nonvolatile read / write memories (hereinafter referred to as RAM),
127 is a first switch, 128 is an audio signal processing circuit,
129 is a second switch, 130 is a synchronizing signal generation circuit for generating a horizontal synchronizing signal, a vertical synchronizing signal, etc., 131 is interpolation processing of an input digital video signal, luminance level control processing of a frame signal when a frame signal is inserted, etc. Display memory, 1
32 is a D / A conversion circuit. 141 is an input terminal 1
02, an NTSC analog video signal,
A signal processing circuit that performs signal processing such as Y / C separation processing and A / D conversion processing on audio signals and the like. Reference numeral 150 denotes a display device that displays a video signal that has been subjected to predetermined processing.
151 is a video signal processing circuit, 152 is a deflection circuit, 153
Is a digital convergence circuit, 154 is a brightness control circuit, 155 is a display monitor having an aspect ratio of 16: 9, and 161 is a second control unit such as a microprocessor which controls the entire system of the video signal display device of the present embodiment.
Control circuit. A power supply circuit 171 generates a DC power supply from 100 V AC supplied from the input terminal 103.
72 is a regulator, 173 is a detection circuit that monitors the input and output of the power supply 171 and the regulator 172, and detects an abnormality around the power supply. 174 is a power switch that cuts off the AC power input from the input terminal 103. 181 is an audio output. Speaker.

FIG. 2 is a detailed block diagram showing an example of the configuration of the display memory 131 shown in FIG. Originally, the display memory 131 needs to process each of the luminance signal and the color difference signal. However, in FIG. 2, only the luminance signal processing unit is shown and described.

In FIG. 2, reference numeral 201 denotes an input terminal for inputting on-screen display information (hereinafter, referred to as OSD) such as a menu screen from the first control circuit 124 in FIG. 1, and reference numeral 202 denotes a luminance signal. Input terminal,
Reference numeral 203 denotes an input / output terminal for inputting / outputting a control signal from the first control circuit 124 in FIG. 1; 204, an input terminal for inputting a synchronization signal generated by the synchronization signal generation circuit 130 in FIG.
Reference numeral 05 denotes an output terminal for outputting a flag signal indicating that the OSD is superimposed on the input video signal, and reference numeral 206 denotes a luminance signal which has been subjected to OSD signal superimposition processing, frame signal insertion processing, and the like as necessary. An output terminal, 211 is an interpolation circuit, 212 is a synthesis circuit, 213 is an average luminance level calculation circuit, 214 is a memory having a capacity of at least 1H, 215 is a write control circuit, 216 is a frame signal generation circuit, and 217 is its frame signal generation circuit. A luminance level setting circuit, 218 is a counter that operates in a 1H cycle, 219 is a read control circuit,
20 is a switching circuit, and 221 is an adder.

A digital broadcast wave input to an input terminal 101 of this embodiment via a digital broadcast receiving antenna (not shown) is received by a tuner 111, demodulated by a demodulation circuit 112, and subjected to an error correction circuit. 113 is input. As shown in FIG. 4A, the received data of the digital broadcast input to the error correction circuit 113 is, for example, 188 bytes of a main data portion including video data compressed by the MPEG2 method and its control signal. , And an error detection code section 16 bytes. The main data section 1 is composed of the error detection code section 16 bytes.
Error correction or error detection of 88 bytes is performed.
The data that has been subjected to the error correction processing by the error correction circuit 113 is generally a transport data as shown in FIG.
Each packet is output as a data string of 188 bytes, which is called a stream (hereinafter referred to as TS), and is input to the demultiplexer 114 in the decoder 110.

In the demultiplexer 114, the T.D. S.
, A packetable elementary stream of audio data and video data (hereinafter referred to as PES) is restored from the data portion,
The compressed data portions of the audio PES and the video PES are respectively stored in the audio data buffer 115 and the video data buffer 11.
7 and a PES header including a control signal of each PES to the system data buffer 119. At the same time, a program clock reference (hereinafter referred to as P
A packet containing time information called "CR" is written in the T.C.R. S. And outputs it to the time control counter 121 and the system clock generation circuit 122.

In general, in digital broadcasting, a plurality of programs are time-division multiplexed on one channel. For example, FIG. 4B shows an example in which two programs are time-division multiplexed. V1 and A1 are video and audio data of program 1, and V2 and A2 are video and audio data of program 2. It is. As described above, a plurality of programs are time-division multiplexed. S. In order to select a target program from, although not shown, the demultiplexer 114 receives a control signal output from the first control circuit 124 and refers to the header of each packet according to the control signal. Voice PE of the desired program
S, the video PES is restored, the audio data buffer 115,
Data is output to the video data buffer 117 and the system data buffer 119, respectively.

The PCR output from the demultiplexer 114 and the output of the oscillator 123 are input to the system clock generation circuit 122, and the oscillation frequency of the oscillator 123 is controlled with reference to the input PCR, and Is generating the system clock. On the other hand, the time control counter 121 similarly controls the operation of the internal counter with reference to the PCR output from the demultiplexer 114, generates information for controlling the decoding timing of compressed data, the output timing, and the like, The information is output to the first control circuit 124.

The digital audio data input to the audio decoder 116 via the audio data buffer 115 is subjected to data compression decoding by the audio decoder 116, and further from the speaker 181 via the switch 127 and the audio signal processing circuit 128. Is output.

On the other hand, the digital compressed video data passed through the video data buffer 117
Is input to

Here, a decoding process of MPEG2 compressed video data, which is used as an example of a digital broadcasting compression method in the present embodiment, will be described.

FIG. 5 shows MPEG2T. S. FIG. 5 is a block diagram of an example of a general decoder of FIG.
Is an input terminal for digital data, 502 is an input terminal for inputting a decoder control signal from the system decoder 120,
Reference numeral 503 denotes an output terminal for outputting a luminance signal and a color difference signal of the decoded video signal, 511 denotes a variable length decoding circuit for decoding variable length encoded data, 512 denotes an inverse quantization circuit, 513 denotes an inverse orthogonal transform circuit, 514 is an adder, 515
Is a demultiplexer, 516 and 517 are first,
And a second prediction memory 518, an averaging circuit 519,
520 is a first and second selection circuit, respectively.

The compressed video data of the MPEG2 system includes I picture, P picture, B picture for each frame or field.
It is composed of pictures. I picture is the previous and next frame,
Or P-picture is data compressed by forward prediction using the I-picture, and B-picture is bidirectional prediction using both the I-picture and P-picture. Is data compressed by FIG. 6 shows an example of the configuration. In FIG. 6, the interval between I pictures is 15 frames, and the interval between I and P pictures is 3 frames.

In the video decoder 118 shown in FIG. 5, if the data input from the input terminal 501 is the I picture data, the variable length decoding circuit 511 performs variable length decoding processing, the inverse quantization circuit 512 performs inverse quantization processing, After being subjected to inverse orthogonal transformation processing by the inverse orthogonal transformation circuit 513, the result is stored in one of the first and second prediction memories 516 and 517, and output from the output terminal 503 via the second selection circuit 520. . In this case, the first selection circuit 519 outputs “0” and does not perform the addition processing in the adder 514. On the other hand, if the data input from the input terminal 501 is P
In the case of picture data, after the variable length decoding process, the inverse quantization process, and the inverse orthogonal transform process, the I picture of the I picture stored in one of the first and second prediction memories 516 and 517 is obtained. The decoded image is added by the adder 514 to restore the original image data. The restored image data is stored in the first or second prediction memory 516,5.
17 and is output from the output terminal 503 via the second selection circuit 520. When the data input from the input terminal 501 is B picture data,
Similarly, after the variable length decoding process, the inverse quantization process, and the inverse orthogonal transform process, the I picture stored in the first and second prediction memories 516 and 517 in the adder 514,
And the average value of the decoded images of the P pictures is added to restore the original image data. The restored image data is output from the output terminal 503 via the second selection circuit 520. In the case of a B picture, the first or second
Is not stored in the prediction memories 516 and 517. The switching of the signal processing, that is, the control of the first and second selection circuits 519 and 520 is performed by the system decoder 1 shown in FIG.
At 20, a control signal based on the type of picture detected from the PES header is input from the input terminal 502 and is performed.
The video signal decoded by the video decoder 118 has a luminance signal and a color
9 to the display memory 131.

Next, the processing in the display memory 131 will be described with reference to FIG.

The luminance signal of the digital video input from the input terminal 202 is first subjected to an interpolation process in an interpolation circuit 211 according to the number of effective pixels of the input digital video.
For example, a digital broadcast cited as an example in the present embodiment has an effective pixel number of 1 horizontal as an image format.
920 pixels, 1080 vertical lines HD format,
Effective pixel number 704 horizontal pixels, vertical 480 lines SD wide format, effective pixel number 640 horizontal pixels, 4 vertical pixels
It is assumed that three types of image display formats of the 80 line SD format are supported. In this case, as shown in FIG. 7, for example, H
In the case of an image in the D format, the process of directly changing the number of horizontal pixels by 30/11 and the number of vertical lines by 9/4 in the case of the SD wide format (see FIG. In the case of the SD format, the process of multiplying both the number of horizontal pixels and the number of vertical lines by 9/4 ((c) in the same figure)
Is performed by the interpolation circuit 211.

The image data subjected to the interpolation processing by the interpolation circuit 211 is then subjected to synthesis of OSD information in the synthesis circuit 212 as required. The OSD information is, for example, a menu screen at the time of image quality adjustment by the user or at the time of timer reservation, and is set by the first control circuit 124 in FIG.
This is the output data.

The data output from the synthesizing circuit 212 is output to the memory 214 and also to the average luminance level calculating circuit 213. The average luminance level calculation circuit 213 calculates the average level of the luminance of each pixel in each image frame after the interpolation processing, which is information for controlling the luminance level of the frame signal when the frame signal is inserted, which will be described later. In this processing, for example, the luminance level of each pixel of 1440 horizontal pixels and 1080 vertical lines (see FIG. 6C) subjected to the interpolation processing, that is, numerical data represented by digital 8 bits is integrated for one frame. This is done by:
This integration process is performed for each frame at 1440 pixels × 108
Although the integration may be performed by integrating 0 lines = 1, 555, and 200 pixels, it is usually sufficient to integrate the luminance level once for i pixels (i is an arbitrary natural number). In this way, if the luminance levels are integrated once for each i pixel, it is possible to realize a simpler circuit than to integrate the luminance levels for all the pixels, and to simplify the processing. Can be.

The average luminance level of each frame obtained by the processing by the average luminance level calculation circuit 213 is output to the first control circuit 124 of FIG. The first control circuit 124 sets the luminance level of the frame signal when inserting the frame signal from the average luminance level of each frame calculated by the average luminance level calculation circuit 213, and sets the luminance level in the luminance level setting circuit 217. Output control information. The luminance level setting circuit 217 sets the luminance level of the frame signal according to the control information from the first control circuit 124, and outputs the frame signal from the frame signal generation circuit 216 to the switching circuit 220. The switching circuit 220 is a counter 2 that operates in synchronization with the horizontal synchronization signal input from the input terminal 204.
In response to the control signal from the controller 18, one of the interpolated image data read from the memory 214 and the frame signal data output from the frame signal generation circuit 216 is selected and output to the adder 221. .

The memory 214 has a capacity of at least 1H or more, specifically, a capacity of at least 1920 bytes. Addresses 0 to 1919 are appropriately used according to an input image. . For example, as shown in FIG.
When an HD format image having 920 pixels and 1080 vertical lines is input, or an SD wide format image having 704 horizontal pixels and 480 vertical lines as shown in FIG. Horizontal 1
In the case of an image converted into 920 pixels and 1080 vertical lines, data of 1920 pixels per 1H is sequentially written from address 0 to address 1919 of the memory 214. Also, as shown in FIG. 7C, the input terminal 202 has an effective pixel count of 640 horizontal pixels and 480 vertical lines.
In the case of an image in which a D format image is input and converted into 1440 horizontal pixels and 1080 vertical lines by the interpolation circuit 211, that is, in the case of the image shown in FIG. 8A, data of 1440 pixels per H is stored in the memory 214. Address 2
The data is sequentially written from address 40 to address 1679. The control of the write address is performed according to a control signal input from the first control circuit 124 via the input / output terminal 203, that is, format information of the input image.

On the other hand, the reading operation from the memory 214 is performed regardless of the format of the input image signal.
The operation is always performed in a constant manner in response to the control signal from the control unit 17. That is, when reading data from the memory 214, addresses 0 to 1919 of the memory are sequentially read in synchronization with the synchronization signal input from the input terminal 204. The image at that time is as shown in FIG.

The setting of the luminance level of the frame signal portion in the luminance level setting circuit 217 and the switching operation of the switch 220 are performed in the same manner as the reading operation of the memory 214.
4 is performed in synchronization with the synchronization signal input from the control unit 4. FIG. 9 shows an operation enable signal of the luminance level setting circuit 217 and a switching signal of the switch 220. FIG. 9B shows an operation enable signal of the luminance level setting circuit 217. The luminance level setting circuit 217 switches the frame signal whose luminance level has been adjusted during the period in which the enable signal is at the "H" level to the switch 22.
0 is output. FIG. 9C shows a switching signal of the switch 220, and the switch 220 outputs the switching signal H ′.
During the level period, the output of the memory 214 is selected and output,
In other periods, the output of the luminance level setting circuit 217 is selected and output. As a result, image data shown in FIG. 8C in which the luminance level of the frame signal portion is adjusted is obtained.

As described above, the display monitor 15 shown in FIG.
In the case where a video signal having an aspect ratio different from the aspect ratio 5 is displayed on the display monitor 155, the inserted frame signal includes a luminance signal having a level controlled based on the average luminance level calculated for each frame of the video signal. , It is possible to give substantially uniform deterioration to the display device, for example, the portion where the video signal of the phosphor of the cathode ray tube is displayed and the portion where the frame signal is displayed.
That is, the display device does not need to have a difference in the degree of luminance deterioration within the same screen. As a result, even when a video signal having the same aspect ratio as that of the display monitor 155 is next displayed on the display monitor, there is no luminance difference due to the difference in the degree of luminance deterioration in the same screen. .

The brightness level setting process of the frame signal in the brightness level setting circuit 217 is performed based on only the average brightness level of each frame for each frame, that is, using only the average brightness level information of one frame. The brightness level of the frame signal may be set, but in this case, for example, when the video signal portion suddenly changes from a dark screen to a bright screen, the brightness level of the frame signal also changes rapidly, Visually uncomfortable. Therefore, the average brightness level information of each frame calculated by the average brightness level calculation circuit 213 is further integrated in the first control circuit 124 of FIG. 1 to some extent, for example, for about 10 minutes, and this information is used to calculate the frame signal. Try to set the brightness level. In this way, even when the video signal portion suddenly changes from a dark screen to a bright screen, the luminance level of the frame signal changes gradually, so that it does not cause visual discomfort. However, this does not apply when the user changes the program selection, that is, when the channel is changed. This is because, when the video signal is changed abruptly by changing the channel, even if the luminance level of the frame signal changes abruptly, there is not so much discomfort. Therefore, when the user changes the channel in this way, the luminance level of the frame signal is set to a predetermined luminance level (for example, 4
(The luminance level of about 0IRE), and the integration of the average luminance level may be started again from that point.

In any case, a frame signal that is too bright causes visual discomfort, and a frame signal that is too dark cannot achieve the object of the present invention. Therefore, the luminance level of the frame signal is set to the calculated average luminance level. Accordingly, for example, 60IR
It is desirable to control the luminance level in a range from about E to about 20 IRE.

In the above description, the processing of the luminance signal in the display memory 131 has been described, but basically the same processing is performed for the processing of the color difference signal. That is, in the processing of the color difference signal, the average luminance level calculation circuit 213 and the luminance level setting circuit 216 do not perform the average luminance level calculation processing for each frame and the luminance level setting processing of the frame signal portion. The conversion processing in 211, the writing to the memory 214, and the reading processing are performed in the same manner as the processing of the luminance signal. In particular, the process of reading data from the memory 214 needs to be performed simultaneously with the timing of reading the luminance signal in synchronization with the synchronization signal.

A flag indicating that the OSD signal output from the display memory 131 shown in FIGS. 2 and 1 has been superimposed is provided to the brightness control circuit 154 shown in FIG. The luminance signal and the chrominance signal appropriately controlled according to the input video signal are input to the video signal processing circuit 151 via the D / A conversion circuit 132, respectively.
The horizontal synchronizing signal and the vertical synchronizing signal generated by the synchronizing signal generation circuit 130 are input to the display memory 131 and simultaneously to the deflection circuit 152.

The video signal processing circuit 151 converts the input luminance signal and color difference signal into RGB primary color signals, and amplifies the input signal voltage (1 V) to a voltage of about 100 V for driving the display monitor 155. Processing, DC reproduction, hue adjustment, contour correction, etc. are performed. The deflection circuit 152 controls the deflection of the electron beam in synchronization with the input horizontal synchronization signal and vertical synchronization signal, and the digital convergence circuit 153 adjusts the convergence of each color. The control processing in each circuit described above is performed in accordance with a signal input to each circuit and a control signal from the second control circuit 161.

Further, in the video signal display device of this embodiment,
If any abnormality occurs in the display device 150, the switch 174 is controlled to perform a process of cutting off the AC power input from the input terminal 103.

At the same time, the detection circuit 173
1 and the input / output of the regulator 172, and detects a power supply circuit or some other abnormality, for example, a situation such as a drop in power supply voltage, and transmits the information to the first control circuit 124. In this way, when a situation occurs, such as a drop in the power supply voltage or the like, abrupt interruption of the power supply or the like, which may occur regardless of the user's intention, the situation is stored in the first control circuit 124. The information set by the user is stored in the RAM 126
As a result, the power supply is momentarily interrupted due to the above situation, and even when the system is restarted, the data written in the RAM 126 is read, so that the power supply is instantaneously interrupted without bothering the user. It is possible to reproduce the previous situation.

As described above, when the apparatus of the present invention is used, a video signal having an aspect ratio equal to that of the display monitor 155 is displayed as it is, and a frame signal is inserted for a video signal having an aspect ratio different from that of the display monitor 155. When displaying on the display screen, the degree of the luminance deterioration of the display monitor 155 is determined at various points in the screen by inserting and displaying a frame signal whose luminance level is adjusted according to the average luminance level of each frame. It becomes possible to make it almost uniform.

Next, the NT input from the input terminal 102
A case where an SC video signal is displayed on the display monitor 155 will be described below.

When displaying an NTSC video signal, the signal processing circuit 141 performs Y / C separation processing, A / D conversion processing, and the like on the NTSC video signal input from the input terminal 102. The digitally sampled luminance signal and color difference signal are output to the display memory 131 via the switch 129. The control of the switch 129 in this case is based on the fact that the video signal of the NTSC system is input from the input terminal 102.
4 performs detection.

The signal processing in the display memory 131 is basically the same as the processing described with reference to FIG.
However, the interpolation processing in the interpolation circuit 211 differs depending on the digital sampling method at the time of A / D conversion in the signal processing circuit 141 described above. For example, when the input NTSC video signal is digitally sampled at 14.3 MHz, which is four times the carrier frequency, in the signal processing circuit 141, the number of effective pixels per frame is as shown in FIG. In addition, the number of horizontal pixels is 768 and the number of vertical lines is 480. Therefore, the interpolation circuit needs to increase the number of horizontal pixels by 15/8 and increase the number of vertical lines by 9/4. For example, when digitally sampling a video signal of the NTSC system at 13.5 MHz, the number of effective pixels per frame is as shown in FIG.
As shown in (e), the number of horizontal pixels is 720, and the number of vertical pixels is 480.
Processing to increase the number of vertical lines by 9/4 is required. Further, for example, when the NTSC video signal is digitally sampled at 27 MHz, the number of effective pixels per frame is 1440 horizontal as shown in FIG.
The number of pixels is 480 vertical lines. In the interpolation circuit, it is necessary to perform a process of multiplying the number of vertical lines by 9/4 while keeping the number of horizontal pixels unchanged.

The image data subjected to the interpolation processing in the interpolation circuit 211 is then written into the memory 214 and the average luminance level calculation circuit 213 calculates the average luminance level. Since this is the same as the case at the time of reception, the description is omitted.

The current NT digitally sampled on the display monitor 155 having an aspect ratio of 16: 9 as described above
Even in the case of displaying an SC video signal, the same effect can be obtained by performing the interpolation processing according to the digital sampling frequency as described above.

FIG. 10 shows the display memory 131 of FIG.
2 is a block diagram showing a configuration example different from that of FIG. FIG.
2, components having the same numbers as those in FIG. 2 operate in the same manner as in FIG.
Memory having a capacity of more than one minute, 235 is a write control circuit,
238 is a read control circuit, and 239 is a switching circuit.

In FIG. 10, an interpolation circuit 211, an average luminance level calculation circuit 213, a luminance level setting circuit 217
Are the same as the respective circuits shown in FIG. 2, and the image data subjected to the same processing is stored in the memory 2 via the switching circuit 239.
34.

Like the memory 214, the memory 234 has a capacity of at least 1H, specifically, at least 19 hours.
It has a capacity of 20 bytes or more, and addresses 0 to 1919 are appropriately used according to the input image. For example, when an HD format image having 1920 effective pixels and 1080 vertical lines is input to the input terminal 202 shown in FIG.
(B) Effective pixels: horizontal 704 pixels, vertical 48
0 line SD wide format image is input,
In the case of an image converted into 1920 horizontal pixels and 1080 vertical lines by the interpolation circuit 211, data of 1920 pixels per 1H is stored in the memory 234 from address 0 to 1
The data is sequentially written to address 919. Also, the input terminal 20
2, the number of effective pixels is 640 pixels in the horizontal direction shown in FIG.
An image in the SD format of 480 vertical lines is input, and 1440 horizontal pixels and 1080 vertical pixels are input by the interpolation circuit 211.
In the case of the image converted to the line, that is, the image shown in FIG. 8A, data of 1440 pixels per 1H is sequentially written into the memory 234 at addresses 240 to 1679.

Further, the frame signal whose luminance level is controlled by the luminance level setting circuit 217 is stored in the memory 234 by controlling the switching circuit 239 and the write control circuit 235 to address addresses 0 to 239 and address 1.
The data is appropriately written from addresses 680 to 1919. In the reading of the memory 234, by sequentially reading addresses 0 to 1919, it is possible to insert a frame signal whose luminance level is controlled on the left and right of the original video signal, and the video signal shown in FIG. Can be obtained.

As described above, even when the display memory 131 in FIG. 1 is configured as shown in FIG. 10, the same effect as in the configuration in FIG. 2 can be obtained. The calculation of the average luminance level for each frame is performed in the case of the configuration shown in FIG.
May be performed using the image data after the interpolation processing in the interpolation circuit 211 and the synthesis processing with the OSD information in the synthesis circuit 212 as described above, or the interpolation in the interpolation circuit 211. Image data before processing may be used. If the image data before performing the interpolation processing in the interpolation circuit 211 is used, for example, when the input video is the SD wide format or the SD format, the number of pixels to be subjected to the integration processing is small. The average luminance level of each frame can be calculated by the processing.

If the video signal displayed by the video signal display device is limited to a received wave of a digital broadcast, that is, a video having no input terminal 102, signal processing circuit 141, and switches 127 and 129 in FIG. In the case of a signal display device, the calculation processing of the average luminance level can be performed in the video decoder 118. That is, in the data compression of the MPEG2 system, one frame image is divided into blocks of 8 horizontal pixels and 8 vertical lines, each block is orthogonally transformed, then quantized, and the result is subjected to variable-length encoding to compress the image. Is going. That is, an image having 704 horizontal pixels and 480 vertical lines in each frame is divided into 44 × 30 × 8 blocks and processed as shown in FIG. By integrating the DC components of the data subjected to the orthogonal transformation, it is possible to calculate the average luminance level for each frame.

A video decoder 118 for realizing the above processing
12 is shown in FIG. In the figure, components having the same numbers as those in FIG. 5 operate in the same manner as in FIG. 5, and 551 is an output terminal for outputting the calculated average luminance level of each frame to the first control circuit 124. And
Reference numeral 561 denotes a DC extraction circuit that extracts a DC component from the data sequence that has been subjected to the inverse quantization process. Reference numerals 562 and 563 denote first and second DC memories that store the DC component extracted by the DC extraction circuit 561. Averaging circuit of 2, 565
Is a third selection circuit, 566 is a second adder, and 567 is an average luminance level calculation circuit.

In FIG. 12, the data that has been subjected to the inverse quantization processing by the inverse quantization circuit 512 is input to the inverse orthogonal transform circuit 513, and is also input to the DC extraction circuit 561 from the data string that has been inversely quantized. DC components are extracted.
The DC component data extracted by the DC extraction circuit 561 is
In the case of an I picture, it is stored in the first or second DC memory, and at the same time, “0” is added by the adder 566 and input to the average luminance level calculation circuit. Also, P
In the case of a picture, the DC of the I picture stored in the first or second DC memory is stored in the adder 566 at the same time when the DC is stored in the first or second DC memory.
The components are added and input to the average luminance level calculation circuit. Similarly, in the case of a B picture, the adder 566 adds the average values of the DC components of the I picture and the P picture stored in the first and second DC memories to obtain an average luminance. It is input to the level calculation circuit. An average luminance level is calculated using the DC components of the input blocks, and the first control circuit 12
By outputting the calculation result to No. 4, it is possible to calculate the average luminance level for each frame. in this case,
The DC component is an average value of luminance levels of 8 pixels × 8 lines = 64 pixels in each block. By calculating the average luminance level using this DC component, a simple circuit and high accuracy for each frame can be used. The average luminance level can be calculated.

In this embodiment, the format of the video signal of the digital broadcast to be received is HD format with 1920 effective pixels and 1080 vertical lines, SD wide format with 704 effective pixels and 480 vertical lines. Effective pixel number 640 horizontal pixels,
Although the description is limited to the three types of image display formats of the vertical 480 line SD format, the effects of the present invention are not limited to the video format. In the above description, the luminance level of the frame signal to be inserted is controlled by calculating the average luminance level of each frame of the input video signal. However, the same effect can be obtained even if the processing is performed for each field. It is possible to get.

[0056]

According to the video signal display apparatus of the present invention, when a video signal having an aspect ratio different from the aspect ratio of the display device is displayed on the display device, a frame signal to be inserted is added to each frame of the video signal. By giving a luminance signal of a level controlled based on the calculated average luminance level, substantially uniform deterioration is given to the portion where the video signal of the display device is displayed and the portion where the frame signal is displayed. This makes it possible to avoid a difference in the degree of luminance degradation within the same screen. As a result, even when a video signal having the same aspect ratio as that of the display device is displayed on the display device, a luminance difference due to the difference in the degree of the luminance deterioration does not occur in the same screen.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of a video signal display device according to the present invention.

FIG. 2 is a detailed block diagram showing an example of a configuration of a display memory 131 in FIG.

FIG. 3 is a conceptual diagram illustrating signal processing performed when displaying images having different aspect ratios.

FIG. 4 is a diagram illustrating a data format of an example of a digital broadcast received by the video signal display device according to the embodiment.

FIG. 5 is a detailed block diagram of an example of a configuration of a video decoder 118 in FIG. 1;

FIG. 6 is a diagram illustrating a format in the MPEG2 compression method.

FIG. 7 is a diagram illustrating an interpolation process in the interpolation circuit 211 of FIG. 2;

FIG. 8 is a diagram illustrating a frame signal insertion process in FIG. 2;

9 is an example of a control signal for a luminance level setting circuit 216 and a switch 219 in FIG.

FIG. 10 is a detailed block diagram showing a configuration of the display memory 131 in FIG. 1 different from that in FIG. 2;

FIG. 11 is a diagram illustrating a block division process of one frame in the MPEG2 compression method.

12 is a detailed block diagram illustrating a configuration example of the video decoder 118 in FIG. 1 including an average luminance level calculation circuit.

[Explanation of symbols]

101 digital broadcast input terminal, 102 terrestrial broadcast video signal input terminal, 110 decoder, 114 demultiplexer, 116 audio decoder, 118 video decoder, 120 system decoder, 124 first
Control circuit 128, audio signal processing circuit 130, synchronization signal generation circuit 131, display memory 132, D / A converter 150, display device 202, luminance signal input terminal 203, control signal input / output terminal Reference numeral 204: synchronization signal input terminal, 206: luminance signal output terminal, 211: interpolation circuit, 213: average luminance level calculation circuit, 214: memory, 215: write control circuit, 216: frame signal generation circuit, 217: luminance level setting circuit 219: Read control circuit, 220: Switching circuit, 221: Adder.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Toshimitsu Watanabe 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Multimedia Systems Development Headquarters, Hitachi, Ltd. (72) Inventor Masahisa Tsukahara Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa 292 Hitachi Image Information System Co., Ltd.

Claims (7)

[Claims] A frame signal insertion unit for inserting a signal into a video signal to adjust the aspect ratio of a display device; an average luminance level calculation unit for calculating an average luminance level for each field or frame of the video signal; A video signal display device comprising: a brightness level setting unit that controls a brightness level of the frame signal to be inserted according to a calculation result of the average brightness level calculation unit. 2. The image processing apparatus according to claim 1, wherein the average luminance level calculating means converts the luminance signal of the digitally sampled video signal to m (m
2. The video signal display device according to claim 1, wherein the integration is performed at a rate of one sample to one or more natural numbers) samples, and an integration result for each field or frame is set as an average luminance level of the field or frame. 3. The average luminance level calculating means performs an integrating process from the digitally sampled video signal using only sampling data at a predetermined position predetermined for each field or frame. 2. The video signal display device according to claim 1, wherein a result is an average luminance level of said field or frame. 4. A digital video signal which has been subjected to data compression processing including at least orthogonal transformation processing is input, and a video signal is obtained by decompressing the data compressed by the data compression processing.
In a video signal display device capable of displaying the video signal,
A display device having an effective display range of an arbitrary aspect ratio and displaying a video signal, a decoder for receiving the compressed data, performing a data decompression process including at least an inverse orthogonal transform process, and restoring the video signal, If the aspect ratio of the video signal restored by the decoder is different from the aspect ratio of the display device, a frame signal is inserted into the restored video signal as appropriate to match the aspect ratio of the display device. Means, an average luminance level calculating means for calculating an approximate average luminance level for each field or frame of the video signal output from the decoder, and the average luminance level is inserted according to the calculation result of the average luminance level calculating means. A video signal display device comprising: a luminance level setting unit that appropriately controls a luminance level of a frame signal. 5. The DC component extraction means for inputting a data sequence before being subjected to inverse orthogonal transform processing in the decoder and extracting a DC component for each luminance signal block from the data sequence. Means, and integrating means for integrating the extracted DC component for each luminance signal block, wherein the integrating means integrates the DC component for each input luminance signal block for each field or for each frame. 5. The video signal display device according to claim 4, wherein the integration result is an approximate average luminance level for each field or each frame of the video signal output from the decoder. 6. The brightness level setting means further calculates at least the average brightness level for each field or frame calculated by the mean brightness level calculation means by n.
The video signal display device according to any one of claims 1 to 5, wherein the video signal display device is controlled according to a result obtained by integrating (n is a natural number of 1 or more) fields or n frames. 7. A display device having an effective display range of j horizontal pixels and k vertical lines, and a digitally sampled video signal in which the number of effective pixels of each video frame is 1 horizontal and m vertical lines, and When the video signal is 1: m =
an interpolating circuit for converting the number of effective pixels of each video frame into a digital video signal of n horizontal pixels and k vertical lines, where n: k; and an effective pixel for each frame of the digital video signal converted by the interpolating circuit. And an average brightness level calculation circuit for calculating an average brightness level in the interpolation circuit having a capacity capable of storing data for at least one horizontal scanning period (hereinafter, referred to as 1H), that is, data for j pixels or more. A memory for storing the converted digital video signal of n pixels per 1H, wherein n is smaller than j and n <
When j, the luminance level of the frame signal portion of (j−n) / 2 pixels inserted on the left and right of the effective data of n pixels of each line is appropriately controlled based on the calculation result in the average luminance level calculation circuit. A luminance level setting circuit, a horizontal synchronization signal, a synchronization signal generation circuit for generating a vertical synchronization signal, and a frame signal read from the memory in synchronization with the horizontal and vertical synchronization signals generated by the synchronization signal generation circuit. A display control circuit that causes the display device to display a video signal including the horizontal and vertical synchronization signals,
(Where j, k, l, m, and n are arbitrary natural numbers).