JPH1141076A - Phase shifter and radio communication equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a phase shifter where amplitude of signals at different phases is equal to each other with excellent phase precision. SOLUTION: A ring oscillator is formed by connecting an odd number of inverters (INV1, INV2, INV3) whose delay times are adjustable depending on a voltage received from a control terminal in a ring and a load capacitor (C10, C11, C12) is connected to each output terminal of each inverter respectively to lead out signals with a phase deviation of 90 deg. from the inverter terminals. The frequency dependence of the amplitude of the output signal is reduced and the output signal as above is obtained to eliminate the need for any amplifier at the post-stage of the phase shifter and to improve the phase precision.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase shifter for generating signals having phases different from each other by 90 degrees, and relates to a technique which is effective when applied to, for example, a high frequency section of a radio communication device.

[0002]

2. Description of the Related Art A personal mobile telephone terminal (PHS), which is an example of a radio communication device, basically includes a high frequency section and a baseband section. The high-frequency section includes a new function for transmitting and receiving radio waves.
Processing of a high frequency signal of 0 MHz or more is performed. The baseband unit is a unit that processes digital signals of 10 MHz or less, a modem for performing conversion (modulation, demodulation) between digital data and an analog signal suitable for wireless transmission,
It comprises a channel codec for synchronizing digital data and the like, an audio codec for digitizing audio and performing data compression and decompression, and a microcomputer for controlling the operation of each unit.

In a high-frequency section of such a radio communication device, a reception mixer and a transmission mixer for enabling transmission and reception of radio frequency signals are provided, and high frequency signals having phases different from each other by 90 degrees are supplied to them. It has become. The signals whose phases are different from each other by 90 degrees can be generated by a relatively simple phase shifter using a combination of a resistor and a capacitor to generate an output signal of an oscillator that generates a signal of a predetermined frequency.

[0004] An example of a document describing a phase shifter is "RF DESIGN GUIDE (pages 156 to 158)" issued by Artech House Publishers in 1995.

[0005]

In a phase shifter using a combination of a resistor and a capacitor, the phase accuracy is relatively good.
Since the signal and the second signal having a phase difference of 90 degrees from the signal have different signal amplitudes, it is necessary to provide an amplifier for aligning the amplitudes of the first signal and the second signal after the phase shifter.

However, if such an amplifier for adjusting the signal amplitude is provided, the variation in delay time between the first amplifier for capturing the first signal and the second amplifier for capturing the second signal cannot be ignored. Therefore, even if a 90-degree phase shift is ensured by a combination of a resistor and a capacitor, the 90-degree phase accuracy is undesirably reduced by passing through a subsequent amplifier.

SUMMARY OF THE INVENTION An object of the present invention is to provide a phase shifter in which signal amplitudes of different phases are equal to each other and excellent in phase accuracy.

Another object of the present invention is to provide a wireless communication device provided with such a phase shifter.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, each of the control terminals has a signal input terminal, an output terminal, and a control terminal, and determines the delay time from when the logic of the signal input from the input terminal is inverted to when the signal is output from the output terminal. Odd number of inverters (INV) configured to be adjustable in accordance with the voltage input from
1, INV2, INV3) are connected in a ring to form a ring oscillator, and load capacitors (C10, C11, C12) are connected to the output terminals of each of the odd number of inverters, and are connected to the output terminals of the specific inverter. When the first signal output terminal (T11) is drawn out, the second signal output terminal (T12) is drawn out via the output terminal of another inverter different from the specific inverter.

The frequency dependence of the amplitude of the output signal is reduced by using the output signal of the inverter forming the ring oscillator to extract signals having phases shifted from each other by 90 degrees. By obtaining such an output signal, it is not necessary to dispose an amplifier at the subsequent stage of the phase shifter, and the phase accuracy is improved.

Further, since the delay time can be finely changed by changing the level of the control voltage (Vc), the phase shifter functions as a VCO (Voltage Controlled Oscillator). There is no need to provide a VCO separately from the vessel.

In a specific mode, each has a signal input terminal, an output terminal, and a control terminal, and sets a delay time from when the logic of the signal input from the input terminal is inverted to when the signal is output from the output terminal. And three inverters (INV1, INV2, INV3) configured to be adjustable in accordance with the control voltage (Vc) input from the control terminal to form a ring oscillator, thereby forming a ring oscillator.
Inverters according to the arrangement order of the first inverter,
When the second inverter and the third inverter are used, the first inverter is used.
A first load capacitance is coupled to each of the output terminal of the inverter and the output terminal of the second inverter, and a second load capacitance corresponding to a capacitance approximately twice the first load capacitance is applied to the output terminal of the third inverter. Coupled to the output terminal of the first signal (T1) via the output terminal of the second inverter.
1) is drawn out, and the output terminal (T12) of the second signal is drawn out via the output terminal of the third inverter.

Further, when n is an integer of 1 or more, 4
When the xn differential amplifiers are coupled in a ring to form a ring oscillator, and a specific differential amplifier among the 4xn differential amplifiers is the first stage, the first stage The output terminal (T21) of the first signal is drawn through the output terminal of the differential amplifier, and the output terminal (T22) of the second signal is drawn through the output terminal of the 2n + 1-th stage differential amplifier. Become.

Further, a wireless communication device can be configured including the phase shifter. An amplifier (A) is provided after the phase shifter.
MP1 and AMP2) need not be arranged, and since the phase shifter also functions as a VCO, there is no need to provide a VCO separately from the phase shifter. The size can be reduced.

[0017]

FIG. 10 shows a personal mobile telephone terminal (P).
HS) is indicated.

As shown in FIG. 10, this PHS is
It is composed of a high frequency (RF) unit 21 and a baseband unit 22, and enables wireless communication.

The high-frequency unit 21 modulates high-frequency with the audio data transmitted from the baseband unit 22 and emits a radio wave from the antenna 211 to enable transmission and reception at a radio frequency. And a receiving system for receiving a target high-frequency signal via the communication system.

The baseband unit 22 includes a modem 221, a channel codec 222, an audio codec 223, a speaker 224, a microphone 225, and a microcomputer 22.
6, liquid crystal display (LCD) 227, keypad 228,
A memory 229 is included.

The modem 221 converts (modulates, demodulates) between digital data and an analog signal suitable for wireless transmission.
I do. The modulation method is π / 4 shift QPSK (Quadrutu
re Phase Shift Keying). The data transmission rate is 384 kbps, and the modulation rate is 192 kbaud.

The channel codec 222 is disposed between the modem and the voice codec 223, and controls digital data synchronization, TDMA / TDD control, privacy control, and so on.
It performs scramble control, error detection, and voltage control of the high frequency unit.

The voice codec 223 performs voice digitization and data compression / decompression. ADP for compression and decompression
CM (Adaptive Differential Pulse CodeModulation)
64 kbps (8b /
1 sample, 8 kHz sampling) audio data
/ 32 kbps, and the reverse (expansion) of such compression is performed.

The microcomputer 226 controls the operation of the entire system including the high frequency unit 21 and the baseband unit 22 according to a predetermined program. In the microcomputer 226, man-machine interface control such as execution of communication protocol processing, key analysis of operation of the keypad 228, and display control of various information on the liquid crystal display unit 227 is performed.

The memory 229 stores a system control program executed by the microcomputer 226, user information of a person who operates the PHS, system parameters, and the like, which are read out by the microcomputer 226 as necessary. It has become.

FIG. 11 shows an example of the configuration of the high-frequency section 21.

As shown in FIG.
Are a duplexer 212 for enabling the same antenna 211 to be shared for transmission and reception, a reception up 213 for improving the S / N characteristic of a reception signal, and a band-pass filter for extracting only a target frequency band. 214, 21
7, the mixers 215 and 219, the phase shifter 216, and the output amplifier 217.

The high-frequency signal input from the antenna is transmitted to the modem 221 in FIG. 10 via the duplexer 212, the receiving amplifier 213, the band-pass filter 214, and the mixer 215.

An output signal from the modem 221 is passed through a mixer 219, a band-pass filter 218, an output amplifier 217, and a duplexer 217 to the antenna 21.
1 is transmitted. The output signals of the phase shifter 216 are input to the mixers 215 and 219. The phase shifter 216 forms signals that are 90 degrees out of phase with each other. For example, when the phase of the first signal transmitted from the phase shifter 216 to the mixer 215 is 0 degree, the phase shifter 216
The phase of the second signal transmitted from the first signal to the mixer 219 is shifted from the first signal by 90 degrees. The mixer 215 performs conversion of the received signal based on the output signal of the phase shifter 216. The output signal of the mixer 215 is transmitted to the modem 221. Mixer 21
Reference numeral 9 modulates a high-frequency signal from the phase shifter 216 with audio data from the modem 221. The phase shifter 216 also functions as a voltage controlled oscillator (VCO) whose oscillation frequency changes in accordance with the level of an input control voltage, as described later in detail. Can be adjusted by a control voltage Vc which is a part of the RF control signal transmitted from the channel codec 222 shown in FIG. This is because the transmission / reception frequency in the high frequency unit 21 is set to 915 MHz, for example, in relation to the channel control in the channel codec 222 shown in FIG.
This is because it is necessary to switch to 920 MHz or the like.

FIG. 1 shows a configuration example of the phase shifter 216.

As shown in FIG. 1, this phase shifter 216
Are three inverters INV1, INV2, INV3
And three load capacitors C10, C11, C12.

Inverters INV1, INV2, INV3
Has a signal input terminal, an output terminal, and a control terminal, and the delay time until the logic of the signal input from the input terminal is inverted and output from the output terminal is input from the control terminal. It is configured to be adjustable according to the control voltage Vc.

Inverters INV1, INV2, INV3
Are combined in a ring to form a ring oscillator. The control terminals of the inverters INV1, INV2, and INV3 are commonly connected to a terminal T10 of the phase shifter 216, and the control voltage Vc is supplied from the terminal T10 of the phase shifter 216.

The inverters INV1, INV2,
Load capacitors C10, C11, and C12 are connected between the output terminal of INV3 and the ground GND, respectively. Here, the values of the load capacitances C10 and C11 (capacity values are referred to as “C”) are equal to each other, and the value of the load capacitance C12 is set to twice (C ′ = 2C) the load capacitances C10 and C11. . The output terminals of the inverters INV1, INV2, INV3 are connected to terminals T1 for extracting signals, respectively.
0, T11 and T12. In order to extract a signal whose phase is shifted by 90 degrees, terminals T11 and T12 are used as described later in detail.

In general, in a ring oscillator using an inverter, since the number of inverters is an odd number of stages, it is impossible to extract a signal having a phase difference of 90 degrees, that is, 1/4 cycle. However, by utilizing the fact that the delay time of the inverter used in each stage is proportional to the load capacity and adopting the configuration shown in FIG. 1, signals having a phase difference of 90 degrees can be extracted as follows.

FIG. 2 shows the relationship between the delay time of the inverter and the load capacity.

As shown in FIG. 2, the delay time of the inverter increases in proportion to the load capacity. Therefore, by setting the load capacitance value of the inverter to an appropriate value as indicated by C and C ', the delay time of a particular inverter forming the ring oscillator is made twice as long as another inverter delay time. Can be. That is, according to the example of FIG. 1, if the values of the load capacitors C10 and C11 are C and the delay time in that case is τ, the value of the load capacitor C12 is C ′
= 2C, and the delay time there is 2τ. Based on this relationship, each terminal T10, T1 shown in FIG.
The operation waveforms of T1 and T12 are as shown in FIG.

The oscillation cycle of the circuit shown in FIG. 1 is 8τ because it is twice the sum of the delay times of the respective stages of the inverter. Here, since the delay time of the inverter INV3 is 2τ, when the output signal of the inverter INV2 is compared with the output signal of the inverter INV3, the delay time 2τ of the inverter INV3 and 4τ for being the inverted output in the total period 8τ are obtained. The output signal of the inverter INV2 and the output signal of the inverter INV3 for the added 6τ, that is, 、 ３ cycle.
Are out of phase. Therefore, in relative phase,
It will be 90 degrees different. Therefore, the inverter INV
By using the output signal of the inverter 2 and the output signal of the inverter INV3, signals whose phases are shifted from each other by 90 degrees can be extracted.

FIG. 7 shows the inverters INV1, INV
A configuration example of one of V2 and INV3 is representatively shown.

As shown in FIG. 7, the inverter includes a p-channel MOS transistor 71 and an n-channel MOS transistor 72 connected in series. The source electrode of the p-channel MOS transistor 71 is coupled to the high-potential-side power supply Vdd,
The source electrode of the OS transistor 72 is connected to the low potential side power supply Vs
s. p-channel type MOS transistor 7
The control voltage Vc is input to the gate electrode of the p-channel MOS transistor 71 by the control voltage Vc.
Is biased. The input signal is input to the base electrode of the n-channel MOS transistor 72, and an output signal out in which the logic of the input signal in is inverted is obtained from the collector electrode of the n-channel MOS transistor 72. The on-resistance of the p-channel MOS transistor 71 is changed according to the voltage level of the control voltage Vc, so that the delay time of the inverter can be adjusted. Actually, as shown in FIG. 1, a load capacitance is coupled to the output terminal of the inverter.
The delay time is substantially determined by the time constant of the load capacitance and the on-resistance of the p-channel MOS transistor 71.

Here, the circuit shown in FIG. 1 will be compared with the circuit shown in FIG.

In FIG. 4, the phase shifters are resistors R1, R2,
Capacitors C1 and C2 are combined to form signals whose phases are shifted from each other by 90 degrees based on the oscillation output signal of VCO 40. Since the phase difference between the output signals of the phase shifter is determined by the ratio of the resistors R1 and R2 and the capacitances C1 and C2, if R1 = R2 and C1 = C2, the phase of the output signal is As shown in FIG. 5, they are shifted from each other by 90 degrees. However, as shown in FIG. 6, although the signal amplitude of the output signal becomes substantially equal in the vicinity of the frequency fc, the amplitude difference between the output signals becomes larger as the frequency deviates from the frequency fc. This means that when the resistance and the capacitance deviate from the predetermined values due to variations in the manufacturing process, the output amplitude also deviates accordingly. The deviation of the output amplitude causes a decrease in receiving sensitivity and the like. Therefore, when the circuit configuration shown in FIG. 4 is employed, the amplifiers AMP1 and AMP are provided after the phase shifter.
2 is arranged. At this time, the amplifier AMP
1, AMP2 functions as a limiter and acts to make the output amplitude of the output signal of the phase shifter uniform. However, by arranging the amplifiers AMP1 and AMP2, although the signal amplitudes are made uniform,
1 and AMP2, there is a manufacturing variation. Therefore, due to a difference in delay time between the amplifiers AMP1 and AMP2, the phase difference between the output signal of the phase shifter and 90 °
The output may be shifted on the output sides of P1 and AMP2.

On the other hand, in the configuration shown in FIG.
Since the output signal of the inverter forming the ring oscillator is used, the amplitude of the output signal does not depend on the frequency. In addition, since the output levels of the terminals T10 to T12 are equal to each other, the amplifiers AMP1 and AMP2 as shown in FIG.
Therefore, the phase accuracy can be improved. Also,
Since the delay time can be finely changed by changing the level of the control voltage Vc, the circuit shown in FIG.
Also functions as a VCO whose oscillation frequency changes in accordance with the level of the control voltage Vc supplied from the control circuit Vc. When the circuit configuration shown in FIG. 1 is employed, VCO as shown in FIG.
There is no need to provide CO40. That way phase shifter and VC
By having the function of O, the circuit area can be reduced as compared with the case where the phase shifter and the VCO are separately formed. This is particularly effective in reducing the size of a semiconductor chip when, for example, forming the high-frequency unit 21 on one semiconductor substrate.

FIG. 8 shows another configuration example of the phase shifter 216.

When n is an integer of 1 or more, the phase shifter 216 can be formed by 4 × n differential amplifiers. The phase shifter 216 shown in FIG. 8 is a case where n = 1, and is formed by coupling four differential amplifiers 81, 82, 83, and 84 in a ring shape. Differential amplifiers 81, 82, 8
In the coupling of 3,84, basically, the non-inverting output terminal of the preceding stage differential amplifier is connected to the non-inverting input terminal of the following stage differential amplifier, and the inverting output terminal of the preceding stage differential amplifier is connected to the subsequent stage differential amplifier. Although each is coupled to the inverting input terminal of the amplifier, only the coupling between the output terminal of the differential amplifier 84 and the input terminal of the differential amplifier 81 is different from the other couplings. That is, in order to enable the oscillation operation in the coupling of the differential amplifier, the non-inverting output terminal of the differential amplifier 84 is coupled to the inverting input terminal of the differential amplifier 81, and the inverting output terminal of the differential amplifier 84 It is coupled to the non-inverting input terminal of the dynamic amplifier 81.

The differential amplifiers 81, 82, 83,
Reference numeral 84 allows the delay time to be adjusted according to the level of the control voltage Vc. The phase shift of 8 stages of the differential amplifier is 36
At 0 degree, the phase shift at the four stages of the differential amplifier is 180 degrees. Therefore, when the first signal is obtained from the non-inverting output terminal of the first stage differential amplifier 81, the first signal is Phase 9
The second signal shifted by 0 degrees can be obtained from the non-inverting output terminal of the third-stage differential amplifier 83. That is, the terminal T21 for obtaining the first signal from the non-inverting output terminal of the first-stage differential amplifier 81 is provided, and the terminal 83 for obtaining the second signal from the output terminal of the third-stage differential amplifier 83 is provided. With this arrangement, the phases are mutually 90 degrees through the terminals T21 and T22.
Different signals can be extracted.

In FIG. 8, four differential amplifiers 81, 82,
Although the phase shifter is configured using 83 and 84, the phase shifter can be formed by 4 × n differential amplifiers.
In this case, when the first stage, the second stage, and the third stage are arranged in the order of arrangement of the differential amplifiers, the output terminal of the first stage differential amplifier and the output terminal of the 2n + 1th stage differential amplifier By extracting the first signal and the second signal, signals having phases different from each other by 90 degrees can be obtained.

FIG. 9 shows a differential amplifier 81 shown in FIG.
To 84 are representatively shown.

As shown in FIG. 9, an n-channel type M
OS transistors 91 and 92 are differentially coupled. Resistance 9
Reference numerals 4 and 95 denote loads of n-channel MOS transistors 91 and 92, respectively, which are coupled to the high-potential-side power supply Vdd. Further, an n-channel MOS transistor 91,
An emitter electrode 92 is connected to a low potential side power supply Vs via an n-channel MOS transistor 93 forming a constant current source.
s. N-channel MOS transistor 9
1 is a non-inverting input terminal, and the gate electrode of the n-channel MOS transistor 92 is an inverting input terminal. The control voltage Vc is input to the gate electrode of the n-channel MOS transistor 93, and the drain and source current of the n-channel MOS transistor 93 are controlled according to the level of the control voltage Vc. Thus, the signal delay time of the differential amplifier can be controlled.

Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited to the embodiments and can be variously modified without departing from the gist thereof. No.

For example, in FIG. 1, a phase shifter is formed by three inverters. However, as shown in FIG. (Limited to an odd number) can be combined in a ring shape.

In the above description, the case where the invention made by the present inventor is mainly applied to a personal mobile telephone terminal, which is a field of use as a background, has been described. It can be widely applied to electronic circuit devices.

The present invention can be applied on condition that at least signals having different phases are handled.

[0054]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, by using the output signal of the inverter forming the ring oscillator to derive signals having different phases from each other, it is possible to reduce the frequency dependence of the output signal amplitude. Since such an output signal is obtained, it is not necessary to dispose an amplifier for aligning the signal amplitude at the subsequent stage of the phase shifter, and the phase accuracy is reduced due to a variation in the manufacturing process of such an amplifier. Can be eliminated. Further, by changing the level of the control voltage, the delay time can be finely changed. Since the delay time can function as a VCO (voltage controlled oscillator) while being a phase shifter, a VCO is provided separately from the phase shifter. No need.

Further, when n is an integer of 1 or more, 4 × n differential amplifiers whose delay time can be adjusted according to the control voltage are connected in a ring to form a ring oscillator, When a specific one of the 4 × n differential amplifiers is the first stage, the output terminal of the first signal is drawn out through the output terminal of the first stage differential amplifier.
By drawing out the output terminal of the second signal via the output terminal of the differential amplifier of the (+1) -th stage, the frequency dependence of the output signal amplitude can be reduced. By obtaining such an output signal, it is not necessary to dispose an amplifier for adjusting the signal amplitude at the subsequent stage of the phase shifter, so that signals having mutually different phases can be accurately extracted. By changing the level of the control voltage, the delay time can be delicately changed. Since the delay time can also function as a VCO, there is no need to provide a VCO separately from the phase shifter.

Then, a wireless communication device can be constructed including the above-mentioned phase shifter. In this case, it is not necessary to dispose an amplifier after the above-mentioned phase shifter.
Since there is no need to provide a CO, the circuit size of the wireless communication device can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating a configuration example of a phase shifter according to the present invention.

FIG. 2 is a characteristic diagram showing a relationship between a load capacity and a delay time in the phase shifter shown in FIG.

FIG. 3 is an operation timing chart of a main part in the phase shifter shown in FIG. 1;

FIG. 4 is a circuit diagram illustrating a configuration example of a phase shifter as a comparison and contrast of the phase shifter illustrated in FIG. 1;

FIG. 5 is a phase characteristic diagram of the phase shifter shown in FIG.

6 is an amplitude characteristic diagram of the phase shifter shown in FIG.

FIG. 7 is a circuit diagram showing a configuration example of an inverter applied to the phase shifter shown in FIG. 1;

FIG. 8 is another configuration example circuit of the phase shifter according to the invention.

9 is a circuit diagram illustrating a configuration example of a differential amplifier applied to the phase shifter illustrated in FIG. 8;

FIG. 10 is a block diagram of an overall configuration example of a personal mobile telephone terminal including the phase shifter shown in FIG. 1 or FIG.

11 is a block diagram showing a configuration example of a high-frequency unit included in the personal mobile telephone terminal shown in FIG.

[Explanation of symbols]

 INV1 to INV3 Onverters C10 to C12 Load capacitance 81 to 84 Differential amplifiers T10 to T13, T21 to T22 Terminal 21 High frequency section 22 Baseband section 211 Antenna 212 Duplexer 213 Receive amplifier 214, 218 Bandpass filter 215, 219 Mixer 216 Phase shift 217 Transmit buffer 221 Modem 222 Channel codec 223 Voice codec 224 Speaker 225 Microphone 226 Microcomputer 227 Liquid crystal display 228 Keypad

Claims (4)

[Claims] 1. A phase shifter for generating a first signal having a predetermined frequency and a second signal having a phase shifted by 90 degrees from the first signal, the phase shifter having a signal input terminal, an output terminal, and a control terminal. An odd number of inverters configured such that the delay time from when the logic of the signal input from the input terminal is inverted to when the signal is output from the output terminal can be adjusted according to the voltage input from the control terminal Are connected in a ring to form a ring oscillator, a load capacitance is connected to the output terminals of the odd-numbered inverters, and the output terminal of the first signal is drawn out via the output terminal of the specific inverter. A phase shifter, wherein an output terminal of the second signal is drawn out via an output terminal of an inverter different from the specific inverter. 2. A phase shifter for generating a first signal having a predetermined frequency and a second signal having a phase shifted by 90 degrees from the first signal, the phase shifter having a signal input terminal, an output terminal, and a control terminal. The delay time from when the logic of the signal input from the input terminal is inverted to when the signal is output from the output terminal can be adjusted according to the control voltage input from the control terminal. Inverters are coupled in a ring to form a ring oscillator. When the three inverters are a first inverter, a second inverter, and a third inverter according to the arrangement order, an output terminal of the first inverter, and The first load capacitance is coupled to the output terminals of the two inverters, respectively.
A second load capacitance corresponding to double the capacitance is coupled, an output terminal of the first signal is drawn out via an output terminal of the second inverter, and an output terminal of the second signal is output via an output terminal of the third inverter. Wherein the phase shifter is drawn. 3. A phase shifter for generating a first signal having a predetermined frequency and a second signal having a phase shifted by 90 degrees from the first signal, wherein n is an integer of 1 or more. 4 × n differential amplifiers configured so that the delay time of an output signal corresponding to the signal input from the control circuit can be adjusted according to the control voltage are connected in a ring to form a ring oscillator, and the 4 × n When a specific differential amplifier among the differential amplifiers is the first stage, the output terminal of the first signal is drawn out through the output terminal of the first stage differential amplifier, and the 2n + 1-th stage is output. Via the output terminal of the differential amplifier, the second
A phase shifter characterized in that a signal output terminal is drawn out. 4. A radio communication device including a radio frequency unit for transmitting and receiving a radio frequency signal and a baseband unit for processing a signal transmitted and received via the radio frequency unit, wherein the radio frequency unit includes a radio frequency signal. And a transmission system mixer for enabling communication of an audio signal according to the first embodiment. A first signal is supplied to the reception system mixer, and a phase of the first signal is different from the first signal by 90 degrees to the transmission system mixer. A 90-degree phase shifter for supplying two signals; and wherein the 90-degree phase shifter is provided as the 90-degree phase shifter.
A wireless communication device characterized by applying the phase shifter described in the paragraph.