JPH1140733A - Semiconductor package structure - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor package structure which can have an excellent high-speed transmission characteristics that can completely remove external noise at a high speed of 100 MHz or more as a response speed to the high-speed processing speed of a CPU. SOLUTION: In a semiconductor package having leads 2 positioned on a semiconductor chip 10, the leads 2 on the chip 10 are made to have a 3-layer structure, that is, a layer of a group of leads 2, a power metallic layer 4 and a grounding metallic layer 3. The power layer 4 is provided on one side of the lead 2 group layer, and the grounding layer 3 is on the other side thereof. The power and grounding layers 4 and 3 are sized so as to cover substantially all surface of all the leads 2 as viewed from an array direction of the lead 2 group.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a LOC (Lead O) in which a lead frame is located on a semiconductor chip.
The present invention relates to a semiconductor package having an n-chip (n-chip) structure, and particularly to a highly integrated multi-bit DRAM (Dynamic Ra).
The present invention relates to a structure of a semiconductor package excellent in high-speed transmission characteristics suitable for Ndam Access Memory).

[0002]

2. Description of the Related Art A semiconductor package having a LOC structure has a structure in which leads for making electrical connections such as IOs for exchanging signals are provided on a semiconductor chip. It has various advantages such as becoming.

A lead has an outer lead which is a lead part outside the resin and an inner lead which is a lead part inside the resin. In a general semiconductor package, the outer lead and the inner lead are made of one metal plate. Is formed by processing. For this reason, there is a problem that the number of external leads inevitably increases due to the improvement in the degree of integration of the semiconductor chip. When the lead density increases and the lead gap decreases, the leads come close to each other and cause electromagnetic interference. In particular, when transmitting a high-frequency signal, crosstalk occurs, and good transmission characteristics cannot be obtained.

In order to solve this problem, there has been proposed a technique in which another inner lead is superimposed on the inner lead (Japanese Patent Application Laid-Open Nos. Hei 5-226559 and Hei 6-17720).
No. 2, JP-A-7-7121).

[0005] As a representative example, FIGS.
No. 177202 is disclosed. this is,
On the outer surface of the semiconductor chip 21, external connection electrodes 22, 23, 24 for power supply, grounding, and signal are mixed and arranged, and the external connection electrodes 22, 23, 24 are sandwiched therebetween.
First and second insulating tape bases 2 disposed on both sides thereof
The first and second insulating tape bases 25 have signal leads 27 on one surface and power bus bar leads 28 on the other surface.
And a signal lead 29 is provided on one surface of the front and back surfaces of the second insulating tape base material 26, and a ground bus bar lead 30 is provided on the other surface. In the case of this structure, the signal leads 27 and the power supply bus bar leads 28 are vertically separated from each other, and the signal lead 29 and the ground bus bar leads 30 are vertically separated from each other. Therefore, the number of external connection electrodes can be reduced. Although there is an effect that can be achieved, these leads are separated even on the plane of the semiconductor chip 21. That is, the power supply line or the ground line is located away from the signal line, and therefore, it is not possible to effectively prevent the transfer of external noise to the signal line.

As shown in FIGS. 6 to 8, a semiconductor chip 31 is mounted on the lower surface side of the inner leads 32, 33 so as to straddle the inner leads 32, 33, and the semiconductor chip 31 and the inner leads 32, 33 are mounted. 33 has an LOC structure electrically connected to the upper surface of the inner lead 3.
The inner leads 32, 33 are laminated on the lower surfaces of the inner leads 32, 33 via an insulating layer 34 so as to be interposed between the semiconductor chips 31 mounted on the lower surfaces of the inner leads 2, 33. A plurality of extending pieces 35a, 35 extending
There is a frame provided with a frame-shaped laminated frame 35 having a b (Japanese Patent Laid-Open No. 7-94658). This is because a plurality of extension pieces 35a, 35b extending between the inner leads 32, 33 are provided.
And the inner lead has a multilayer structure.
In the drawing, reference numeral 32a denotes an inner lead on the extension piece 35b side.
However, the laminated frame 35 and the extension pieces 35a and 35b are not located on all the upper and lower surfaces of the other inner leads.
Therefore, the transfer of external noise to the signal line cannot be effectively prevented.

As described above, the structure of the conventional semiconductor package has a structure in which another inner lead is superimposed on the inner lead. However, since the structure is partial, the transfer of external noise to the signal line is effective. Can not be prevented.

[0008]

However, in recent years,
With the increase in the processing speed of CPUs and MPUs, it has become important to increase the speed of memories such as DRAMs. Some personal computers for personal use are equipped with a CPU capable of operating at a high speed of 100 MHz or more. For this reason, the structure technology of the semiconductor package that completely prevents the transfer of external noise to the signal line is very important.

The use of the conductive layer of the lead frame as a ground layer is an effective means for preventing electromagnetic interference between adjacent leads and obtaining good high-frequency signal transmission characteristics. From this point of view, the use of multiple layers of leads has been studied for the purpose of using the lead frame as a ground layer (Japanese Patent Application Laid-Open No. 7-249724).

[0010] As shown in FIG. 9, the inner lead of the lead 42 and the internal circuit of the package 41 are
Outer lead and signal pad 48 of external circuit board 45
And a lead frame in which at least a part of the surface of the lead 42 is covered with a dielectric layer 43 and the surface of the dielectric layer 43 is further covered with a conductive layer 44. The conductive layer 44 is connected to a ground pad 46 provided on the external circuit board 45.
Is provided with a thermal via 47 underneath. That is, the tip of the outer lead is connected to the signal pad 48 of the external circuit board 45 by the solder 49,
2 is connected to an external circuit board 45.
Is connected to a ground pad 46 provided on the substrate by solder 49. Therefore, each lead of the lead frame can be used as a ground layer, and it is not necessary to provide a ground connection lead, and the number of pins of the lead frame can be reduced.

However, in the structure of the conventional semiconductor package shown in FIG. 9 in which the leads are multilayered, consideration is given to efficiently and completely removing the influence of external noise due to the above-mentioned increase in the speed of the signal line. Did not. That is,
Since the structure around the leads is covered with a conductive layer via a dielectric layer, a dedicated conductive layer must be provided for each lead, or a power supply lead must be separately provided.

Accordingly, an object of the present invention is to solve the above-mentioned problems and to provide a response speed to a high-speed CPU processing speed.
An object of the present invention is to provide a semiconductor package structure which can completely remove external noise at a high speed of 00 MHz or more and has excellent high-speed transmission characteristics.

[0013]

In order to achieve the above object, a semiconductor package structure according to the present invention comprises a semiconductor package in which a lead frame is located on a semiconductor chip. It consists of a lead, a power supply metal layer and a ground metal layer, with a power supply metal layer on one side and a ground metal layer on the other side with a group of leads interposed. The power supply metal layer and the ground metal layer are provided in such a size as to cover almost all of the leads when viewed in the arrangement direction of the group of leads (claim 1).

On one side of the group of leads is a power supply metal layer,
Since the ground metal layer is disposed on the other side, electromagnetic interference between approaching leads is prevented. In addition, since the three-layer structure is formed to have a size that covers almost all of the leads in the arrangement direction of the group of leads, external noise can be completely removed.
Accordingly, a lead frame structure suitable for a high-speed memory module or the like can be obtained.

Further, in the semiconductor package structure according to claim 1, the semiconductor chip is a dynamic RAM.
In the case of (Random Access Memory) (claim 2), a highly integrated multi-bit DRAM excellent in high-speed transmission characteristics can be obtained.

Specifically, in the semiconductor package structure according to the first aspect, the power supply metal layer and the ground metal layer may be made of copper metal foil.

Further, in the semiconductor package structure according to the first aspect, the power supply metal layer, a group of leads and the ground metal layer constituting the three-layer lead frame are fixed to each other by an adhesive layer, and the adhesive layer is used. It is fixed to a semiconductor chip (claim 4). The adhesive is preferably a heat-resistant adhesive.

However, in the semiconductor package structure according to the first aspect, the power supply metal layer, a group of leads and the ground metal layer constituting the three-layer lead frame are fixed to each other by a tape having an adhesive layer on both surfaces. Alternatively, the semiconductor chip can be fixed to the semiconductor chip with a tape having an adhesive layer on both sides (claim 5).

The power supply metal layer and the ground metal layer may be either upper or lower, but the upper power supply metal layer has less influence on the semiconductor chip, and good electrical characteristics can be obtained.

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a highly integrated multi-bit DRAM.
1 shows a part of a semiconductor package having a LOC structure applied to the present invention, particularly a part of a lead frame. FIG. 2 is a cross-sectional view of a lead frame portion of the semiconductor package. FIG. 3 is a sectional view of the completed semiconductor package of the high-speed DRAM.

As shown in FIG. 1, the semiconductor package comprises:
The lead frame 1 is provided on a semiconductor chip 10. The lead frame 1 includes three layers of a group of leads 2, a ground metal layer 3, and a power supply metal layer 4. A group of leads 2
Is composed of a power supply lead 2b at the innermost position, a ground lead 2a at the front of the power source lead 2a, and a signal lead 2c at the other end.

A group of leads 2 is composed of one semiconductor chip 1
One group is provided on the left and right with respect to 0. Both groups of the leads 2 are arranged so as to face each other on both sides of a group of connection pads 11, which are groups of external connection electrodes for signal, power and ground, which are linearly arranged on the outer surface of the semiconductor chip 10. Has been established. The arrangement direction is parallel to the arrangement direction of the connection pads 11.

In the lead frame 1, a power supply metal layer 4 is disposed on one of the upper and lower sides of the group of leads 2 and a ground metal layer 3 is disposed on the other side. I have. In this embodiment, the power supply metal layer 4 is arranged above the group of leads 2, and the ground metal layer 3 is arranged below the group of leads 2. The reason is that, when viewed from the semiconductor chip 10 side, the semiconductor chip 10, the ground metal layer 3,
The semiconductor chip 10 and the power supply metal layer 4 are stacked, and the ground metal layer 3 is interposed between the semiconductor chip 10 and the group of leads 2.
This is because the electrical characteristics are better than when the power supply metal layer 4 is interposed between the group of leads 2.

Both the power supply metal layer 4 and the ground metal layer 3 are made of copper metal foil. The metal foils of the power supply metal layer 4 and the ground metal layer 3 are provided in such a size as to cover almost the entire surface of all the leads 2 in the arrangement direction of the group of leads 2. That is, the ground metal layer 3
Are arranged on the entire lower surface side of the group of leads 2 in a size that covers substantially the entire area of the inner leads of each lead 2, and the metal foil of the power supply metal layer 4 is It covers almost the entire area of the inner lead,
It is arranged on the entire upper surface side of the group of leads 2. Therefore, two groups of leads 2 belonging to one semiconductor chip 10
Is covered from the front and back by a common power supply metal layer 4 and a ground metal layer 3 until all the leads 2 of each group slightly leave the front end and the rear end of the inner lead. Will be FIG. 1 shows a state in which a group of leads 2 is covered from the front and back by a power supply metal layer 4 and a ground metal layer 3 made of one piece of copper foil.

A power supply metal layer 4, a group of leads 2 and a ground metal layer 3 constituting each of the multilayer lead frames 1.
Are fixed to each other by an adhesive layer, and are fixed on the semiconductor chip 10 by an adhesive. Here, the ground metal layer 3 is fixed on the semiconductor chip 10 with a heat-resistant adhesive 5, the group of leads 2 is fixed on the ground metal layer 3 with a heat-resistant adhesive 6, and The power supply metal layer 4 was fixed on the group of leads 2 with a heat-resistant adhesive 7. The connection was made by a bonding wire 8.

In this case, the lead frame 1 includes a group of leads 2, a ground metal layer 3 and a power supply metal layer 4 which are slightly displaced in the longitudinal direction, that is, in the direction orthogonal to the direction in which the leads 2 are arranged. Lead connection pad 11
It is arranged so that the step-like connecting step 12 remains on the side. The step-like internal connection step 12 is formed so as to extend longer toward the outer surface of the semiconductor chip 10.

In this embodiment, the connection pads 11 of the ground metal layer 3 and the power supply metal layer 4 are connected to the leads 2.
Are cut in a wavy manner in accordance with the arrangement pitch of the leads 2 so that the notches 13 are located in the gaps between the leads 2. This is to facilitate the work of wire bonding for connecting the group of leads 2, the ground metal layer 3, and the power metal layer 4 to the connection pad 11.

Thereafter, as shown in FIG. 2, the leads 2 and the connection pads 11 provided on the semiconductor chip 10 are connected to the semiconductor chip 10 by bonding wires 8. This is to connect the group of leads 2, the ground metal layer 3, and the power metal layer 4 to the corresponding connection pads 11 by bonding wires 8 using the stepped internal connection step 12. Do with.

The ground lead 2a and the ground metal layer 3 are connected by a bonding wire 83, and the power lead 2b and the power metal layer 4 are connected by a bonding wire 84.
Connect with As a result, the ground metal layer 3 has the ground potential, and the power metal layer 4 has the power potential.

Further, as shown in FIG.
Then, the semiconductor package 14 was obtained.

The dynamic RA obtained as described above
The M package realized a high-speed response of 100 MHz or more. That is, since the power supply metal layer 4 and the ground metal layer 3 are located above and below all the signal leads 2c, the transfer of external noise to the signal lines can be completely eliminated.

In the above embodiment, in consideration of the influence on the chip, the power supply metal layer and the ground metal layer are arranged above and below a group of leads with the power supply metal layer on the upper side.
It is also possible to dispose them on a group of leads with the ground metal layer facing upward.

Further, an adhesive is used for bonding between the leads or between the leads and the semiconductor chip.
A double-sided adhesive tape used for a package having an OC structure can also be used.

[0035]

As described above, according to the present invention, the following excellent effects can be obtained.

According to the first aspect of the present invention, the power supply metal layer is disposed on one side of the group of leads, and the ground metal layer is disposed on the other side. Interference is prevented. In addition, since the three-layer structure is formed to have a size that covers almost all of the leads in the arrangement direction of the group of leads, external noise can be completely removed. Therefore, a lead frame structure excellent in high-speed transmission characteristics suitable for a high-speed memory module or the like is obtained.

Further, since it is not necessary to provide a dedicated conductive layer for each lead or to separately provide a power supply metal layer, it is possible to efficiently and completely eliminate the influence of external noise accompanying the speeding up of the signal line. it can.

According to the second aspect of the present invention, the semiconductor chip is a dynamic RAM, so that a highly integrated multi-bit DRAM excellent in high-speed transmission characteristics can be obtained.

According to the invention described in claim 3, according to claim 1
Since the power supply metal layer and the ground metal layer described above are made of copper metal foil, they can be manufactured easily and at low cost.

According to the invention described in claim 4, according to claim 1 of the present invention,
The power supply metal layer constituting the three-layer lead frame according to the above,
Since the group of leads and the ground metal layer are fixed to each other by the adhesive layer and fixed to the semiconductor chip by the adhesive, a multilayer structure can be easily formed.

According to the invention set forth in claim 5, according to claim 1,
The power supply metal layer constituting the three-layer lead frame according to the above,
A group of leads and a ground metal layer are fixed to each other by a tape having an adhesive layer on both sides, and are fixed to a semiconductor chip by a tape having an adhesive layer on both sides, so that these multilayer structures can be easily created. .

[Brief description of the drawings]

FIG. 1 is a perspective view showing a lead frame portion of a semiconductor package of the present invention.

FIG. 2 is a sectional view of a semiconductor chip of the present invention and a lead frame portion.

FIG. 3 is a sectional view of the semiconductor package of the present invention after molding.

FIG. 4 is a plan view showing a structure of a conventional semiconductor package.

FIG. 5 is a sectional view of the semiconductor package of FIG. 4;

FIG. 6 is a plan view showing another lead frame structure of a conventional semiconductor package.

FIG. 7 is a partial sectional view of a lead frame of the semiconductor package of FIG. 6;

FIG. 8 is an enlarged plan view of a lead frame part of FIG. 7;

FIG. 9 is a sectional view showing still another structure of a conventional semiconductor package.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 lead frame 2 group of leads 2a ground lead 2b power lead 2c signal lead 3 ground metal layer 4 power metal layer 5,6,7 adhesive 8 bonding wire 9 molding resin 10 semiconductor chip 11 connection pad 12 inside Connection step 13 Notch 83 Bonding wire 84 Bonding wire

 ──────────────────────────────────────────────────の Continued on the front page (72) Inventor Ryuji Yonemoto 3550 Kida Yomachi, Tsuchiura City, Ibaraki Prefecture Within Hitachi Cable System Materials Research Laboratories (72) Inventor Osamu Yoshioka 3550 Kida Yomachi, Tsuchiura City, Ibaraki Hitachi Cable (72) Inventor: Moto Murakami 3-1, 1-1 Sukekawacho, Hitachi City, Ibaraki Pref. Hitachi Cable Co., Ltd.

Claims (5)

[Claims] In a semiconductor package in which a lead frame is located on a semiconductor chip, the lead frame on the semiconductor chip is composed of a group of leads, a power supply metal layer, and a ground metal layer. The power supply metal layer is arranged on one side and the ground metal layer is arranged on the other side, and these power supply metal layer and ground metal layer are viewed in the arrangement direction of the group of leads. A semiconductor package structure provided so as to cover almost all of the leads. 2. The semiconductor package structure according to claim 1, wherein said semiconductor chip is a dynamic RAM. 3. The semiconductor package structure according to claim 1, wherein said power supply metal layer and ground metal layer are made of copper metal foil. 4. The semiconductor package structure according to claim 1, wherein the power supply metal layer, a group of leads and the ground metal layer constituting the three-layer lead frame are fixed to each other by an adhesive layer. And a semiconductor package structure fixed to the semiconductor chip with an adhesive. 5. The semiconductor package structure according to claim 1, wherein the power supply metal layer, the group of leads and the ground metal layer constituting the three-layer lead frame have adhesive layers on both surfaces. A semiconductor package structure, wherein the semiconductor package structure is fixed to each other by a tape having an adhesive layer on both sides thereof.