JPH1140545A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control a side wall inclination angle of a hole with no effect on such other factors as affects etching characteristics, by providing cooling gas on the other surface of a substrate when an insulating film formed on one surface of the substrate is etched to form the hole. SOLUTION: Relating to a leaf type narrow gap type RIE device, a substrate wafer is cooled down with a wafer rear-surface (the side opposite to that where wiring is formed) cooling gas which uses He during etching. Relating to a cooling mechanism of wafer, a lower part electrode 304 is provided with two systems, wafer rear-side cooling gasses 302 and 303, which separately control a center and an edge of the wafer 311. The lower part electrode 304, using a lower part electrode cooling medium 301 for temperature control of itself, lets fluorine group medium, etc., circulate for cooling the lower part electrode 304. Since the cooling gasses 302 and 303 are provided under a specified gas pressure on the rearside of the substrate wafer 311, a gap for releasing gas is generated between the wafer 311 and the lower part electrode 304.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device. In particular, the present invention relates to a method for manufacturing a semiconductor device in which an etching process for forming a hole in an insulating film is improved in manufacturing a semiconductor device. INDUSTRIAL APPLICABILITY The present invention can be generally used in the manufacture of various semiconductor devices having a step of forming a hole in an insulating film, and is used, for example, when forming a via hole for making a connection between multilayer wirings. Can be.

[0002]

2. Description of the Related Art In the field of semiconductor devices in recent years, as the integration and performance of semiconductor devices have increased as seen in, for example, VLSIs, the proportion of wiring portions on device chips has increased. There is a tendency. As means for preventing a large increase in chip area for this purpose, multilayer wiring has become an essential technology.

In a multilayer wiring structure, a via hole is formed as a connection hole in order to establish a connection between wiring layers.
Here, a wiring plug is formed, and connection is made. A typical method for forming a wiring plug is shown in FIG.
13 to FIG.

[0004] The structure shown in FIG.
A metal wiring 102 is formed on a base layer 01 (underlying interlayer film or lower wiring), and an interlayer insulating film 104 is formed thereon with an antireflection film 103 interposed therebetween. A hole is formed in the interlayer insulating film 104 to form a via hole for connecting the upper and lower wirings. That is, a photoresist 105 is formed by patterning, and using this as a mask, the insulating film 104 is etched to form holes as shown in FIG. Next, as shown in FIG. 12, a wiring plug material 10 such as polysilicon or blanket tungsten is used.
13 is formed on the entire surface of the substrate while also burying it in the via hole, and then, for example, the entire surface is etched back to leave the wiring plug material 107 only in the via hole.
The wiring plug structure shown in FIG.

It is the shape of the via hole that determines the buried state of the wiring plug. If a good inclination (taper) is not formed on the side wall of the formed hole, a poor connection between wirings due to insufficient step coverage of the wiring plug material 107 becomes a serious problem. Therefore, the quality of the wiring plug depends on the shape of the via hole, particularly the inclination angle of the side wall.

Heretofore, finding a condition for forming a favorable inclination angle on the side wall of the via hole has required a great deal of time and cost (particularly, material cost). This is because the inclination angle can be controlled by the atmospheric pressure and the gas flow rate at the time of forming the hole. However, when these pressures and the gas flow rate are changed, other conditions, in particular, in-plane uniformity of the etching rate (hereinafter simply referred to as “uniformity”). The property may be abbreviated as “abbreviation”), so that the experiment had to be repeated many times in order to find the optimum conditions of the pressure and the gas flow rate while maintaining good uniformity.

[0007] This problem is particularly serious in an apparatus in which other conditions such as uniformity are likely to change due to changes in pressure and gas flow rate. For example, a parallel plate type reactive ion etching apparatus having a narrow electrode gap, for example, a so-called narrow electrode (narrow gap) having an electrode gap of 12 mm or less.
In the type ion etching apparatus, since the distance between the electrodes is narrow, if the pressure or the gas flow rate is changed, the density or distribution of the plasma changes, and the in-plane uniformity of the etching rate greatly changes. In such a narrow gap ion etching apparatus, it is technically difficult to adjust the inclination angle of the side wall of the hole to be formed while maintaining good uniformity.
Inevitably, it is necessary to repeat the experiment several times to find the optimum condition.

As is remarkable in the above-mentioned narrow gap type ion etching apparatus, it is difficult to adjust the side wall inclination angle of the hole to be formed at the same time with good uniformity. This is because the uniformity easily changes with pressure. In a narrow gap ion etching system, plasma is confined and uniform and high-speed etching is performed.However, when the pressure is changed, the density and distribution of the confined plasma change, so that even if the electrode spacing is not changed, the density is uniform and high. As a result, it is impossible to form a suitable plasma, which leads to a decrease in etch rate and a deterioration in uniformity. Also, when the pressure is increased while keeping the gas flow rate constant, the resident time of the gas becomes longer, and the reaction products such as CFx and CO deposit on the semiconductor wafer or the like as the material to be etched. Adverse effects, such as non-uniform etching due to dissociation or re-dissociation in plasma.

As described above, when adjusting the side wall inclination angle of the hole, a desirable condition cannot be obtained only by changing the pressure alone. As described above, according to the conventional method of obtaining the conditions by changing the pressure and the gas flow rate, when determining the conditions at the time of forming a hole, for example, a via hole, the pressure, the electrode interval, and the gas flow rate are all taken into consideration. The uniformity and side wall inclination angle of the hole must be matched at the same time, which requires a lot of time, cost and experience.

[0010]

As described above, in the conventional semiconductor device manufacturing technology having the hole forming step, in order to obtain the optimum condition by adjusting the side wall inclination angle of the hole,
It took a lot of time and cost. The present invention solves such a problem of the prior art, and when setting conditions for forming a hole, it is possible to control only the required side wall inclination angle, and to minimize the influence on other factors. It is another object of the present invention to provide a method of manufacturing a semiconductor device in which holes can be easily and appropriately formed, and a good connection wiring structure can be obtained.

[0011]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention has at least a step of forming a hole in an insulating film formed on one surface of a substrate by etching. In the method of manufacturing a device, a cooling gas is applied to the other surface of the substrate when the insulating film is etched to form a hole.

According to the present invention, the shape of the hole to be formed can be controlled by controlling the gas pressure at which the cooling gas is applied to the substrate surface. This does not affect other factors that may affect the etching characteristics,
Therefore, the sidewall inclination angle of the hole can be controlled without deteriorating other etching characteristics.

For example, the cooling gas is formed so as to be applied to the substrate so that the temperature of the entire substrate can be uniformly controlled or the temperature can be selectively controlled at a portion of the substrate at which attention is paid. The inclination angle of the side wall of the hole can be controlled. Further, the cooling gas is supplied to at least two places of the substrate, for example, at least two places of the center and the edge of the substrate in two systems, and the pressure of the supplied cooling gas can be controlled independently at each given place. Thus, by independent control at the point of interest, it is possible to control only the side wall inclination angle of the hole.

Further, the substrate is supported by a monopolar electrostatic chuck, and the substrate supporting electrodes of the monopolar electrostatic chuck are cooled during etching so as to cool the entire wafer substrate and pay attention. By controlling the temperature of the portion as described above, the shape of the hole can be controlled.

As an etching gas at the time of etching, a gas containing at least F atoms, Ar, N ₂
And a mixed gas of the above. In addition,
Etching gas is used under conditions such as the material of the material to be etched.
Of course, it should be appropriately selected.

According to the present invention, a parallel plate type reactive ion etching apparatus having an electrode interval of 12 mm or less, that is, a so-called narrow gap type ion etching apparatus is used as an etching apparatus. Since it is not necessary to determine the conditions, it can be used easily and as an appropriate hole forming technique.

The present invention can be used for forming various types of holes such as contact holes, via holes, and other connection holes formed in an insulating film.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be specifically described below with reference to the drawings. However, needless to say, the present invention is not limited by the following embodiments.

Embodiment 1 This embodiment, which will be described below, is a wafer-by-wafer type etching method for forming a via hole in an insulating film for a multilayer wiring structure when manufacturing a fine and integrated semiconductor device. The present invention is embodied when a narrow gap type RIE apparatus (especially an etching apparatus having a structure shown in FIG. 1) is used. In this embodiment, during etching, He
The substrate wafer is cooled by the cooling gas of the back surface of the wafer (the surface opposite to the wiring forming surface) using the cooling gas. Further, CHF ₃ and CF ₄ are mainly used as the etching gas, and the pressure of the cooling gas on the back surface of the wafer is applied to the center and the edge of the substrate, and each is controlled independently. In this example, since the cooling gas enters the chamber after cooling the back surface of the wafer, a gas (for example, N ₂ ) which affects the etching in the system to be used cannot be used, but is an inert gas which does not affect the etching. Any gas can be used as a cooling gas, for example, Ar or the like.
However, it is also possible to adopt a configuration in which the cooling gas does not affect the chamber in the closed system, in which case, various cooling gases can be used as appropriate.

In this embodiment, as a result of applying the present invention, the sidewall inclination angle of the via hole can be controlled only by the cooling gas pressure on the back surface of the wafer without deteriorating other etching characteristics (for example, uniformity). . This is because the formation of the deposited film is controlled by the degree of cooling as described below, and thereby the inclination angle of the side wall of the hole can be controlled. A desired control can be realized by appropriately increasing the cooling gas pressure to increase the cooling efficiency and lowering the temperature of the substrate or the target substrate portion, or conversely, lowering the cooling gas pressure to lower the cooling efficiency.

The operation of controlling the inclination angle of the side wall of the via hole will be described below with reference to FIGS. In each of the drawings, reference numeral 104 denotes an interlayer insulating film in which a via hole is to be opened, for example, an oxide film. Reference numeral 105 denotes a patterned photoresist used as a mask for forming a via hole.

Specifically, the control of the side wall inclination angle changes the cooling capability by controlling the cooling gas pressure on the back surface of the wafer to change the temperature of the wafer substrate. As a result, the amount of the reaction product deposited on the side wall changes, and the inclination angle of the side wall can be controlled.

For example, when an oxide film is etched using CHF ₃ and CF ₄ , a fluorocarbon-based substance (CFx) is deposited as a reaction product. FIG. 2 shows a state at the initial stage of etching. 2 to 4, F radical (or F ion) particles exhibiting an etching action are schematically indicated by reference numeral 202, and reaction products are schematically indicated by reference numeral 203.
, And the deposited film is schematically indicated by reference numeral 201. In the first place, CF ₄ is dissociated into CF, CF ₂ , CF ₃ , and F in plasma, but in fact, CFx radicals and F radicals repeat dissociation and recombination to reach a steady state. Since H of CHF ₃ reacts with F radicals there,
The amount of F radicals for recombining with CFx radicals is reduced. As a result, CF becomes CF ₂ and CF ₂ becomes CF
_Third , CF ₃ cannot return to CF ₄ and CF and CF ₂ increase as compared to the steady state.

Since these CF and CF ₂ have only one or two fluorine atoms bonded to a carbon atom having a valence of 4, two or more unpaired electrons survive and react with each other to polymerize. To form a fluorocarbon film. The deposition rate of the fluorocarbon film increases as the substrate temperature of the wafer decreases. This phenomenon has also been confirmed by plasma CVD and the like, and is presumed to be due to an increase in the amount of active species adsorbed on the surface of the substrate (side surface). Since this fluorocarbon film cannot be completely decomposed during etching and remains on the side wall, the area of the bottom of the hole is reduced by the deposited film 201 as shown in FIG. 3 (showing the state during etching). Finally, the shape becomes as shown in FIG.

Therefore, when controlling only the side wall inclination angle, it is possible to control only the side wall inclination angle by changing the deposition rate of the fluorocarbon film. Since the deposition rate varies depending on the substrate temperature, it is possible to control only the side wall inclination angle by changing the substrate temperature for the wafer to be etched. The substrate temperature can be changed by the temperature of the lower electrode supporting the substrate and the cooling gas on the back surface of the wafer. However, since the temperature of the lower electrode is generally controlled by a chiller or the like outside the apparatus, it takes time to change the temperature. Take it. On the other hand, since the cooling pressure of the wafer cooling gas can be set by a parameter, it can be changed immediately.

Hereinafter, the present embodiment will be specifically described with reference to the drawings. First, the narrow-gap RI of each leaf type, which is the etching apparatus used in the present embodiment.
The E device will be described with reference to FIG.

This device uses an upper electrode 3
A high-density plasma is formed by applying a 380 MHz RF bias to the lower electrode 05 and the lower electrode 304 (forming a susceptor for supporting the wafer). Reference numeral 310 denotes an arrow indicating the introduction of a process gas, and reference numerals 308 and 309 denote first and first arrows, respectively.
3 shows a second gas diffusion plate. During etching,
When the lower electrode 304 is moved up and down (indicated by an arrow 312 to indicate vertical driving), the distance between the upper and lower electrodes 305 and 304 is set to tens of mm, and the plasma is sealed by the quartz rings 306 and 307. Substrate wafer 311 being etched (eg, 8-inch wafer)
Are fixed on the lower electrode 304 by a monopolar electrostatic chuck. The wafer cooling mechanism includes two systems of a wafer backside cooling gas 302 and 303 on the lower electrode 304, which independently control the center and the edge of the wafer 311 respectively. The lower electrode 304 uses a lower electrode cooling refrigerant pipe 301 for its own temperature control,
The lower electrode 304 is cooled by circulating a refrigerant (for example, a fluorine-based refrigerant commercially available as Florinert). During etching, the substrate wafer 311
Is electrostatically attracted and supported on the lower electrode 304, so that the substrate wafer 311 almost adheres to the lower electrode 304,
The cooling gas 302, 303 is applied to the back surface of the substrate wafer 311 at a set gas pressure, so that it does not clearly appear in the drawing, but a small amount of gas that escapes between the substrate wafer 311 and the lower electrode 304. There is a gap.

In this embodiment, the present invention is applied to formation of a via hole. The sample used here has the structure shown in FIG. Base 10 formed on one surface of the substrate
1 (underlying interlayer film or lower wiring), metal wiring 1
As 02, an aluminum-based material wiring, particularly an Al—Cu alloy (for example, an Al-1 wt% Cu alloy) is formed, and a TiN film or the like is formed thereon as the anti-reflection film 103. After that, as the interlayer insulating film 104, SiO ₂ is formed to a thickness of 900 nm by, for example, a low pressure CVD method, and then the photoresist 105 is patterned into a 0.5 μm diameter using an i-line stepper. Thus, the structure shown in FIG. 10 is obtained. As a schematic process, the insulating film 104 is etched using the photoresist 105 as a mask, and a via hole is opened as shown in FIG. FIG. 11 shows a state in which the resist is removed after the opening of the via hole. Further, TiN / Ti (film thickness: 70 / 30n) is formed in the hole by, for example, a sputtering method.
m) is formed by a Ti collimated sputtering method or the like, and then, as shown in FIG. Form. And this wiring plug material 1
07 (blanket tungsten) is entirely etched back to leave the wiring plug material 107 only in the via hole, thereby obtaining a wiring plug structure schematically shown in FIG.

In this case, in this example, the sample of FIG.
The shape shown in FIG. 5A was obtained by etching under the following conditions. (Condition 1) Apparatus: Narrow gap type ion etching apparatus Gas: CHF ₃ / CF ₄ / Ar / N ₂ = 35/50/4
00/20 sccm Pressure: 160 Pa RF power: 1400 W Electrode spacing: 11 mm Lower electrode temperature: 0 ° C. He gas pressure for cooling the back surface of wafer: (center / edge) = 10 / 26.6 hPa

In this example, a hole structure in which the side wall inclination angle 401 of the via hole was 85 ° and the diameter of the bottom of the via hole was 0.30 μm was obtained by this etching. The in-plane uniformity of the etch rate of the insulating film 104 (oxide film) was ± 8%. Thereafter, according to the above-described procedure, TiN / Ti (film thickness: 70
/ 30 nm), and a wiring plug material 107 made of blanket tungsten having a thickness of 600 nm was formed by blanket tungsten, and the entire surface was etched back to form wiring plugs.
As shown in FIG. 7, according to the present embodiment, good wiring plug formation was realized. As described above, according to this example, by applying the present invention, the sidewall inclination angle can be controlled by solely controlling only the cooling gas pressure applied to the back surface of the substrate wafer, and thus, the sidewall inclination angle can be reduced at a low cost and in a short time. Can be adjusted. In addition, it becomes possible to form a good wiring plug.

In this embodiment, the diameter of the bottom of the via hole is 0.30 μm, and the etching conversion difference is −0.2 μm.
It became. When the diameter of the bottom is small, the electric resistance per unit area is large, so that the electrical reliability tends to be reduced.Therefore, the inclination angle of the side wall at which a good wiring plug can be formed is maintained, and It can be said that it is desirable that the etching conversion difference be as small as possible.

Embodiment 2 In this embodiment, as in Embodiment 1, the present invention is applied to formation of a via hole. Other than the conditions specifically described below, for example, the configuration of the etching apparatus and the like to be used is the same as that of the first embodiment.

The sample used here is the first embodiment.
Similarly to the structure shown in FIG. An aluminum-based material wiring, in particular, an Al—Cu alloy is formed as a metal wiring 102 on a base 101 (a base interlayer film or a lower wiring) formed on one surface of the substrate. A film or the like is formed. Thereafter, the SiO ₂ for example under reduced pressure C as an interlayer insulating film 104
After being formed to a thickness of 900 nm by the VD method, the photoresist 105 is patterned into a 0.5 μm diameter using an i-line stepper. Thus, the structure shown in FIG. 10 is obtained. As a schematic process, the insulating film 104 is etched using the photoresist 105 as a mask, and a via hole is opened as shown in FIG. FIG. 11 shows a state in which the resist is removed after the opening of the via hole. Further, an adhesion layer 106 made of TiN / Ti (thickness: 70/30 nm) is formed in the hole by, for example, a sputtering method by a Ti collimated sputtering method or the like, and then, as shown in FIG. As a 107, this is applied to the entire surface of the substrate, and is buried in the via hole for 600 n.
It is formed with a thickness of m. Then, the wiring plug material 107 (blanket tungsten) is entirely etched back to leave the wiring plug material 107 only in the via hole, thereby obtaining a wiring plug structure schematically shown in FIG.

In this case, in this example, the sample of FIG.
The shape shown in FIG. 6A was obtained by etching under the following conditions. (Condition 2) Apparatus: Narrow gap type ion etching apparatus Gas: CHF ₃ / CF ₄ / Ar / N ₂ = 35/50/4
00/20 sccm Pressure: 160 Pa RF power: 1400 W Electrode spacing: 11 mm Lower electrode temperature: 0 ° C. He gas pressure for cooling the backside of wafer: (center / edge) = 6.7 / 17.3 hPa

In this example, a hole structure in which the side wall inclination angle 402 of the via hole was 87 ° and the diameter of the bottom of the via hole was 0.40 μm was obtained by this etching. In this example, the side wall inclination angle was closer to vertical than in the first embodiment, and the diameter of the bottom was 0.40 μm, which was larger than that in the first embodiment. The in-plane uniformity of the etching rate of the insulating film 104 (oxide film) was ± 7.5%. Then, according to the above-described procedure, TiN / Ti (film thickness: 70/30)
An adhesive layer 106 (Ti collimated sputtering method) composed of 600 nm and a wiring plug material 107 composed of blanket tungsten were formed to a thickness of 600 nm, and this was etched back to form a wiring plug, as shown in FIG. 6B. In addition, according to the present embodiment, it is possible to realize the formation of a wiring plug that can sufficiently guarantee good wiring reliability. Thus, according to this example, by applying the present invention, the sole control of only the cooling gas pressure applied to the back surface of the substrate wafer,
The side wall inclination angle can be controlled, so that the side wall inclination angle can be adjusted at low cost and in a short time. In addition, it becomes possible to form a good wiring plug.

Embodiment 3 In this embodiment, as in Embodiment 1, the present invention is applied to formation of a via hole. Other than the conditions specifically described below, for example, the configuration of the etching apparatus and the like to be used is the same as that of the first embodiment.

The sample used here is the first embodiment.
Similarly to the structure shown in FIG. An aluminum-based material wiring, in particular, an Al—Cu alloy is formed as a metal wiring 102 on a base 101 (a base interlayer film or a lower wiring) formed on one surface of the substrate. A film or the like is formed. Thereafter, the SiO ₂ for example under reduced pressure C as an interlayer insulating film 104
After being formed to a thickness of 900 nm by the VD method, the photoresist 105 is patterned into a 0.5 μm diameter using an i-line stepper. Thus, the structure shown in FIG. 10 is obtained. As a schematic process, the insulating film 104 is etched using the photoresist 105 as a mask, and a via hole is opened as shown in FIG. FIG. 11 shows a state in which the resist is removed after the opening of the via hole. Further, an adhesion layer 106 made of TiN / Ti (thickness: 70/30 nm) is formed in the hole by, for example, a sputtering method by a Ti collimated sputtering method or the like, and then, as shown in FIG. As a 107, this is applied to the entire surface of the substrate, and is buried in the via hole for 600 n.
It is formed with a thickness of m. Then, the wiring plug material 107 (blanket tungsten) is entirely etched back to leave the wiring plug material 107 only in the via hole, thereby obtaining a wiring plug structure schematically shown in FIG.

In this case, in this example, the sample of FIG.
The shape shown in FIG. 7A was obtained by etching under the following conditions. (Condition 3) Apparatus: Narrow gap type ion etching apparatus Gas: CHF ₃ / CF ₄ / Ar / N ₂ = 50/75/8
00/20 sccm Pressure: 70 Pa RF power: 1100 W Electrode interval: 10 mm Lower electrode temperature: 0 ° C. He gas pressure for cooling the back surface of wafer: (center / edge) = 10 / 26.6 hPa

In this embodiment, a hole structure in which the side wall inclination angle 501 of the via hole is 86 ° and the diameter of the bottom of the via hole is 0.38 μm is obtained by this etching. The in-plane uniformity of the etching rate of the insulating film 104 (oxide film) was ± 7.5%. Thereafter, TiN / Ti (film thickness:
An adhesive layer 106 (Ti collimated sputtering method) of 70/30 nm) and a wiring plug material 107 of blanket tungsten were formed to a thickness of 600 nm, and the entire surface was etched back to form a wiring plug.
As shown in (b), the present embodiment has realized the formation of a wiring plug that can sufficiently guarantee good wiring reliability. As described above, according to this example, by applying the present invention, the sidewall inclination angle can be controlled by solely controlling only the cooling gas pressure applied to the back surface of the substrate wafer, and thus, the sidewall inclination angle can be reduced at a low cost and in a short time. Can be adjusted. In addition, it becomes possible to form a good wiring plug.

Fourth Embodiment In this embodiment, as in the first embodiment, the present invention is applied to formation of a via hole. Other than the conditions specifically described below, for example, the configuration of the etching apparatus and the like to be used is the same as that of the first embodiment.

The sample used here is the first embodiment.
Similarly to the structure shown in FIG. An aluminum-based material wiring, in particular, an Al—Cu alloy is formed as a metal wiring 102 on a base 101 (a base interlayer film or a lower wiring) formed on one surface of the substrate. A film or the like is formed. Thereafter, the SiO ₂ for example under reduced pressure C as an interlayer insulating film 104
After being formed to a thickness of 900 nm by the VD method, the photoresist 105 is patterned into a 0.5 μm diameter using an i-line stepper. Thus, the structure shown in FIG. 10 is obtained. As a schematic process, the insulating film 104 is etched using the photoresist 105 as a mask, and a via hole is opened as shown in FIG. FIG. 11 shows a state in which the resist is removed after the opening of the via hole. Further, an adhesion layer 106 made of TiN / Ti (thickness: 70/30 nm) is formed in the hole by, for example, a sputtering method by a Ti collimated sputtering method or the like, and then, as shown in FIG. As a 107, this is applied to the entire surface of the substrate, and is buried in the via hole for 600 n.
It is formed with a thickness of m. Then, the wiring plug material 107 (blanket tungsten) is entirely etched back to leave the wiring plug material 107 only in the via hole, thereby obtaining a wiring plug structure schematically shown in FIG.

In this case, in this example, the sample of FIG.
By etching under the following conditions, the shape of FIG. 8A was obtained. (Condition 4) Apparatus: Narrow gap type ion etching apparatus Gas: CHF ₃ / CF ₄ / Ar / N ₂ = 50/75/8
00/20 sccm Pressure: 70 Pa RF power: 1100 W Electrode interval: 10 mm Lower electrode temperature: 0 ° C. He gas pressure for wafer back surface cooling: (center / edge) = 6.7 / 17.3 hPa

In this example, a hole structure in which the side wall inclination angle 502 of the via hole was 87 ° and the diameter of the bottom of the via hole was 0.40 μm was obtained by this etching. The in-plane uniformity of the etching rate of the insulating film 104 (oxide film) was ± 7%. Thereafter, according to the above-described procedure, TiN / Ti (film thickness: 70
/ 30 nm), and a wiring plug material 107 made of blanket tungsten was formed to a thickness of 600 nm, and the entire surface was etched back to form a wiring plug.
As shown in the above, the present embodiment has realized the formation of a wiring plug that can sufficiently guarantee good wiring reliability.
As described above, according to the present embodiment, by applying the present invention, the sidewall inclination angle can be controlled by the sole control of only the cooling gas pressure applied to the back surface of the substrate wafer, and therefore, the cost can be reduced.
It is possible to adjust the inclination angle of the side wall in a short time. In addition, it becomes possible to form a good wiring plug.

Embodiment 5 In this embodiment, as in Embodiment 1, the present invention is applied to formation of a via hole. Other than the conditions specifically described below, for example, the configuration of the etching apparatus and the like to be used is the same as that of the first embodiment.

The sample used here is the first embodiment.
Similarly to the structure shown in FIG. An aluminum-based material wiring, in particular, an Al—Cu alloy is formed as a metal wiring 102 on a base 101 (a base interlayer film or a lower wiring) formed on one surface of the substrate. A film or the like is formed. Thereafter, the SiO ₂ for example under reduced pressure C as an interlayer insulating film 104
After being formed to a thickness of 900 nm by the VD method, the photoresist 105 is patterned into a 0.5 μm diameter using an i-line stepper. Thus, the structure shown in FIG. 10 is obtained. As a schematic process, the insulating film 104 is etched using the photoresist 105 as a mask, and a via hole is opened as shown in FIG. FIG. 11 shows a state in which the resist is removed after the opening of the via hole. Further, an adhesion layer 106 made of TiN / Ti (thickness: 70/30 nm) is formed in the hole by, for example, a sputtering method by a Ti collimated sputtering method or the like, and then, as shown in FIG. As a 107, this is applied to the entire surface of the substrate, and is buried in the via hole for 600 n.
It is formed with a thickness of m. Then, the wiring plug material 107 (blanket tungsten) is entirely etched back to leave the wiring plug material 107 only in the via hole, thereby obtaining a wiring plug structure schematically shown in FIG.

In this case, in this example, the sample of FIG.
The shape shown in FIG. 9A was obtained by etching under the following conditions. (Condition 5) Apparatus: Narrow gap type ion etching apparatus Gas: CHF ₃ / CF ₄ / Ar / N ₂ = 50/75/8
00/20 sccm Pressure: 70 Pa RF power: 1100 W Electrode spacing: 10 mm Lower electrode temperature: 0 ° C. He gas pressure for cooling the back surface of wafer: (center / edge) = 6.7 / 13.3 hPa

In this example, a hole structure in which the side wall inclination angle 503 of the via hole was 88 ° and the diameter of the bottom of the via hole was 0.44 μm was obtained by this etching. The in-plane uniformity of the etching rate of the insulating film 104 (oxide film) was ± 7.5%. Thereafter, TiN / Ti (film thickness:
An adhesive layer 106 (Ti collimated sputtering method) made of 70/30 nm) and a wiring plug material 107 made of blanket tungsten were formed to a thickness of 600 nm, and the whole was etched back to form wiring plugs.
As shown in (b), the present embodiment has realized the formation of a wiring plug that can sufficiently guarantee good wiring reliability. As described above, according to this example, by applying the present invention, the sidewall inclination angle can be controlled by solely controlling only the cooling gas pressure applied to the back surface of the substrate wafer, and thus, the sidewall inclination angle can be reduced at a low cost and in a short time. Can be adjusted. In addition, it becomes possible to form a good wiring plug.

The above-described third to fifth embodiments are completely different from the first and second embodiments in terms of the gas ratio, pressure, power, and the like. As a result, the in-plane uniformity of the etch rate of the insulating film (oxide film) does not change much, and only the sidewall inclination angle changes. That is, from this, it can be said that the gas pressure on the back surface of the wafer is a parameter that can change only the sidewall inclination angle of the via hole while maintaining the in-plane uniformity of the oxide film etch rate under any etching conditions.

Although the present invention has been described with reference to the five specific embodiments, the present invention is not limited to the above specific embodiments as described above. Sample structure to be etched,
It goes without saying that the etching gas and other process conditions can be appropriately selected within the scope of the present invention.

[0050]

As described above, according to the method of manufacturing a semiconductor device according to the present invention, it is easy to determine the conditions for forming holes when manufacturing a semiconductor device having a hole forming step.
In addition, by making it possible to control only the side wall inclination angle required for forming a hole, it is possible to easily and properly form a hole such as a connection hole while minimizing other influences. A method for manufacturing a semiconductor device capable of obtaining a connection wiring structure can be provided.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing a chamber structure of an etching apparatus (narrow gap type RIE apparatus) used in an embodiment of the present invention.

FIG. 2 is an operation explanatory view of the embodiment of the present invention (1).

FIG. 3 is an operation explanatory view of the embodiment of the present invention (2).

FIG. 4 is an operation explanatory view of the embodiment of the present invention (3).

5A and 5B are cross-sectional views illustrating a wiring plug structure according to the first embodiment, where FIG. 5A illustrates a structure after hole etching;
(B) shows the structure after the etch back of the wiring plug material.

FIG. 6 is a cross-sectional view illustrating a wiring plug structure according to a second embodiment, in which (a) illustrates a structure after hole etching;
(B) shows the structure after the etch back of the wiring plug material.

FIG. 7 is a cross-sectional view illustrating a wiring plug structure according to a third embodiment, in which (a) illustrates a structure after hole etching;
(B) shows the structure after the etch back of the wiring plug material.

FIG. 8 is a cross-sectional view showing a wiring plug structure according to a fourth embodiment, in which (a) shows a structure after hole etching;
(B) shows the structure after the etch back of the wiring plug material.

FIG. 9 is a cross-sectional view showing a wiring plug structure according to a fifth embodiment, in which (a) shows a structure after hole etching;
(B) shows the structure after the etch back of the wiring plug material.

FIG. 10 is a sectional view showing a general step of forming a via hole (1).

FIG. 11 is a sectional view showing a general step of forming a via hole (2).

FIG. 12 is a sectional view showing a general step of forming a via hole (3).

FIG. 13 is a sectional view showing a general step of forming a via hole (4).

[Explanation of symbols]

101: Underlayer (underlying interlayer film or underlying wiring), 10
2 ... metal wiring, 103 ... antireflection film, 104
... Insulating film (interlayer insulating film for forming holes, SiO
₂ etc.), 105 ... photoresist, 106 ... adhesion layer, 107 ... wiring plug forming material, 201 ...
Deposited film, 202... F radical (F ion), 203
... Reaction product, 301 ... Refrigerant pipe for cooling the lower electrode, 302 ... Substrate (wafer) backside cooling gas (for substrate center), 303 ... Substrate (wafer) backside cooling gas (for substrate edge) ), 304 ... lower electrode (substrate support electrode), 305 ... upper electrode, 311 ... substrate (wafer), 401 ... sidewall inclination angle in the first embodiment, 402 ... implementation Sidewall inclination angle in Embodiment 2; 501: Sidewall inclination angle in Embodiment 3; 502: Sidewall inclination angle in Embodiment 4; 503: Sidewall inclination angle in Embodiment 4.

Claims (9)

[Claims] 1. A method of manufacturing a semiconductor device, comprising: at least a step of forming a hole in an insulating film formed on one surface of a substrate by etching, wherein the insulating film is etched to form a hole. A method for manufacturing a semiconductor device, characterized by providing a cooling gas to the other surface. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the shape of a hole to be formed is controlled by controlling a gas pressure when the cooling gas is supplied. 3. The semiconductor device according to claim 1, wherein the cooling gas is applied to at least two locations on the substrate, and the pressure of the applied cooling gas can be independently controlled at each applied location. Production method. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the cooling gas is supplied to at least two places of a center and an edge of the substrate in two systems. 5. The method according to claim 1, wherein the substrate being etched is supported by a monopolar electrostatic chuck. 6. The method of manufacturing a semiconductor device according to claim 3, wherein the substrate supporting electrode of the monopolar electrostatic chuck is cooled during etching. 7. The method according to claim 1, wherein a gas containing at least F atoms, Ar, and N ₂ are used as the etching gas when etching the holes.
13. The method for manufacturing a semiconductor device according to item 5. 8. The method according to claim 1, wherein the etching apparatus used for the etching is a parallel plate type reactive ion etching apparatus having an electrode interval of 12 mm or less. 9. The method according to claim 1, wherein the hole formed in the insulating film is a via hole for connecting two or more wiring layers formed on the substrate between the wiring layers.
13. The method for manufacturing a semiconductor device according to item 5.