JPH1139372A - Method and device for calculating wiring capacity, and storage medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To highly precisely calculate wiring capacity by using a symbolic layout wiring by calculating wiring capacity of a grid unit of a remarked wiring as segment capacity and cumulatively adding segment capacity. SOLUTION: A data processing part 20 creates a wiring state vector map in map memory 22, reads one piece of wiring data after another from wiring table memory 21, successively reads the wiring state vectors V of each wiring segment from the memory 22 and loads them to a register 23. Segment capacity Cs about each value of the vectors is calculated and stored in an address of wiring state vector/segment capacity table memory 24. In a cumulative adding part 25, an addition circuit 28 adds outputs of registers 26 and 26 and the result is held by the register 27. A data processing part 20 writes an output of the register 27 in each wiring in a field of capacity C of the memory 21.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for calculating a capacitance of a symbolic layout wiring and a storage medium storing a program for executing the method.

[0002]

2. Description of the Related Art In LSI design, the capacitance of a layout wiring is calculated in order to simulate whether conditions such as a hold time and a setup time are satisfied. As shown in FIG. 9A, when the capacitance of the wiring 10A is calculated in consideration of the wiring width, for example, the wirings 10A and 11A
Since it is necessary to determine the area of the overlapping portion with A, the area of the overlapping portion of the wirings 10A and 12A, and the like, the calculation time becomes too long when the circuit is a large-scale LSI.

In order to reduce the calculation time, as shown in FIG. 9B, symbolic layout wirings 10B to 12B whose wirings are represented by their center lines are used.
Paying attention to, the capacitance of a wiring segment in grid units is determined from the surrounding wiring state as a segment capacitance, and the wiring capacitance is determined by cumulatively adding the segment capacitance. In this case, the off-grid wiring is rounded off to the on-grid wiring collectively before calculating the wiring capacitance, regardless of the current wiring of interest.

[0004]

However, FIG. 10 (A)
As shown in the figure, when the target wiring 13 is off-grid and the wirings 14 and 15 on both sides thereof are on-grid, the target wiring 1
As shown in FIG. 10B, 3 is rounded to a wiring 13A on the grid on the side of the wiring 15, for example. For example, when considering only the wiring on the adjacent grid on the side of the target wiring in the capacitance calculation, the wiring 14 is ignored when the target wiring is the wiring 13A, and the wiring 13A is ignored when the target wiring is the wiring 14. You. For this reason, the accuracy of the calculated capacity deteriorates, and the reliability of the simulation result decreases.

SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a method and an apparatus for calculating a wiring capacitance capable of calculating a wiring capacitance with higher accuracy by using a symbolic layout wiring, and to implement this method. It is to provide a storage medium in which a program is stored.

[0006]

According to a first aspect of the present invention, in a wiring capacitance calculating method for calculating a capacitance of a symbolic layout wiring, when a target wiring to be calculated is an off-grid wiring, the target wiring and the target wiring are calculated. A first step of copying data relating to the surrounding wiring affecting the capacity calculation to the work storage area, and laying out the wiring of interest and surrounding wiring affecting the capacity calculation based on the copied data; A second step of rigidly displacing the grid to turn the wiring of interest into an on-grid wiring, a third step of rounding off grid wiring within a predetermined distance from the wiring of interest to an on-grid wiring, A fourth step of calculating a wiring capacity in grid units of the wiring of interest as a segment capacity, and cumulatively adding the segment capacitances to obtain the capacity of the wiring of interest. That.

According to this wiring capacitance calculating method, when the wiring of interest is an off-grid wiring, the first to first wirings are used for each wiring of interest.
Since four steps are performed, it is possible to calculate the wiring capacity using symbolic layout wiring with higher accuracy than the conventional method of rounding off-grid wiring to on-grid wiring for all wirings in the map storage area at once. It has the effect of being able to.

According to a second aspect of the present invention, in the first aspect, in the third step, off-grid wiring within a predetermined distance from an adjacent grid line parallel to the target wiring is set as wiring on the grid line. Round. According to a third aspect of the present invention, there is provided the wiring capacitance calculating method according to the first or second aspect, wherein
Before the process, when a wire having a length of a grid interval is set as a wiring segment, a code indicating the presence / absence state of a wiring segment around the target wiring segment is obtained as a wiring state vector of the target wiring segment. The corresponding segment capacity is stored in a memory using the wiring state vector as an address. In the fourth step, the wiring state vector is obtained for each wiring segment along the target wiring, and the obtained wiring state vector is obtained. The address of the memory is designated, and the segment capacity read from the memory is cumulatively added to obtain the capacity of the wiring of interest.

According to this wiring capacity calculation method, the capacity of the wiring of interest can be obtained by cumulatively adding the segment capacities read from the memory, so that the capacity calculation can be performed at a high speed. According to a fourth aspect of the present invention, in the wiring capacity calculating method for obtaining the capacity of a wiring of interest corresponding to data read from the symbolic layout wiring data stored in the wiring table storage area, when a wiring having a length of a grid interval is used as a wiring segment, A set of a code indicating a distance between a grid line passing through the target wiring segment and a grid line surrounding the grid line and a code indicating the presence / absence state of a wiring segment surrounding the target wiring segment is defined as the wiring of the target wiring segment. A first step of storing a segment capacity, which is a capacity of the wiring segment of interest corresponding to the wiring state vector, as a state vector in a memory using the wiring state vector as an address; A storage unit for storing the wiring state vector is stored for each of the matching grid points. For each of the wiring data stored in the wiring table storage area, when the wiring corresponding to the wiring data is set as the non-interest wiring, and the non-interest wiring is arranged along the grid, A wiring around the external wiring that affects the capacitance calculation is taken as a wiring of interest, and the effect of the wiring of interest outside on the wiring state vector as viewed from the wiring of interest is written to the storage unit corresponding to the wiring of interest. In a second step, wiring data is sequentially read from the wiring table storage area, and for each read wiring data, a wiring corresponding to the wiring data is set as a target wiring, and the map storage area is referred to along the target wiring. Reading the contents of the storage unit as a wiring state vector, addressing the memory with the read wiring state vector, and reading the segment capacity read from the memory. And a third step of obtaining a volume of the remarked wiring cumulatively added.

According to this wiring capacitance calculation method, by using grids with different grid intervals, it is possible to set on-grid wiring that is off-grid when the same grid interval is used. There is an effect that the wiring capacitance can be calculated with higher accuracy than when the wiring is rounded to the on-grid wiring.

According to a fifth aspect of the present invention, in the fourth aspect, when the target wiring corresponding to the wiring data read from the wiring table storage area in the third step is an off-grid wiring, Without performing the capacity acquisition processing in three steps, after the third step, the data relating to the wiring of interest and surrounding wirings that affect the calculation of the capacity are copied to a work storage area, and in the work storage area, Based on the copied data, lay out the wiring of interest and the surrounding wiring that affects the capacitance calculation, shift the grid rigidly to make the wiring of interest on-grid wiring, and move the wiring within a predetermined distance from the wiring of interest. The off-grid wiring is rounded to the on-grid wiring, the segment capacitance is calculated for each of the wiring segments along the target wiring, the segment capacitance is cumulatively added, and the capacity of the target wiring is calculated. The seek.

According to the storage medium of claim 6, the storage medium of claims 1 to 5
A program for executing the wiring capacitance calculation method according to any one of the above is stored. According to a seventh aspect of the present invention, in the wiring capacity calculating apparatus for determining the capacity of a wiring of interest corresponding to data read from the symbolic layout wiring data stored in the wiring table storage area, the wiring capacity calculating apparatus may be configured to correspond to each of grid points or adjacent grid points. A map storage unit in which a storage unit for storing a wiring state vector is secured, a register, and a wiring having a length of a grid interval is defined as a wiring segment, and an interval between a grid line passing through the wiring segment of interest and a surrounding grid line parallel thereto. And a code indicating
When a set of codes indicating the presence / absence state of a wiring segment around the target wiring segment is defined as a wiring state vector of the target wiring segment, a segment capacitance corresponding to the wiring state vector, which is a capacitance of the target wiring segment, is obtained. Paying attention to the wiring corresponding to the wiring data for each of the table storage unit in which the wiring state vector is stored as an address and addressed by the output of the register, and the wiring data stored in the wiring table storage area. When the external wiring is arranged along the grid as the external wiring, the wiring that affects the capacitance calculation around the external wiring is regarded as the external wiring, and the external wiring of the external wiring as viewed from the external wiring is regarded as the external wiring. The effect on the wiring state vector is written in the storage unit corresponding to the target wiring, and wiring data is sequentially read from the wiring table storage area. For each of the read wiring data, a wiring corresponding to the wiring data is set as a target wiring, and the contents of the storage unit are read as a wiring state vector along the target wiring with reference to the map storage area. A data processing unit for outputting the data to be stored in the register; and a cumulative addition unit for cumulatively adding the segment capacity read from the table storage unit to obtain the capacity of the wiring of interest.

According to an eighth aspect of the present invention, there is provided the wiring capacity calculating apparatus according to the seventh aspect, further comprising a work storage unit, wherein the data processing unit stores the target wiring corresponding to the wiring data read from the wiring table storage area. In the case of the off-grid wiring, the data relating to the wiring of interest and the surrounding wiring affecting the capacitance calculation is copied to the working storage area, and the wiring of interest is copied to the working storage area based on the copied data. The layout is laid out with surrounding wirings that affect the capacitance calculation, the grid is rigidly shifted to make the focused wiring an on-grid wiring, an off-grid wiring within a predetermined distance from the focused wiring is rounded to an on-grid wiring, The segment capacitance is calculated for each of the wiring segments along the wiring, and the segment capacitance is cumulatively added to obtain the capacitance of the wiring of interest.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a schematic configuration of a wiring capacity calculation device. The data processing unit 20 includes, for example, a microprocessor, a program storage memory, and a work memory 20.
a, and performs data processing mainly on the wiring table memory 21 and the map memory 22.

The wiring table memory 21 stores data of all wirings of each wiring layer obtained by layout design. The bent wiring is divided into linear wirings, and each of the divided wirings is connected in a list structure to indicate that it is one connected wiring.
Each wiring data (bent wiring is data of one straight wiring)
Includes the coordinates of the start and end of a straight line. Blank spaces for the capacitance C and the resistance R are provided corresponding to the respective wiring data. The resistance R of the wiring can be easily obtained by multiplying the wiring length by the resistance value per unit length. The signal propagation delay time (time constant) of each wiring is the product of the capacitance C and the resistance R.

In principle, the layout wiring has its center line on a grid line, and a wiring portion between adjacent grid points constituting one wiring is called a wiring segment. The data processing unit 20 controls the wiring table memory 2
1 based on all the wiring data in the map memory 22
A wiring state vector map, which will be described later, is created. Next, wiring data is read out one by one from the wiring table memory 21. For each wiring data, the wiring of each wiring segment along the wiring is read from the map memory 22. The state vectors V are sequentially read and loaded into the register 23.

The wiring state vector V will be described with reference to FIG. In FIG. 4A, the wiring segment direction of the wiring layer L1 and the wiring segment direction of the wiring layer L2 are perpendicular to each other, and the wiring segment direction of the wiring layer L2 and the wiring segment direction of the wiring layer L3 are perpendicular to each other. It has become. On one side and the other side of the target wiring segment SP in the wiring layer L2, wiring segments SL and SR are arranged at intervals of one grid. Each of the wiring segments L1 and L3 has a wiring segment S
D and SU are arranged, and the wiring segments SD and SU are located immediately below and directly above the target wiring segment SP, respectively.

The capacitance of the target wiring segment SP differs depending on the state of the surrounding wiring. In order to represent this wiring state, the presence / absence of the wiring of the wiring segments SL, SR, SD and SU is determined by the bits Lb and R as shown in FIG.
Expressed as b, Db and Ub. First code CD1 = (Lb,
Rb, Ub, Db) indicate the wiring state. As shown in FIG. 4C, the first code CD1 has 16 hexadecimal numbers 0 to F. In FIG. 4C, the capacitance Cs (segment capacitance) of the target wiring segment corresponding to each of them is Cs1.
〜CsF.

In FIG. 4, for simplicity, the wiring layers L1 and L
2, the interlayer contact between the wiring layers L2 and L3, the wiring segment S of interest in the wiring layer L1.
Consider a wiring segment that is at least two grid intervals away from P in the same wiring layer, a wiring segment next to the wiring segment SU in the wiring layer L3, a wiring segment above the wiring layer L3, and a wiring segment below the wiring layer L1. Not
These may also be added as components of the first code CD1.

In general, the grid interval is constant. For example, as shown in FIG. 7A, considering a grid including the interval d and the interval 1.5d in the X direction, if many wirings are on-grid, Using such a different pitch grid. Also in this case, the same first code CD1 as in the case of FIG. 4 is used. As a second code that affects the capacitance calculation, in FIG. 4A, when the wiring interval on both sides of the target wiring segment SP is d, one wiring interval of the target wiring segment SP is d and the other wiring interval is 1 .5d, and the wiring interval on both sides of the target wiring segment SP is 1.5
A code for distinguishing from the case of d is used. Other parameters affecting the capacity calculation may be added to the second code CD2.

The first code CD1 and the second code CD2 determine the wiring state surrounding the calculation of the capacitance of the wiring segment SP of interest. Therefore, the wiring state vector V
= (CD2, CD1). Wiring state vector V
, The segment capacitance Cs is obtained by calculation. In FIG. 1, the address AD of the wiring state vector / segment capacitance table
D) = (segment capacitance Cs) corresponding to (wiring state vector V) is stored. A data output terminal of the register 23 into which the wiring state vector V is loaded is connected to an address input terminal of the wiring state vector / segment capacity table memory 24. Is read out as the segment capacity.

In the accumulative adder 25, the read segment capacity is held in the register 26, and the output of the register 26 and the output of the register 27 are added by the adder circuit 28.
The result is held in the register 27. The output of the register 27 is written by the data processing unit 20 into the column of the capacity C in the wiring table memory 21 for each wiring. The data holding timing signals to the registers 26 and 27 are supplied from the data processing unit 20.

Next, the procedure of data processing by the data processing unit 20 will be described with reference to FIGS. It is assumed that the contents of the wiring state vector / segment capacity table memory 24 have already been obtained independently of this processing. (S1) The data processing unit 20 includes the wiring table memory 21
Map memory 22 based on each of all the wiring data in
A wiring state vector map is created as follows.

FIG. 5A schematically shows a partial configuration of a wiring state vector map corresponding to an arbitrary wiring layer in the wiring table memory 21 in relation to a grid indicated by a dotted line. A word R for storing a wiring state vector V corresponds to each space between adjacent grid points. FIG.
In (A), for the sake of simplicity, the first code CD1 = (Lb, Rb, Ub, D
The case represented by b) is shown. First, all the words R in the wiring table memory 21 are initialized to 0, for example.

One wiring data, for example, data of the wiring P0 in the wiring layer B is read out from the wiring table memory 21, and based on the coordinates, the wiring P0 is virtually stored in the map memory 22 as shown in FIG. Place Assuming that the target wiring exists on the grid line on the left side parallel to the wiring P0, the wiring P0 exists on the right side of the target wiring, so that each bit R of the words RB1 to RB3
b is set to '1'. In FIG. 5, bits of “1” are indicated by hatching. When it is assumed that the target wiring exists on the grid line on the right side parallel to the wiring P0, the wiring P0 exists on the left side of the target wiring, so that the words RB7 to RB
Each bit Lb of B9 is set to '1'. When it is assumed that there is a line of interest in a grid line corresponding to a position directly above the line P0 in the wiring layer A shown in FIG. 6A above the wiring layer B, the line P0 exists immediately below the line of interest. Therefore, the bit Db of each of the words RA4 to RB6 corresponding to the target wiring is set to “1”. Similarly, when it is assumed that there is a target line in a grid line corresponding to directly below the line P0 in the wiring layer C shown in FIG. 6B below the wiring layer B in FIG. Is located right above the word RC4 to the word RC4
Each bit Ub of RC6 is set to '1'.

If the wiring P0 is off-grid, the above processing is performed after rounding to on-grid. Also in this case, the wiring of interest is on-grid. By performing such processing for all wiring data in the wiring table memory 21, a wiring state vector map is created in the map memory 22 of FIG. (S2) The data processing unit 20 includes the wiring table memory 21
One data of the wiring of interest is extracted from. The retrieval order is
For example, it is determined in advance from the top of the table.

(S3) If there is no target wiring to be taken out in step S2, the process proceeds to step S12 in FIG. 3, and if there is, the process proceeds to the next step S4. (S4) This wiring of interest is stored in the map memory 22,
If it is off-grid, the process proceeds to step S5, and if it is on-grid, the process proceeds to step S6. (S5) The pointer of the off-grid wiring data on the wiring table is stored in the working memory 20a, and the process returns to step S2.

(S6) The contents of the register 27 are cleared to zero. (S7) The point of interest is advanced by one grid interval along the wiring of interest. However, for each wiring of interest, steps S7 to S7
At the first time of the loop processing of 10, the coordinates of one end of the wiring in the wiring table memory 21 are set as a point of interest. For example, in the case of FIG. 7B, the grid point G0 is set as the target point of the target wiring P1 at the first time, and the grid point G1 is set as the target point at the next time.

(S8) If a wiring segment exists from the point of interest to the next point of interest along the wiring P1 of interest, the flow proceeds to step S9, and if not, to step S11. In the case of FIG. 7B, if the point of interest is the grid point G3, the process proceeds to step S11. (S9) The wiring state vector V of the target wiring segment from the target point to the next target point along the target wiring P1 is read from the map memory 22 and loaded into the register 23.

(S10) The segment capacity Cs read from the wiring state vector / segment capacity table memory 24 is stored in the register 26, and the addition result of the adding circuit 28 is stored in the register 27. Next, the process returns to step S7. (S11) The contents of the register 27 are written as the capacity of the wiring of interest into the capacity C of the wiring column extracted in step S2 in the wiring table memory 21. Next, the process returns to step S2.

(S12) One pointer of the off-grid wiring data stored in step S5 is taken out as a pointer of the data of the wiring of interest. If there is no pointer of the off-grid wiring data to be taken out, the process is ended, and if there is, the process proceeds to the next step S13. (S13) The target wiring is set to the on-grid wiring, and the wiring within a predetermined distance on the side, for example, within 1.5d, is rounded to the on-grid wiring. Since this processing is performed for each wiring of interest, the data of the wiring of interest in the wiring table memory 21 and the data of the surrounding wiring which affects the calculation of the capacity are read out, copied to the working memory 20a in the data processing unit 20, and This is performed in the memory for memory 20a.

For example, as shown in FIG.
In the case where 3 is off-grid, the grid indicated by the dotted line is shifted in the direction perpendicular to the direction of the wiring 13 of interest, thereby turning the wiring of interest 13 on-grid as shown in FIG. Next, the wirings 14A and 15A existing within a distance of, for example, 0.75d from the grid adjacent to the wiring of interest 13
Is shifted onto the grid adjacent to the target wiring 13 so that the wirings 14A and 15A are rounded to on-grid wiring.

(S14) With respect to only the target wiring, the above-mentioned wiring state vector is obtained along the target wiring. (S15) The same processing as in steps S6 to S11 is performed to calculate the capacitance of the wiring of interest, store this in the column of capacitance C in the wiring table, and return to step S12.

Step 12 for off-grid wiring
By performing the processing of S15 to S15 for each line of interest, FIG.
The problem described above for 0 is solved. With the above processing, each wiring capacitance C in the wiring table memory 21 is obtained.
Is required. The capacitance of the bent wiring is obtained by adding the capacitance of the divided wiring.

The present invention also includes various modifications. For example, in FIG. 7B, the wiring state vector V may be obtained by using a range H1 to H4 of a distance d / 2 before and after the grid point as a center as a wiring segment. In this case, the length of the wiring segment at the wiring end is d / 2
Therefore, the output of the wiring state vector / segment capacity table memory 24 is multiplied by 1/2 ^m . That is,
Wiring state vector / segment capacity table memory 24
Is shifted m bits to the lower side. Where m is
The number of segments is d / 2 in length between the target wiring segment and the surrounding wiring segments.

The above word may be any storage unit for storing the wiring state vector in the memory. For example, (1 word) = (2 storage units) or (2 words) = (1 storage unit). Good. Also, the memories 20a, 21, 22
And 24 need only correspond to the storage area of the storage device.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a wiring capacitance calculation device according to an embodiment of the present invention.

FIG. 2 is a flowchart illustrating a procedure of processing by a data processing unit in FIG. 1;

FIG. 3 is a flowchart showing a continuation of FIG. 2;

FIG. 4 is an explanatory diagram of a wiring state vector.

FIG. 5 is an explanatory diagram of a process in step S1 of FIG. 2;

FIG. 6 is an explanatory diagram of a process in step S1 of FIG. 2;

FIG. 7A is a symbolic layout wiring diagram on a different pitch grid, and FIG. 7B is an explanatory diagram of calculating the capacitance of the wiring.

FIG. 8 is an explanatory diagram of a process in step S5 of FIG. 2;

FIG. 9 is an explanatory diagram of a problem in the related art.

FIG. 10 is an explanatory diagram of a problem in the related art.

[Explanation of symbols]

 Reference Signs List 20 data processing unit 20a working memory 21 wiring table memory 22 map memory 23, 26, 27 register 24 wiring state vector / segment capacity table 25 cumulative addition unit SP target wiring segment SL, SR, SU, SD wiring segment L1 to L3 wiring Layer G0-G3 Grid point

Claims (8)

[Claims] In a wiring capacitance calculating method for calculating a capacitance of a symbolic layout wiring, when a target wiring to be calculated is an off-grid wiring, data on the target wiring and surrounding wirings affecting the calculation of the capacitance are processed. A first step of copying the target wiring and surrounding wiring affecting the capacity calculation based on the copied data, and shifting the grid rigidly so that the target wiring is on-grid. A second step of wiring, a third step of rounding off-grid wiring within a predetermined distance from the target wiring to an on-grid wiring, and setting a wiring capacitance in grid units of the target wiring along the target wiring as a segment capacitance A fourth step of calculating and cumulatively adding the segment capacitances to obtain the capacitance of the wiring of interest. 2. The wiring capacitance according to claim 1, wherein in the third step, an off-grid wiring within a predetermined distance from an adjacent grid line parallel to the target wiring is rounded to a wiring on the grid line. Method of calculation. 3. When a wiring having a length of a grid interval is set as a wiring segment before the first step, a code indicating the presence / absence state of a wiring segment surrounding the wiring segment of interest is assigned to a wiring state vector of the wiring segment of interest. As
The segment capacity corresponding to the wiring state vector is calculated as follows:
The wiring state vector is stored in a memory as an address. In the fourth step, the wiring state vector is obtained for each wiring segment along the wiring of interest, and the memory is addressed by the obtained wiring state vector. 3. The wiring capacity calculation method according to claim 1, wherein the capacity of the wiring of interest is acquired by cumulatively adding the segment capacity read from the memory. 4. A wiring capacity calculation method for calculating a capacity of a wiring of interest corresponding to data read from symbolic layout wiring data stored in a wiring table storage area, wherein a wiring having a length of a grid interval is used as a wiring segment. A code indicating a distance between a grid line passing through the wiring segment of interest and a surrounding grid line parallel thereto,
A set of a code indicating the presence / absence state of the wiring segment around the target wiring segment is set as a wiring state vector of the target wiring segment, and a segment capacity corresponding to the wiring state vector, which is a capacity of the target wiring segment, is calculated as A first step of storing a wiring state vector as an address in a memory; and securing a wiring state vector storage unit corresponding to each grid point or between adjacent grid points in a map storage area. For each of the wiring data stored in the wiring table storage area, when the wiring corresponding to the wiring data is a non-interest wiring and the non-interest wiring is arranged along the grid, The wiring that affects the capacitance calculation is defined as the target wiring, and the influence of the non-target wiring on the wiring state vector as viewed from the target wiring is determined as the target wiring. A second step of writing to the storage unit corresponding to the line; sequentially reading wiring data from the wiring table storage area; for each read wiring data, setting a wiring corresponding to the wiring data as a target wiring; Read the contents of the storage unit as a wiring state vector along the wiring of interest with reference to the area, address the memory with the read wiring state vector, and accumulate the segment capacity read from the memory. A third step of obtaining the capacitance of the wiring of interest by adding. 5. The wiring of interest corresponding to the wiring data read from the wiring table storage area in the third step,
In the case of off-grid wiring, after the third step, data on the target wiring and surrounding wiring affecting the calculation of the capacity is copied to the working storage area without performing the capacity acquisition processing in the third step. In the working storage area, lay out the wiring of interest and surrounding wiring affecting the capacity calculation based on the copied data, rigidly shift the grid to make the wiring of interest on-grid wiring, The off-grid wiring within a predetermined distance from the target wiring is rounded to the on-grid wiring, the segment capacitance is calculated for each of the wiring segments along the target wiring, the segment capacitance is cumulatively added, and the capacitance of the target wiring is calculated. The wiring capacitance calculation method according to claim 4, wherein the calculation is performed. 6. A storage medium storing a program for executing the wiring capacitance calculation method according to claim 1. Description: 7. A wiring capacity calculating apparatus for calculating a capacity of a wiring of interest corresponding to data read from symbolic layout wiring data stored in a wiring table storage area, wherein each of the grid points or each space between adjacent grid points is determined. A map storage unit in which a storage unit for storing a wiring state vector is secured, a register, and a wiring having a length of a grid interval is defined as a wiring segment, and a distance between a grid line passing through the wiring segment of interest and a surrounding grid line parallel thereto. And a code indicating the presence / absence state of the wiring segment around the wiring segment of interest as a wiring state vector of the wiring segment of interest, the capacitance of the wiring segment of interest corresponding to the wiring state vector Is stored with the wiring state vector as an address, A table storage unit addressed by the output of the register, and for each of the wiring data stored in the wiring table storage area, a wiring corresponding to the wiring data is regarded as a non-interest wiring, and the non-interest wiring is arranged along the grid. When the wiring is placed in a position other than the wiring of interest, the wiring affecting the capacitance calculation is taken as the wiring of interest, and the effect of the wiring of interest as viewed from the wiring of interest on the wiring state vector is expressed as the wiring of interest. , And the wiring data is sequentially read from the wiring table storage area. For each read wiring data, a wiring corresponding to the wiring data is set as a target wiring, and the map storage area is Reference and along the wiring of interest,
A data processing unit for reading the contents of the storage unit as a wiring state vector and storing the contents in the register; and a cumulative addition unit for cumulatively adding the segment capacity read from the table storage unit to obtain the capacity of the wiring of interest. A wiring capacitance calculation device, comprising: 8. A work storage unit, wherein the data processing unit, when the wiring of interest corresponding to the wiring data read from the wiring table storage area is an off-grid wiring, calculates the wiring of interest and its capacitance. The data relating to the surrounding wiring affecting the wiring is copied to the work storage area, and the wiring of interest and the surrounding wiring affecting the capacity calculation are laid out in the work storage area based on the copied data. The grid is rigidly displaced to turn the wiring of interest into an on-grid wiring, the off-grid wiring within a predetermined distance from the wiring of interest is rounded to the on-grid wiring, and the segment capacitance is set for each of the wiring segments along the wiring of interest. 8. The wiring capacity calculation device according to claim 7, wherein the calculation is performed, and the segment capacity is cumulatively added to obtain the capacity of the wiring of interest.