JPH0276196A - Semiconductor device - Google Patents

Abstract

PURPOSE:To equalize the selecting time of a memory cell on a same bit at a word line by optimizing the method to form of an area to form an auxiliary word line and an area not to form the line. CONSTITUTION:Auxiliary word lines 4 to 7 and 8 to 11, in one side of adjoining word lines 1 and 2, are formed in respective sections of a length L/4M with respective points of a main word line 1 at the distance of L(4N-4)/4M and L(4N-1)/4M (provided that N=1,2,...,M,M is an integer and L is the length of a main word line) as a tip from one edge of the main word line 1 and in other side, respectively formed in respective sections of a length L/4M with respective points of the main word line at the distance of L(4N-3)/4M and L(4N-2)/4M as a tip from one edge of a main word line. Thus, the selection of the memory cell of the word lines 1 and 2 adjoining can be speeded up and the selecting time of the memory cell on the same bit line can be more equalized.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to semiconductor devices, particularly random access memories (
The present invention relates to the structure of a memory cell array in a DRAM (DRAM).

(Prior Art) A semiconductor device, such as a DRAM, has a large number of memory cells arranged in a matrix, multiple rows of bit lines from which data is extracted, and multiple columns that cross at right angles to the bit lines and select memory cells. It has a word line. The word line is selected and brought to a high potential, which serves to transfer data between the associated memory cell and the bit line.

In such a RAM, it is required to increase the read and write operation speed, but in order to increase the operation speed, it is necessary to lower the resistance of the word line.

FIG. 2 shows an example of a conventional semiconductor device in which the resistance of word lines is reduced (for example, Japanese Patent Laid-Open No. 63-6870). In FIG. 2, numerals 1 and 2 are word lines (hereinafter referred to as main word lines) made of layers with relatively high resistance, which are adjacent to each other, and one end of which is connected to a word driver 3. The main word line 1.2I/C is composed of word lines (hereinafter referred to as auxiliary word lines) 12 to 15 and 16 to 1 made of a layer having a lower resistance than the main word Hip2.
9 is connected. That is, the auxiliary word lines 12 to 15 are connected to the main word line 1 zl and z2 . z3 and z4z5 and z6. At each point zl and z8, the auxiliary word lines 16 to 19 are electrically connected to the main word line 2 at points Zll, zl2 # Zl3, zl4 # Zl5, Zl6 t, zl7, respectively. z4. Z2. ...,
z, and zl. The intervals between the points tZl, t..., z, 8 are almost equal, and the auxiliary word lines 12-15 and 16-
19 are formed so that they are not adjacent to each other. Although pit lines are not directly shown in FIG. 2, the relationship between word lines and pit lines is as shown in FIG. 3. In FIG. 3, the bit lines 20 and 21 are connected to the bit lines 20 and 21 of the transfer transistors Tr1 and Tr2, and the bit line 22 is connected to the drains of the transformer 7 add transistors Tr1 and Tr2.
Memory cells D4. D
2 are connected. When the word line 20 or 21 is set to a high potential, the transfer r-) transistor T'r or Tr2 is turned on and transmits the data of the memory cell D1 or D2 to the bit line 22.

At this time, the auxiliary word lines 12 to 19 are the main word lines l.

It works by lowering the resistance value of 2 and speeding up data transmission.

(Problem to be Solved by the Invention) However, in the above semiconductor device, there is a difference in memory cell selection time between adjacent word lines, which results in a difference in cell selection time on the same bit line. The problem was that it was not done.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device which eliminates the above-mentioned problems, speeds up the selection of memory cells on adjacent word lines, and improves the selection time of memory cells on the same bit line.

(Means for Solving the Problems) The present invention includes forming a plurality of auxiliary word lines having a lower resistivity than the main word line along the main word line, and electrically connecting both ends of each auxiliary word line to the main word line. In a semiconductor device having a memory array structure having a plurality of columns of word lines, the auxiliary word line is L (4N-4)74M from one end of the main word line in one of the adjacent word lines.
and L (4N-1)74M (however, N=1.2...
・, M, M is an integer, L is the length of the main word line) The length L / 4 from the tip to each point of the main word line
Within each section of M, on the other hand, there is a length L ending at each point of said main word line that is at a distance of L(4N-3 - 4M and L(4N-2) 74M from one end of that main word line, on the other hand). /4
This semiconductor device is characterized in that the semiconductor device is formed in each section of M.

(Function) The present invention optimizes the method for forming regions in which auxiliary word lines are formed and regions in which auxiliary word lines are not formed in adjacent word lines, thereby making the selection time of memory cells on the same bit on the word line uniform. It is also possible to shorten the selection time and speed up the selection.

(Example) FIG. 1 is a circuit diagram showing an embodiment of the present invention.

In FIG. 1, l and 2 are main word lines made of relatively high resistance layers, 3 is a word driver that drives the main word lines 1 and 2, and 4 to 2 and 8 to 11 are for the main word lines 1 and 2. The main word line and the auxiliary word line constitute the auxiliary word line, which is composed of a layer with a lower resistance. The auxiliary word lines 4 to 11 are formed along and above the main word line 1 or 2, and both ends thereof are connected to the main word line 1 or 2. 7 or 2 zl and z2. z4 and z5. z5 and 26, 28 and z9j z,
1 and z12s Zl2 and z13゜z, s and Zl, S s
They are electrically connected at each point zl6 and Zl7. The auxiliary word lines 4 to 7 and 8 to 11 are formed so as not to be adjacent to each other, and the entire auxiliary word lines 4 to 7,
The total length of lines 8 to 11 occupies approximately half the area of main word line 1 or 2.

According to the present embodiment shown in FIG. 1, compared to the conventional circuit shown in FIG. 2, it is possible to more uniformize the selection time of mesori cells on the same bit line in adjacent word lines. Also, it is possible to speed up the selection of memory cells.

4 and 5 are circuit diagrams used to compare the effect of this embodiment and the effect of the conventional example using a simulator. FIG. 5 is a simulation circuit diagram corresponding to FIG. 2. In Figures 4 and 5, 1 and 2 are main word lines, 3 is a word driver, M1 to M16 are main word line circuits, R1 to R16 are auxiliary word line resistors, and C1 to C29 are auxiliary word lines. The wiring capacity of the line is j5. R
The value of R16 to 1 is 15.568Ω, C1~c, , C
5~C8, C1°.

C11# The value of C13 to C29 is 0.07284PF,
C4°c, # The value of C12 is 0.14568PF.

FIG. 6 is a circuit diagram showing the main word line circuits M, to M16 shown in FIGS. 4 and 5, and includes R17 to R20.
is the resistance of the main word line, C1-054 is the wiring capacitance %Q1~
Q5 is a transformer 7 agate transistor. Here, the value of the resistors R17 to R20 is 0.854681 Ω, the dart width of the transformer 7 add transistor Q, ~Q5 is 16 μm, the gate length is 0.75 μm, and the wiring capacitance is 03 G.
The value of C34 is Coo #C54 is 0.0234PF, C, ~ C3 in the area where the auxiliary word line is not formed.
3 is 0.0468 pF, and in the area where the auxiliary word line is formed, C30# C54 is 0.0206 pF, C
3, ~css is 0.0412PF.

FIG. 7 and FIG. 8 are diagrams showing the results of shimmy erase using the circuit diagrams shown in FIGS. 4 and 5. FIG. That is, the seventh
The figure shows the smearing results for the smearing circuit (Fig. 4) corresponding to the conventional example shown in Fig. 2.
D, a are 2 and 2. in FIG. . The input waveform at K, b is the most delayed point on main word line 1, 2. The waveform C is the waveform at the point Z18 where the main word line 2 is delayed the most.

On the other hand, FIG. 8 shows the results of the stain removal circuit (FIG. 5) corresponding to the embodiment of the present invention shown in FIG. 1, and a is 2 in FIG. , and 21
The input waveform at 0 (same as the input waveform shown in FIG. 7), b and c are the point Z at which the main word lines 1 and 2 are delayed the most.
, , 218. In FIG. 7, there is a delay difference between the waveform S and C, but in FIG. 8, there is almost no delay difference between the waveform S and C, and
Waveforms S and C shown in FIG. 8 have less delay than waveform C shown in FIG. That is, according to this embodiment, there is almost no signal delay difference between two adjacent word lines, and the signal speed is increased.

In the embodiment shown in FIG. 1, the main word line is divided into eight,
Auxiliary word lines are formed in predetermined sections.1 Generally, the main word line is divided into 4M (M is an integer), and for one adjacent main word line, L (4N 4) 74 lines are formed from one end of the main word line.
M and L(4N-1)74M (However, N=1, 2
, . . . , M, I, is the length of the main word line) within each section of length L/4M with each point at the tip, and for the other main word line, from one end to L. (4N -3)
The same effect can be obtained by forming auxiliary word lines within each section of length L/4M with the tip at each point located at a distance of /4M and L(4N-2)74M. Note that by forming the connection points z1 to Z18 shown in FIG. 1 so that the distances between them are the same and forming a checkerboard pattern, the selection time can be made more uniform.

(Effects of the Invention) As described above in detail, according to the present invention, the selection time for memory cells on the same pit line in adjacent word lines can be made more uniform, and the selection time can also be sped up. can.

Note that the present invention is not limited to DRAM, but also applies to SRAM, R
OM.

All ICs with word lines, such as memory ICs such as EPROMs and microcomputers containing these memories,
It can be applied to C.

[Brief explanation of the drawing]

FIG. 1 is a detailed explanatory diagram of the present invention, FIG. 2 is an explanatory diagram of a conventional semiconductor device, FIG. 3 is a diagram showing the relationship between word lines and bit lines, and FIG. Figure 5 is a circuit diagram of the circuit for simulators shown in Figure 1, Figure 6 is a circuit diagram of M1 to M2S, and Figure 7 is a diagram showing the results of the simulation of Figure 4. , FIG. 8 is a diagram showing the results of the simulation of FIG. 5. 1.2... Main word line, 3... Word driver, 4
~11... Auxiliary word line. Patent applicant: Oki Electric Industry Co., Ltd.
Yako Figure 2 Figure 3 1.2 + \io + Shireji Hiko - Memu Road Figure 4 JLI Figure th Shiro s - Rege m > 111i1 %'
j2rFigure 5M1~Mτ8#I(ii) LessonsFigure 6Figure 7Figure 8

Claims (1)

[Scope of Claims] A plurality of rows of word lines are formed by forming a plurality of auxiliary word lines having a lower resistivity than the main word line along the main word line, and electrically connecting both ends to the main word line. In a semiconductor device having a memory cell array structure, the auxiliary word line is L(4N-4)/4M and L(4N-1)/4M( from one end of the main word line in one of the adjacent word lines). However, N=1, 2,...,M
, M is an integer, and L is the length of the main word line), within each section of length L/4M starting at each point of the main word line, and on the other hand from one end of the main word line. L (4N
-3) A semiconductor characterized in that it is formed in each section having a length of L/4M with its tip at each point of the main word line located at a distance of /4M and L(4N-2)/4M, respectively. Device.