JPH1138091A - Analog-digital mixedly loaded circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an analog-digital mixedly loaded circuit having a structure which can cancel a state of an analog pad through a board test depending upon a boundary scanning technique. SOLUTION: A/D converter 3 and a digital circuit 4 are mixedly loaded on the same semiconductor, and a boundary scan cell 7 is arranged in a boundary between the A/D converter 3 and the digital circuit 4. The boundary scan cell 7 has an input section (API) to input the digital output of the A/D converter 3 and an input section (DPI) to input a signal sent from the analog pad 1 in the A/D converter 3, and is equipped with a selection means for selecting either of inputs, and the selecting motion of the selecting means is carried out on a selection signal obtained by decoding a command sent from a nonillustrated boundary scanning command register.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog / digital mixed circuit capable of reliably and easily testing a circuit operation when mounted on a printed circuit board.

[0002]

2. Description of the Related Art Various board tests are performed when a semiconductor integrated circuit (IC) is mounted on a printed circuit board.
As this test method, a boundary scan according to IEEE1149.1 is known. The IC corresponding to the boundary scan includes a boundary scan cell including a register, a latch circuit, and the like in the IC. A plurality of boundary scan cells are connected to each other to form a scan chain (scan register). When the IC is a digital circuit, the scan chain is inserted at the boundary between the pad of the IC and the internal logic circuit. By using the boundary scan cell, a signal can be input and output from the pad regardless of the normal operation logic of the IC, and by examining the signal from the boundary scan cell,
Operation test can be performed. Such an IC corresponding to the boundary scan is disclosed in detail in Japanese Patent Application Laid-Open No. H4-211842.

On the other hand, when the IC is an analog / digital mixed circuit, the scan chain is inserted at the boundary between the analog circuit section and the digital circuit section. FIG.
FIG. 8 is a block diagram showing a schematic configuration of an analog / digital mixed circuit, and FIG. 8 is a block diagram when a scan chain is inserted into the analog / digital mixed circuit. In the figure, 101 is an analog pad, 102 is an amplifier, 103 is an analog circuit (here, an A / D converter), 104 is a digital circuit, and 105 and 106.
Is a digital pad. And 201 is the A
A boundary scan cell arranged at the boundary between the / D converter 103 and the digital circuit 104;
Reference numeral 203 denotes a boundary scan cell arranged between the digital circuits, and these boundary scan cells and another boundary scan (not shown) are connected to each other to form a scan chain.

[0004]

However, as described above, in the configuration in which the boundary scan cell 201 is inserted at the boundary between the A / D converter 103 and the digital circuit 104, the state of the analog pad 101 can be scanned. As a result, failure diagnosis of wiring connected to the analog pad 101 cannot be performed.

Japanese Patent Application Laid-Open No. Sho 62-172751 discloses a technique for easily performing an operation test of a mixed analog / digital circuit.
It is disclosed that the output of the converter is sent to a digital pad so that the A / D converter and the digital circuit are separated to perform a test on the A / D converter side.
No. 93485 discloses that a test is performed while separating an A / D converter and a digital circuit by a scan path and shifting the data by the shift register to amplify the output of the A / D converter in a pseudo manner. Is disclosed.

[0006] However, Japanese Patent Application Laid-Open No. Sho 62-172751.
In the technique disclosed in the publication, the method of separating the A / D converter and the digital circuit is performed only by switching the transmission signal to the pad, and is not configured to perform the separation by the scan path. On the other hand, in the technique disclosed in JP-A-63-293485, although separation is performed by a scan path, the technique does not use the boundary scan technique.

In view of the above circumstances, an object of the present invention is to provide an analog / digital mixed circuit having a structure capable of scanning the state of an analog terminal in a board test using a boundary scan technique.

[0008]

In order to solve the above-mentioned problems, an analog / digital mixed circuit according to the present invention includes an analog circuit, an A / D converter and a digital circuit mixedly mounted on the same semiconductor. In an analog / digital mixed circuit in which a boundary scan cell is arranged at a boundary between an A / D converter and the digital circuit, the boundary scan cell includes an input unit for inputting a digital output of the A / D converter. An input unit for inputting a signal from an analog pad in the A / D converter, and selecting means for selecting one of the inputs; and a selecting operation of the selecting means is performed by a signal from a boundary scan instruction register. It is characterized in that it is performed by a selection signal obtained by decoding an instruction.

With the above configuration, a signal from the analog pad of the A / D converter (a digital signal is input at the time of a test) is selected by the selecting means, and the selected signal is taken into the boundary scan cell. Therefore, the state of the analog pad can be scanned by the boundary scan mechanism. Therefore, in the board test, it is possible to detect a defect in wiring connected to the analog pad of the analog / digital mixed circuit and a defect in soldering.

In the analog / digital hybrid circuit according to the present invention, a D / A converter and a digital circuit, which are analog circuits, are mounted on the same semiconductor, and a boundary between the D / A converter and the digital circuit is provided. In an analog / digital hybrid circuit in which a boundary scan cell is arranged, an output terminal of the boundary scan cell is connected to an output pad of the D / A converter via a bus, and the bus is connected to a boundary scan instruction register. Is controlled by a selection signal obtained by decoding the instruction.

With the above configuration, the signal of the boundary scan cell can be output from the output pad of the D / A converter using the bus, so that the state of the output pad is determined by the boundary scan mechanism. Can scan. Therefore, in board test,
It is possible to detect a defect of wiring connected to the output pad of the digital hybrid circuit and a defect of soldering.

In the analog / digital mixed circuit of the present invention, a D / A converter and a digital circuit, which are analog circuits, are mounted on the same semiconductor, and a boundary between the D / A converter and the digital circuit is provided. A first boundary scan cell group disposed and a second boundary scan cell group disposed between the digital circuit and the digital pad are connected to form a scan chain, and one end of the scan chain Side, a test data in terminal is provided, and the other end is provided with a test data out terminal. In the analog / digital mixed circuit, the test data in terminal, the first boundary scan cell group, and the test data Selection means for selecting a path connecting to the OUT terminal, and the selection operation of the selection means is performed by a Characterized in that it is so performed by selection signals obtained by decoding the instruction from the scan instruction register.

With the above arrangement, when performing an operation test of the A / D converter, the selecting means connects the test data-in terminal, the first boundary scan cell group, and the test data-out terminal. Path, ie
Partial scan chains can be generated. Therefore, the test time for performing the operation test of the A / D converter can be reduced as compared with the case where the entire scan chain is used.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment 1) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an analog / digital hybrid circuit according to this embodiment. In the figure, 1 is an analog pad, 2 is an amplifier, 3 is an A / D converter, 4 is a digital circuit, 5 and 6 are digital pads, and 7, 8, and 9 are boundary scan cells. These boundary scan cells 7, 8, and 9 and other boundary scan cells (not shown) are connected to each other to form a scan chain.
The boundary scan cells 8 and 9 include a D / A converter 4
The boundary scan cell 7 is provided between the digital circuit 4 and the A / D converter 3, while the boundary scan cell 7 is provided between the digital circuit 5 and the digital pads 5 and 6. The boundary scan cell 7 has an input section (API) for inputting a digital output of the A / D converter 3 and an input section (DPI) for directly inputting a signal from the analog pad 1 in the A / D converter 3. And a terminal (SI) connected to a boundary scan (not shown) at the preceding stage.
And a terminal (SO) to which the next-stage boundary scan (not shown) is connected, and an output unit (PO) connected to the digital circuit 4. Also, this boundary scan cell 7 includes SELECT, CAPTURE, and UP.
Signals such as DATA and MODE are input. In addition,
UPDATA is a control signal from a TAP (test access port) not shown, and MODE is a control signal distributed by decoding an instruction code in an instruction register not shown.

FIG. 2 is a block diagram showing the internal configuration of the boundary scan cell 7. First multiplexer 7
“a” selects one of the inputs of the input unit (API) and the input unit (DPI) and outputs it to one input terminal of the second multiplexer 7b. The selection operation of the first multiplexer 7a is performed by the SELECT, which is a selection signal obtained by decoding an instruction from a boundary scan instruction register (not shown) by a decoder (for example, the decoder is configured by a program logic array or the like). In the EXTEST, the input unit (DPI)
Is selected, and when the A / D converter 3 is inspected, the input unit (A
PI) is selected. The second multiplexer 7b has a first
The signal output from the multiplexer 7a and the terminal (SI)
And outputs the selected signal. The first flip-flop (CAP) holds the output of the second multiplexer 7b based on the CAPTURE signal. The second flip-flop (UPD) holds an output of the first flip-flop (CAP) based on the UPDATE signal. The third multiplexer 7e outputs one of the signal output from the second multiplexer 7b and the signal output from the second flip-flop (UPD) to the MO.
The selection is made based on the DE signal and output to the output section (PO).

Next, the operation of the analog / digital hybrid circuit will be described with reference to FIGS. Figure 3 shows EXT
The signal path at the time of EST is described, and FIG. 4 illustrates the signal path at the time of inspection of the A / D converter 3.

When testing the A / D converter 3, an analog test signal is input to the analog pad 1 as shown in FIG. This analog test signal is supplied to the input section (AP
Is taken into the boundary scan cell 7 via I),
An operation test of the A / D converter 3 is performed. EXTES
At time T, a digital test signal is input to the analog pad 1 as shown in FIG. This test signal is supplied to the boundary scan cell 7 via the input unit (DPI).
Therefore, the state of the analog pad 1 can be scanned by the boundary scan mechanism. Therefore, in the board test, it is possible to detect a defect of the wiring connected to the analog pad 1 of the analog / digital mixed circuit and a defect of the soldering.

(Embodiment 2) FIG. 5 is a circuit diagram showing a main part of an analog / digital mixed circuit according to a second embodiment. A boundary scan cell 11 is provided at a boundary between the D / A converter 12 and a digital circuit (not shown). The output terminal of the D / A converter 12 is connected to the output pad 14 via the gate 13. A bus 15 is constituted by a line 15a connecting the input terminal of the D / A converter 12 and the output terminal of the gate 13, and a three-state buffer 15b inserted in the line 15a. A control signal from the instruction decoder 16 is input to a control terminal of the three-state buffer 15b. The instruction decoder 16 receives TCK (test clock), TMS (test mode select), and TDI (test data in).

With the above configuration, when testing the D / A converter 12, the three-state buffer 15b is disabled by an instruction (control signal) from the instruction decoder 16, and the D / A converter is connected to the output pad 14. The analog signal from 12 is output. The operation test of the D / A converter 12 can be performed by detecting this analog signal. On the other hand, E
At the time of XTEST or the like, the three-state buffer 15 is controlled by an instruction (control signal) from the instruction decoder 16.
b is enabled, and the boundary scan cell 1
1 from the D / A converter 1 using the bus 15.
2 can be output from the output pad 14,
The state of the output pad 14 can be scanned by a boundary scan mechanism. Therefore, in the board test, it is possible to detect a defect of wiring connected to the output pad 14 of the analog / digital mixed circuit, a defect of soldering, and the like. That is, the EXTEST of IEEE1149.1
A (wiring connection test) command, a HIGHZ (high impedance test) command, and a CLAMP (clamp test) command can be executed on the output pad 14.

(Embodiment 3) The hybrid analog / digital circuit of this embodiment is obtained by improving the basic configuration shown in FIG. 7A as shown in FIG. 7B. To briefly explain the basic configuration, a D / A / A / D converter 22 having analog pads 20 and a digital circuit 23 having digital pads 21 are mounted together on the same semiconductor. A first boundary scan cell group 24 is disposed at a boundary between the D / A / A / D conversion section 22 and the digital circuit 23, and a first boundary scan cell group 24 is provided between the digital circuit 23 and the digital pad 21. Two boundary scan cells 25 are arranged and connected to form a scan chain. A test data in terminal (TDI) is provided at one end of the scan chain, and a test data out terminal (TDO) is provided at the other end.

The improvement will be described. As shown in FIG. 2B, the test data in terminal (TD)
A line 26 is provided between I) and the input side end of the first boundary scan cell group 24 to connect them. Further, a line 27 connecting the output side end of the first boundary scan cell group 24 and the selector 28 is provided. The selector 28 has a two-input configuration. One input terminal is connected to the line 27, and the other input terminal is connected to the output terminal (TD) of the second boundary scan cell group 25.
O), and one of these two inputs is selected based on the SELECT signal and T
Output to DO. The SELECT signal is a signal obtained by decoding an instruction from a boundary scan instruction register (not shown) by a decoder. During a normal test, the output terminal of the second boundary scan cell group 25 is selected, and the D / A signal is output. , A / D converter 22 is selected so that the line 27 is selected.

The configuration of the input end of the first boundary scan cell group 24 will be described with reference to FIG. 4 shown in the first embodiment.
This corresponds to a configuration including a multiplexer (not shown) in the portion I), and selects the signal of the input terminal (SI) and the signal of the TDI. This selection operation is also performed by a signal obtained by decoding an instruction from a boundary scan instruction register (not shown) by a decoder. In a normal test, a signal at an input terminal (SI) is selected, and D / A, A / D
When the converter 22 is tested, the TDI (that is, the line 26) is selected.

With the above configuration, the D / A, A / D
When an operation test of the conversion unit 22 is performed, a path connecting the test data in terminal (TDI) → the first boundary scan cell group 24 → the test data out terminal (TDO) by the multiplexer and selector 28 (not shown), that is, Partial scan chains can be generated. Therefore, the test time for performing the operation test of the D / A and A / D converters 22 can be reduced as compared with the case where the entire scan chain is used.

[0025]

As described above, according to the present invention, in an analog / digital mixed circuit, it is possible to easily inspect the state of the pad on the analog circuit side. In addition, when an analog circuit is inspected, a partial scan chain is generated to shorten the test time.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main part of an analog / digital mixed circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a boundary scan cell in the mixed analog / digital circuit of FIG. 1;

3 is an explanatory diagram showing a signal flow when inspecting a state of a pad on an analog side in the analog / digital mixed circuit of FIG. 1;

FIG. 4 is an explanatory diagram showing a signal flow when inspecting a state of an analog circuit in the analog / digital mixed circuit of FIG. 1;

FIG. 5 is a block diagram showing a main part of an analog / digital mixed circuit according to a second embodiment of the present invention.

FIG. 6A is a block diagram showing an example of a basic configuration of an analog / digital mixed circuit, and FIG. 6B is a third embodiment of the present invention in which FIG. FIG. 2 is a block diagram showing a mixed analog / digital circuit according to the embodiment.

FIG. 7 is a block diagram illustrating an example of a basic configuration of an analog / digital mixed circuit.

FIG. 8 is a block diagram illustrating an example of a conventional analog / digital mixed circuit having a boundary scan configuration.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Analog pad 2 Amplifier 3 A / D converter 4 Digital circuit 5, 6 digital pad 7, 8, 9 Boundary scan cell 11 Boundary scan 12 D / A converter 14 Output pad 15 Bus 15a line 15b Three-state buffer 16 Instruction Decoder 20 Analog pad 21 Digital pad 22 D / A, A / D converter 23 Digital circuit 24 First boundary scan cell group 25 Second boundary scan cell group 26 Line 27 Line 28 Selector

Claims (3)

[Claims] An analog / digital converter in which an A / D converter as an analog circuit and a digital circuit are mixedly mounted on the same semiconductor, and a boundary scan cell is arranged at a boundary between the A / D converter and the digital circuit. In the digital hybrid circuit, the boundary scan cell includes an input section for inputting a digital output of the A / D converter and an input section for inputting a signal from an analog pad in the A / D converter. A selection means for selecting one of the inputs is provided, and the selection operation of the selection means is performed by a selection signal obtained by decoding an instruction from a boundary scan instruction register. Analog / digital mixed circuit. 2. An analog / digital converter in which a D / A converter as an analog circuit and a digital circuit are mixedly mounted on the same semiconductor, and a boundary scan cell is arranged at a boundary between the D / A converter and the digital circuit. In the digital hybrid circuit, an output terminal of the boundary scan cell is connected to an output pad of the D / A converter via a bus, and the bus is a selection signal obtained by decoding an instruction from a boundary scan instruction register. An analog / digital mixed circuit characterized in that it is controlled by: 3. A first boundary scan cell group in which a D / A converter, which is an analog circuit, and a digital circuit are mixedly mounted on the same semiconductor, and which is arranged at a boundary between the D / A converter and the digital circuit. And a second group of boundary scan cells arranged between the digital circuit and the digital pad to form a scan chain. A test data in terminal is provided at one end of the scan chain. An analog / digital mixed circuit provided with a test data out terminal on the other end side, for selecting a path connecting the test data in terminal, the first boundary scan cell group, and the test data out terminal. Selecting means for decoding an instruction from the boundary scan instruction register. Analog-digital mixed circuit which is characterized in that is adapted to be performed by the obtained selection signal.