JPH11355127A - Precharging circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the delay of a data signal and to reduce power consumption by operating a first circuit and precharging a load to a high level in a precharging period, and operating a second circuit or preventing it from being operated with the combination of a clock signal and data and changing the high level of a load to a low level or holding the high level in a logic operation period. SOLUTION: In a precharging period, a clock signal CK1 is set to a high level and first N channel MOSFET 2 is turned on. Power voltage high level VDD passes through first channel MOSFET 2 by turning on first channel MOSFET 2 and load capacity 5 is precharged. Output data OUT 1 of the high level based on precharging voltage is generated to load capacity 5. In a logic operation period, the clock signal CK1 changes from the high level to a low level, first channel MOSFET 2 changes from 'on' to 'off' and the precharging of load capacity 5 is stopped.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a precharge circuit, and more particularly to a precharge circuit for precharging a load by using a precharge voltage supplied from a power supply high-level terminal to the load through an N-channel MOSFET. The present invention relates to a precharge circuit that achieves high speed and low power consumption of a circuit.

[0002]

2. Description of the Related Art Conventionally, as a gate circuit used for processing a data signal, a gate circuit having a CMOS circuit connected between a power supply high-level terminal and a power supply low-level terminal for charging and discharging a load (hereinafter referred to as a gate circuit). ,
This is referred to as a known first gate circuit) or a P-channel M having a weak driving force between the power supply high-level terminal and the load.
The OSFET and a logic circuit having an N-channel MOSFET having a strong driving force are connected between the load and the low-level terminal of the power supply, respectively. A precharge circuit (hereinafter referred to as a precharge circuit (hereinafter referred to as a charge circuit) for switching the operation and non-operation of the N-channel MOSFET of the logic circuit during the non-precharge period of the load to keep the precharge voltage of the load as it is or discharge the precharge voltage of the load , Which is referred to as a known second precharge circuit).

In this case, the known second precharge circuit performs most of the logic operation by using an N-channel MOS transistor having a strong driving force.
Since the operation is performed by using the FET, there is an advantage that the operation speed can be increased as compared with the known first precharge circuit.

In addition, a domino circuit is known as an application circuit of the precharge circuit, not the precharge circuit itself. This domino circuit is a P-channel MOSFET between the power supply high level terminal and the power supply low level terminal.
, A multi-input NMOS logic circuit and an N-channel MOSFET in series, and a P-channel MOSFET and an N-channel M
A clock signal is supplied to the gate of the OSFET, and a connection point between the P-channel MOSFET and the multi-input NMOS logic circuit is connected to an output terminal through an inversion circuit. The inversion circuit used in the domino circuit has a function of shaping the waveform of the data signal and separating the internal load from the output load. During the precharge period of the domino circuit, many inversion circuits connected to the next stage are provided. Since the operation of the input NMOS logic circuit is made inoperative, it is possible to connect domino circuits of the same configuration in multiple stages.

In each of the known first gate circuit, known second precharge circuit and known domino circuit, the high level of the data signal to be processed is the voltage of the power supply high level terminal, and the low level of the data signal is the power supply low level. Since these are equal to the voltage of the terminal (ground voltage) and are at the same level as the high level and the low level of the data signal processed by another known general-purpose CMOS circuit, these other general-purpose CMOs are known.
The interface with the S circuit can be easily performed.

[0006]

By the way, the known second technique
The precharge circuit converts the voltage of the power supply high-level terminal into a P-channel MOS
Since the load is precharged through the FET and the P-channel MOSFET is not involved in the data signal delay (critical path delay), it is required to operate at a higher speed than the known first gate circuit using a CMOS circuit. Can be.

However, since the known second precharge circuit performs the precharge and discharge of the load in synchronization with the input clock signal, the frequency of the precharge and discharge of the load is known. There is a problem that the frequency is twice as high as the same frequency of one gate circuit, and the power consumption increases accordingly.

Further, the domino circuit is very effective when the same circuit is connected in multiple stages, and the internal load (precharge node) is discharged by an N-channel MOSFET having a strong driving force. Known second
Same as the precharge circuit, but the output load is driven by an inverting circuit connected between the internal load and the output load, so it is equivalent to driving the output load with a weak P-channel MOSFET. And the data signal delay (critical path delay) is P channel MOS
There is a problem that the data signal delay (critical path delay) is deteriorated due to the influence of the FET.

In order to address these problems, recently, an N-channel M channel has been connected between the power supply high-level terminal and the load.
The OSFET is connected, and during the load precharge period, the load is precharged through this N-channel MOSFET, and the precharge voltage of the load is reduced to a voltage lower than the voltage of the power supply high-level terminal by the threshold value of the N-channel MOSFET. Then, a precharge circuit designed to reduce power consumption and speed up data signal processing has been proposed and is disclosed in Japanese Patent Application Laid-Open No. 6-5083.

The precharge circuit disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 6-5083, for the time being, makes the precharge voltage of the load N-channel MO
By reducing the voltage to the voltage lower by the threshold value of the SFET, the power consumption is reduced and the data signal processing is speeded up as compared with the case where the precharge voltage of the load is equal to the voltage of the power supply high level terminal. Can be achieved.

On the other hand, the precharge circuit disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 6-5083 includes a data register for reading out a data signal, a data register and a load between the data register and a load, as related circuit parts necessary for operating the precharge circuit. , A control signal generating circuit for generating a precharge circuit control signal supplied to a control terminal (gate) of an N-channel MOSFET, and a transfer gate control signal supplied to a control terminal (gate) of the transfer gate Therefore, many related circuits such as the control signal generation circuit for generating the above are required, which causes a problem that the entire circuit configuration is complicated and the manufacturing cost is increased.

In the precharge circuit disclosed in Japanese Patent Application Laid-Open No. 6-5083, the precharge voltage of the load is discharged through the transfer gate and the data register during the discharge period of the load. There is also a problem that the discharge of the charge voltage becomes slow and the data signal delay (critical path delay) cannot be made so good.

The present invention solves all of these problems. It is an object of the present invention to reduce data signal delay, reduce power consumption, and simplify the circuit configuration.
An object of the present invention is to provide a precharge circuit capable of reducing manufacturing costs.

[0014]

In order to achieve the above object, a precharge circuit according to the present invention comprises a precharge period for receiving a clock signal and data and precharging a load when one polarity of the clock signal arrives. A logic operation period for performing a logic operation corresponding to data when the other polarity of the clock signal arrives is alternately executed, and a first circuit including at least one first N-channel MOSFET connected between a power supply high-level terminal and a load; A second circuit connected between the load and the power supply low-level terminal and including at least one second N-channel MOSFET;
A logic circuit connected to the FET and selectively operating according to the clock signal and the data, wherein the first circuit operates during the precharge period to precharge the load to a high level; In this combination, the second circuit is activated or deactivated to change the high level of the load to the low level or to switch the load so as to maintain the high level.

According to the above means, when the load is precharged to the high level by controlling the input clock signal, the precharge voltage is lowered from the power supply high level by the threshold voltage of the first N-channel MOSFET. Discharge operation is speeded up by the threshold voltage, and when the data high level of the load is reduced by the threshold voltage, the amount of charge for precharging and discharging the load is reduced, and low power consumption is achieved. .

According to the above means, during the discharge period of the load, the second N-channel MOSFET is driven to an on state by a combination of a clock signal and data,
Since the precharge voltage is discharged via the second N-channel MOSFET, the discharge can be quickly performed with a simple circuit configuration, and a precharge circuit having good data delay characteristics can be obtained.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In a main embodiment of the present invention, a precharge circuit receives a clock signal and data, and precharges a load when one polarity of the clock signal arrives; A logic operation period in which a logic operation corresponding to data is performed alternately when the other polarity is reached, wherein the first circuit is connected between the power supply high-level terminal and the load and includes at least one first N-channel MOSFET A second circuit connected between the load and the power supply low-level terminal and including at least one second N-channel MOSFET;
A logic circuit connected to the FET and selectively operating according to a clock signal and data; during a precharge period, the first circuit operates and a load is precharged to a high level; The combination with the data activates or deactivates the second circuit,
The high level of the load is changed to a low level, or the load is switched so as to maintain the high level.

In the first embodiment of the present invention, the precharge circuit is a precharge type logic circuit in which a logic circuit precharges its output load, and precharges the load to a high level during a precharge period. At this time, it operates so as to precharge the output load of the precharge type logic circuit to a low level.

In a modification of the first embodiment of the present invention, in the precharge circuit, the precharge type logic circuit is a multi-input logic circuit, and different data signals are input to respective inputs of the multi-input logic circuit. Is what you do.

In the second embodiment of the present invention, the precharge circuit has a logic circuit having a plurality of multi-input logic circuits, and different data are input to respective inputs of the plurality of multi-input logic circuits. A second circuit having a plurality of second N-channel MOSFETs each having an input connected to a corresponding output of the plurality of multi-input logic circuits, wherein the plurality of second N-channel MOSFETs are single or in series with other second N-channel MOSFETs; It is connected between the load and the power supply low level terminal.

In the third embodiment of the present invention, the precharge circuit comprises a first circuit, a first N-channel MOSFET having a power supply voltage supplied to an input terminal, and a first N-channel MOSFET.
A P-channel MOSFET to which a clock signal is supplied to an input terminal connected in series to the SFET.

In a specific example of the third embodiment of the present invention, in the precharge circuit, the second circuit comprises a second N-channel MOSFET to which a clock signal is supplied to an input terminal, and a logic circuit differs for each input. The data is inputted, and is constituted by a multi-input NMOS logic circuit connected in series to the second N-channel MOSFET.

In one of the embodiments of the present invention, the precharge circuit is such that data is supplied through a level conversion circuit which makes its high level equal to the voltage of the power supply high level terminal.

In another embodiment of the present invention, the precharge circuit has a load connected to an NMOS drive circuit for driving a next-stage load, and the NMOS drive circuit precharges the next-stage load. 3N channel MO
An SFET and a fourth N-channel MOSFET for discharging a next-stage load, precharging the next-stage load via a third N-channel MOSFET during a load precharge period, and via a fourth N-channel MOSFET during a load discharge period. To discharge the next stage load.

In an application example of each embodiment of the present invention,
In a semiconductor integrated circuit, a plurality of logic blocks including a precharge circuit are arranged in a large-scale integrated circuit chip, and a signal interface in each logic block uses a CMOS-level data signal whose high level is equal to a power supply high level. The signal interface between the logic blocks uses a data signal in which the high level is precharged to the power supply high level through the first N-channel MOSFET.

According to these embodiments of the present invention, during the precharge period in which the first N-channel MOSFET is turned on by one polarity of the supplied clock signal,
A first circuit including a first N-channel MOSFET operates to precharge the load to a high level, and during a logic operation period,
The combination of the other polarity of the clock signal and each polarity of the data activates or deactivates the second circuit including the second N-channel MOSFET, and changes the high level of the load to a low level or maintains the high level. Since the precharge voltage of the load is lowered from the power supply high level by the threshold voltage of the first N-channel MOSFET, it is possible to speed up the discharge operation of the load by the low threshold voltage. Become
When the signal amplitude of the load is reduced by the low threshold voltage, the amount of charge for precharging and discharging the load is reduced, so that low power consumption can be achieved.

According to these embodiments of the present invention, the second N-channel MOSFET during the logic operation period
During the operation of the second circuit including the second circuit, the precharge voltage of the load is discharged to the power supply low level side (ground point) through the second N-channel MOSFET. Can be performed quickly, and an inexpensive precharge circuit having good data delay characteristics can be obtained.

[0028]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing a configuration of a first embodiment of a precharge circuit according to the present invention.

In FIG. 1, 1, 1 'is an NMOS precharge circuit, 2 and 2' are first N-channel MOSFETs,
3, 3 'is a second N-channel MOSFET, 4, 4' is N
OR circuits (logic circuits), 5 and 5 'are load capacitors, CK1,
CK2 is a clock signal, DATA1 is input data, OU
T1 is the output data of the NMOS precharge circuit 1, OU
T2 is the output data of the NMOS precharge circuit 1 ', V
DD is a power supply high level voltage, and VSS is a power supply low level voltage (ground voltage).

The NMOS precharge circuit 1 and the NMOS precharge circuit 1 'are cascaded along a data transmission path. NMOS precharge circuit 1
Are the power supply high level voltage VDD and the power supply low level voltage V
1st N-channel MOSFE connected in series with SS
T2, a second N-channel MOSFET 3, and a NOR whose output is connected to the gate of the second N-channel MOSFET 3.
A clock signal CK1 is supplied to the gate of the first N-channel MOSFET 2 and one input of the NOR circuit 4, and the input data DA is supplied to the other input of the NOR circuit 4.
TA1 is supplied. A load capacitance 5 is externally connected between a connection point between the first N-channel MOSFET 2 and the second N-channel MOSFET 3 and between the power supply low-level voltage VSS. Also, the NMOS precharge circuit 1 '
The first N-channel MOSFET 2 ′ and the second N-channel MOSFET having the same configuration as the precharge circuit 1 and connected in series between the power supply high-level voltage VDD and the power supply low-level voltage VSS.
Channel MOSFET 3 'and second N-channel MOSFET
A NOR circuit 4 ′ having an output connected to the gate of the ET 3 ′.
The clock signal CK2 is supplied to one input of the OR circuit 4 ', and the output data OUT1 is supplied to the other input of the NOR circuit 4.
Is supplied. The first N-channel MOSFET 2 'and the second
A load capacitance 5 'is externally connected between a connection point with the N-channel MOSFET 3' and the power supply low level voltage VSS.

FIG. 2 is a characteristic diagram showing an example of a temporal change of the voltage state of each part in the NMOS precharge circuit 1 of the first embodiment. The vertical axis represents voltage, and the horizontal axis represents time. .

Here, the operation of the precharge circuit according to the first embodiment will be described with reference to FIGS.

First, in the operation of the NMOS precharge circuit 1, during the precharge period, the clock signal CK1 goes high (equal to the power supply voltage high level VDD), and the first N-channel MOSFET 2 turns on. When the first N-channel MOSFET 2 is turned on, the power supply voltage high level VDD changes to the first N-channel MOSFET.
2, the load capacitor 5 is precharged, and the high-level output data O based on the precharge voltage is applied to the load capacitor 5.
Generate UT1. As shown in FIG. 2, the precharge voltage of the load capacitance 5 is equal to the power supply voltage high level VDD.
From the threshold voltage (Vt) of the first N-channel MOSFET 2
hN) is obtained (VDD−VthN).
At this point, the high level of the clock signal CK1 changes to NOR.
The second N-channel MOSFET 3 is turned off because the low level of its output is applied to the gate of the second N-channel MOSFET 3.

Next, during the logic operation period, the clock signal CK1 changes from high level to low level (low power supply voltage level, that is, equal to the ground voltage VSS), and the first N-channel MOSFET 2 changes from on to off. ,
The precharge of the load capacitance 5 stops.

At this time, when the input data DATA1 is at a low level, the low level of the clock signal CK1 and the low level of the input data DATA1 are input, so that the output of the NOR circuit 4 becomes high. In addition to the gate of the second N-channel MOSFET 3, the second N-channel MOSFET 3 changes from off to on. When the second N-channel MOSFET 3 is turned on, the pre-charge voltage of the load capacitor 5 is discharged through the second N-channel MOSFET 3, and the low-level output data OUT1 equal to the ground voltage VSS is generated in the load capacitor 5.

On the other hand, when the input data DATA1 is at a high level, the output of the NOR circuit 4 goes to a low level,
Since this low level is applied to the gate of the second N-channel MOSFET 3, the second N-channel MOSFET 3 is continuously turned off. Therefore, the precharge voltage of the load capacitance 5 is not discharged, and the output signal OU
T1 is held at a high level equal to the precharge voltage.

Next, regarding the operation of the NMOS precharge circuit 1 ', a clock signal CK2 is used instead of the clock signal CK1 used in the NMOS precharge circuit 1.
The operation is the same as that of the above-described NMOS precharge circuit 1 except that the output data OUT1 is used instead of the input data DATA1. In this case, the clock signal CK2 is the same clock signal as the clock signal CK1, and its pulse width or phase is the same as or slightly different from that of the clock signal CK1. The operation is clear from the operation of the above-described NMOS precharge circuit 1, and further description will be omitted. Then, the load capacitor 5 ′ is changed from the high level of the power supply voltage VDD to the threshold voltage (VthN) of the first N-channel MOSFET 2.
Output data OUT2 whose low level is the power supply voltage low level VSS at the voltage (VDD−VthN) obtained by subtracting
Is obtained.

According to the precharge circuit of the first embodiment,
The pre-charge voltage of the load capacitors 5, 5 'is changed from the power supply voltage high level VDD to the first N-channel MOSFETs 2, 2'.
The voltage (VDD−) obtained by subtracting the threshold voltage (VthN)
VthN), the power supply voltage high level VDD
Lower voltage can be set. By setting such a low precharge voltage, the amount of discharge charge when the output data OUT1, OUT2 is changed from high level to low level can be reduced, and the NMOS precharge circuits 1, 1 'are correspondingly reduced. Operation can be speeded up.

According to the precharge circuit of the first embodiment, during the discharge operation of the output data OUT1 and OUT2, after the NOR circuit 4 takes the logic of the clock signal CK1 and the input data DATA1, the NOR circuit 4 performs the operation. 4 ', the logic of the clock signal CK2 and the output data OUT1 are taken, and then the second N-channel MOSFET
Since the single discharge is performed by T3 and 3 ', the discharge operation of the load capacitors 5 and 5' is performed at high speed.

Furthermore, according to the precharge circuit of the first embodiment, the amount of charge to be charged when the load capacitors 5 and 5 'are precharged and the amount of discharge to be discharged when the load capacitors 5' are respectively reduced. 1 'can be reduced.

By the way, in the first embodiment, the second N
The two-input NOR circuits 4, 4 'are used as the logic circuits connected to the gates of the channel MOSFETs 3, 3', but a multi-input NOR circuit or the like may be used instead of the two-input NOR circuits 4, 4 '. It is. In general, logic circuits such as the NOR circuits 4 and 4 ′ are provided with clock signals CK1 and C
K2, input data DATA1 or output data OUT
1 has a function of waveform shaping, and the output data OUT1 and OUT2 are changed by sharply changing the output data.
Can be performed at a high speed. Further, as in the first embodiment, by connecting the NMOS precharge circuits 1 and 1 'in multiple stages, it is possible to further increase the speed of the critical path and reduce the power consumption of the precharge circuit. However, when the NOR circuits 4 and 4 ′ are composed of CMOS circuits, the high level of the output data is an intermediate level between the high level and the low level of the power supply voltage. May flow.

Considering mainly the reduction of power consumption,
When the effect of reducing power consumption by reducing the amount of charge / discharge current of the output data OUT1 and OUTO2 is obtained with respect to the amount of through current of the NOR circuits 4 and 4 ', low consumption by the NMOS precharge circuits 1, 1' is achieved. Electrification is an effective means. It should be noted that in order to eliminate the amount of through current of the NOR circuits 4 and 4 ′, the NOR circuits 4 and 4 ′ are provided immediately before the NOR circuits 4 and 4 ′.
A level conversion circuit for increasing the intermediate level of the output data 4 'to the power supply voltage high level may be provided.

FIG. 3 is a circuit diagram showing a configuration of a precharge circuit according to a second embodiment of the present invention.
3 shows an example of a specific configuration of the circuit 4.

In FIG. 3, reference numeral 6 denotes a first P-channel MOS
FET, 7 is the second P-channel MOSFET, 8 is the third N-channel MOSFET
The channel MOSFET 9 is a fourth N-channel MOSFET.
T, and the same components as those shown in FIG. 1 are denoted by the same reference numerals.

Then, the NOR circuit 4 includes a first P-channel MOSFET 6, a second P-channel MOSFET 7, between the power supply voltage high level VDD and the power supply voltage low level VSS.
A third N-channel MOSFET 8 is connected in series,
4th N-channel MOSFET to channel MOSFET8
9 are connected in parallel. First P-channel MOSFET
The clock signal CK1 is supplied to the gate of the second N-channel MOSFET 9 and the gate of the fourth N-channel MOSFET 9.
Input data DATA1 is supplied to the gate of the FET 7 and the gate of the third N-channel MOSFET 8. The connection point between the second P-channel MOSFET 7 and the third N-channel MOSFET 8 is the second N-channel MOSFET of the succeeding NMOS precharge circuit 1.
It is connected to the gate of channel MOSFET3.

When the clock signal CK1 is at a high level, the NOR circuit 4 turns off the first P-channel MOSFET 6,
When the fourth N-channel MOSFET 9 is turned on, the second N-channel MOSFET
A low level is supplied to the gate of the channel MOSFET 3. When the clock signal CK1 is at a low level, the first
P-channel MOSFET 6 is on, 4th N-channel MO
SFET 9 turns off. At this time, the input data DAT
When A1 is at a low level, the second P-channel MOSFE
When T7 is turned on and the third N-channel MOSFET 8 is turned off, a high level is supplied to the gate of the second N-channel MOSFET 3. On the other hand, when the input data DATA1 is at a high level, the second P-channel MOSFET 7 is turned off and the third N-channel MOSFET 8 is turned off. Is turned on to supply a low level to the gate of the second N-channel MOSFET 3.

As described above, the NOR circuit 4 supplies a high level to the gate of the second N-channel MOSFET 3 only when both the clock signal CK1 and the input data DATA1 are at a low level, and the clock signal CK1 and the input data DATA1 output the high level. At the level other than
A low level is supplied to the gate of the channel MOSFET 3.

FIG. 4 is a circuit diagram showing the configuration of a third embodiment of the precharge circuit according to the present invention.
This shows an example in which a pre-charge circuit 10 is used in place of the R circuit 4.

In FIG. 4, reference numeral 10 denotes a pre-charge circuit, 11 denotes a third P-channel MOSFET, 12 denotes a multi-input PMOS logic circuit, and 13 denotes a fifth N-channel MOSFET.
In addition, the same components as those shown in FIG. 1 are denoted by the same reference numerals.

In the pre-charge circuit 10, a third P-channel MOSFET 11, a multi-input PMOS logic circuit 12, and a fifth N-channel MOSFET 13 are connected in series between the power supply voltage high level VDD and the power supply voltage low level VSS. The clock signal CK1 is supplied to the gate of the third P-channel MOSFET 11 and the gate of the fifth N-channel MOSFET 13, and the multi-input PMOS logic circuit 12
Are supplied with individual input data DATA. Multi-input PMOS logic circuit 12 and fifth N-channel MOSFE
The next NMOS precharge circuit 1 is connected to T13.
Is connected to the gate of the second N-channel MOSFET 3.

When the clock signal CK1 is at the high level, the pre-charge circuit 10 of the present embodiment operates the third P-channel MO
SFET 11 is off, 5th N-channel MOSFET 13
Is turned on to supply a low level to the gate of the second N-channel MOSFET 3. Also, the clock signal CK1
At the low level, the third P-channel MOSFET 11 is turned on and the fifth N-channel MOSFET 13 is turned off.
At this time, if one or more of the input data DATA are at a low level, the multi-input PMOS logic circuit 1
2 is turned on to supply a high level to the gate of the second N-channel MOSFET 3, while each input data DATA
Is high, the multi-input PMOS logic circuit 12 is turned off and the low level of the gate of the second N-channel MOSFET 3 is maintained.

The pre-charge circuit 10 of this embodiment supplies a high level to the gate of the second N-channel MOSFET 3 only when one or more of the clock signal CK1 and each input data DATA is at a low level. When the clock signal CK1 and each input data DATA are at other levels, the low level of the gate of the second N-channel MOSFET 3 is held.

According to the precharge circuit of the third embodiment,
Since the logic circuit for controlling the voltage level of the gate of the second N-channel MOSFET 3 is constituted by the pre-charge circuit 10, the number of transistors used can be reduced as compared with the case where the logic circuit is constituted by a CMOS static circuit.
The area of the circuit can be reduced, and at the same time, the internal parasitic capacitance can be reduced and the operation of the precharge circuit can be speeded up.

[0055] followed, FIG. 5 is a circuit diagram showing the configuration of a fourth embodiment of the precharge circuit according to the present invention, an example of using a plurality of the 2N channels MOSFET3 _{1, 3 2,} 3 3 Things.

In FIG. 5, 3 ₁ , 3 ₂ , and 3 ₃ are second N-channel MOSFETs, respectively, 14, 15, and 16 are multi-input logic circuits, respectively, and are otherwise the same as the components shown in FIG. Elements have the same reference numerals.

The precharge circuit according to the fourth embodiment includes a power supply voltage high level VDD and a power supply voltage low level V
The 1N channel MOSFET2 between SS, the 2N channels MOSFET 3 ₁ are connected in series, the 2N channels M
OSFET3 ₁ The 2N channel MOSFET 3 _2, 3
_Three series connection circuits are connected in parallel. In the multi-input logic circuit 14, a clock signal CK1 is supplied to a clock input, and individual input data DATA is supplied to each input.
The multi-input logic circuit 15 supplies a clock signal C to the clock input.
K1 is supplied, and individual input data DATA different from individual input data DATA supplied to the multi-input logic circuit 14 is supplied to each input. The clock signal CK1 is supplied to the clock input of the multi-input logic circuit 16, and individual input data DATA different from the individual input data DATA supplied to the multi-input logic circuits 14 and 15 is supplied to each input. The output of the multi-input logic circuit 14 is connected to the gate of the 2N channels MOSFET 3 _2, the output of the multi-input logic circuit 15 is connected to the gate of the 2N channels MOSFET 3 _3, the output of the multi-input logic circuit 16 first 2N channel MOSFET 3 Connected to _one gate. In this case, the multi-input logic circuits 14, 15, 16 are constituted by the CMOS static NOR circuit 4 and the pre-charge circuit 10 shown in FIG.

According to the precharge circuit of the fourth embodiment, the logic function realized in the precharge circuit is
Second N-channel MOS for discharging load capacitance 5
FETs 3 ₁ , 3 ₂ , 3 ₃ and each second N-channel MOSFET
T3 _1, 3 _2, 3 because be realized by the combination of multi-input logic circuits 14 to control the voltage level of the gate of _3, sharing logic functions so as not to impair the speed of operation By doing so, it is possible to realize the NMOS precharge circuit 1 that performs a complicated logical function.

FIG. 6 is a circuit diagram showing the configuration of a fifth embodiment of the precharge circuit according to the present invention.
This shows an example in which the N-channel MOSFET 2 is used only for generating a threshold voltage (VthN).

In FIG. 6, reference numeral 17 denotes a fourth P-channel MO.
The SFET 18 is a multi-input NMOS logic circuit, and the same components as those shown in FIG. 1 are denoted by the same reference numerals.

The precharge circuit according to the fifth embodiment includes a power supply voltage high level VDD and a power supply voltage low level V
A fourth P-channel MOSFET 17, a first N-channel MOSFET 2, a multi-input NMOS logic circuit 18, and a second N-channel MOSFET 3 are connected in series between the SSs. A clock signal C is applied to the gate of the fourth P-channel MOSFET 17 and the gate of the second N-channel MOSFET 3, respectively.
K1 is supplied, and the power supply voltage high level VDD is supplied to the gate of the first N-channel MOSFET2. Multi-input N
Individual input data DAT is applied to each input of MOS logic circuit 18.
A is supplied. A load capacitance 5 is connected to a connection point between the first N-channel MOSFET 2 and the multi-input NMOS logic circuit 18.

When the clock signal CK1 is at a low level, the precharge circuit of the fifth embodiment
The SFET 17 is turned on when the clock signal CK1 is supplied to the gate, and the first N-channel MOSFET 2 is turned on when the power supply voltage high level VDD is supplied to the gate. Therefore, the load capacitance 5 is switched from the power supply voltage high level VDD to the first Nth.
It is precharged to a voltage (VDD-VthN) obtained by subtracting the threshold voltage (VthN) of the channel MOSFET 2. When the clock signal CK1 is at a high level, the fourth P-channel MOSFET 17 is turned off, and the clock signal CK1 is supplied to the gate of the second N-channel MOSFET 3 and turned on. At this time, each input data DAT
When the multi-input NMOS logic circuit 18 performs a logical operation in accordance with the level of A, and the multi-input NMOS logic circuit 18 is turned on by the logical operation, the precharge voltage of the load capacitance 5 is increased by the multi-input NMOS logic circuit 18 and the second N Channel MO
Discharged through SFET3 and output data O
UT1 is changed from high level to low level, while
When the multi-input NMOS logic circuit 18 is turned off by the logic operation, the precharge voltage of the load capacitance 5 is held as it is, and the output data OUT1 maintains the high level.

According to the precharge circuit of the fifth embodiment,
The precharge period is started when the clock signal CK1 is at a low level, and the logic operation period is started when the clock signal CK1 is at a high level. Therefore, unlike the first to fourth embodiments, the level polarity of the clock signal CK1 during the precharge period is opposite. In the precharge period, a fourth P-channel MOS connected in series is connected.
The precharge operation is slightly delayed because the load capacitance 5 is precharged through the FET 17 and the first N-channel MOSFET 2. However, the precharge operation may be generally slow, so that the delay of the critical path is not affected.

Further, according to the precharge circuit of the fifth embodiment, a multi-input N
Since the MOS logic circuit 18 is connected, the load capacitance 5
The operation when the precharge voltage is discharged is slightly delayed, and the steep characteristic at the time of falling of the output data OUT1 is slightly deteriorated. However, this point does not cause much problem.

FIG. 7 is a circuit diagram showing the configuration of a sixth embodiment of the present invention.
2 shows an example in which an inverting circuit is connected to the input side of the multi-input NMOS logic circuit 18.

In FIG. 7, reference numeral 19 denotes an inverting circuit, reference numeral 20 denotes an inverting logic circuit, and the same components as those shown in FIG. 6 are denoted by the same reference numerals.

The precharge circuit according to the sixth embodiment includes a power supply voltage high level VDD and a power supply voltage low level V
1st N channel MOSFET2 between SS, multiple input NMO
The S logic circuit 18 and the second N-channel MOSFET 3 are connected in series. The clock signal CK1 is supplied to the gate of the first N-channel MOSFET 2 via the inverting circuit 19, and the clock signal CK1 is supplied to the gate of the second N-channel MOSFET 3. Multi-input NMOS logic circuit 18
Are supplied with individual input data DATA via the inversion logic circuit 20.

When the clock signal CK1 is at the low level, the precharge circuit of the sixth embodiment
Is inverted to a high level by the inverting circuit 19,
The high level turns on the first N-channel MOSFET 2 to precharge the load capacitance 5. When the clock signal CK1 is at a high level, the second N-channel MOSFE
T3 turns on. At this time, the level of each input data DATA is inverted by the inversion logic circuit 20 and applied to the multi-input NMOS logic circuit 18, where the logic operation is performed as in the above-described embodiments. Then, when the multi-input NMOS logic circuit 18 is turned on, the precharge voltage of the load capacitance 5 is changed to the multi-input NMOS logic circuit 18 and the second N-channel
Discharged through SFET3 and output data O
UT1 is changed to low level, while multi-input NMOS
When the logic circuit 18 is off, the precharge voltage of the load capacitance 5 is held, and the output data OUT1 is maintained at a high level.

In this case, the inversion logic circuit 20 can be constituted by a multi-input logic circuit. When the preceding logic circuit is precharged at a high level, the N-channel in the multi-input NMOS logic circuit 18 By turning off the MOSFET, it is possible to make a configuration in which the precharge circuits can be connected in multiple stages. Such a configuration performs the same function as an inverter arranged in a well-known domino circuit.

FIG. 8 is a circuit diagram showing a configuration of a seventh embodiment of the present invention.
1 shows an example in which a level conversion circuit is connected to the preceding stage.

In FIG. 8, reference numeral 21 denotes a level conversion circuit;
Reference numeral 2 denotes a fifth P-channel MOSFET, reference numeral 23 denotes a sixth N-channel MOSFET, and other components that are the same as those shown in FIG.

The level conversion circuit 21 includes a fifth P-channel MOSFET 22 and a sixth N-channel MOSFET 2 between the power supply voltage high level VDD and the input data DATA.
3 are connected in series. Fifth P-channel MOSFET
The connection point (output node) between the NMOS 22 and the sixth N-channel MOSFET 23 is the NOR of the next NMOS precharge circuit 1.
A fifth P-channel MOS connected to the other input of the circuit 4
The gate of the FET 22 is connected to the gate of the second N-channel MOSFET 3 of the NMOS precharge circuit 1. The power supply voltage high level VDD is supplied to the gate of the sixth N-channel MOSFET 23.

In the level conversion circuit 21 having the above configuration, when the input data DATA is at the high level, the output node is precharged via the sixth N-channel MOSFET 23, and the precharge voltage does not reach the power supply voltage high level VDD. When the fifth P-channel MOS
The FET 22 is turned on, and the output node is precharged to the power supply voltage high level VDD.

According to the precharge circuit of the seventh embodiment,
Even when the NMOS precharge circuits 1 are connected in multiple stages, the NOR circuit 4 in each NMOS precharge circuit 1
No through current flows due to the high level of the input data DATA. This level conversion circuit 21
This is effective when the MOS precharge circuit 1 is connected to a CMOS circuit.

By the way, if the level conversion circuit 21 is provided, the delay of the critical path may be deteriorated.
The driving force of the P-channel MOSFET 22 is weakened,
By increasing the driving force of the channel MOSFET 23 and reducing the parasitic capacitance of the output node, it is possible to reduce the delay deterioration. In this case, it is worth using when the effect of increasing the operation speed by setting the input data DATA to a level lower than the power supply voltage high level VDD is greater than the delay deterioration caused by using the level conversion circuit 21. is there. That is, in the precharge circuit of the seventh embodiment, by connecting the NMOS precharge circuits 1 in multiple stages, it is possible to achieve both high-speed operation and low power consumption.

FIG. 9 is an operation explanatory diagram showing an example of a voltage state during the operation of the level conversion circuit 21.

As shown in FIG. 9, the clock signal CK
1 is fixed to a low level, the input data DA
When TA is propagated to the output node via the sixth N-channel MOSFET 23, the output level of the NOR circuit 4 changes to low level, and the fifth P-channel MOSFET
ET22 is turned on, and the voltage level of the output node is raised until it becomes equal to the power supply voltage high level VDD.

FIG. 10 is a circuit diagram showing the configuration of an eighth embodiment of the present invention, in which a second level conversion circuit is connected to a stage preceding the NMOS precharge circuit 1 of the third embodiment. Things.

In FIG. 10, reference numeral 24 denotes a second level conversion circuit, 25 denotes a sixth P-channel MOSFET, and 26 denotes a 7Nth MOSFET.
Channel MOSFET, 27 is a second inverting circuit, DATA
Reference numeral 2 denotes input data output from another NMOS precharge circuit 1, and the same reference numerals are given to the same components as those shown in FIG.

Then, the second level conversion circuit 24 performs the sixth level conversion between the power supply voltage high level VDD and the input data DATA2.
P channel MOSFET 25, 7th N channel MOSF
The ET 26 is connected in series. 6th P channel MOS
A connection point (output node) between the FET 25 and the seventh N-channel MOSFET 26 is connected to one input of the multi-input PMOS logic circuit 12 of the succeeding pre-charge circuit 10. The clock signal CK1 is supplied to the gate of the sixth P-channel MOSFET 25 via the second inverting circuit 27, and the power supply voltage high level VDD is supplied to the gate of the seventh N-channel MOSFET 26. In this case, a multi-input PMOS
Each input data DATA supplied to the other inputs of the logic circuit 12 has a high level of the power supply voltage high level VD.
D and the low level is equal to the power supply voltage low level VSS.

In the second level conversion circuit 24, when the input data DATA2 is at the high level and the clock signal CK1 is at the high level, the output node is connected to the high level of the input data DATA2 through the seventh N-channel MOSFET 26 in which the input data DATA2 is on. Precharge to. At the same time, the high level of the clock signal CK1 is converted to a low level by the second inverting circuit 27 and supplied to the gate of the sixth P-channel MOSFET 25, and the sixth P-channel MOSFET 25 is turned on to change the voltage of the output node to the power supply voltage high level. VDD is increased to a value equal to VDD, and the power supply voltage high level VDD is precharged to the output node. When the precharge voltage of this output node is applied to the multi-input PMOS logic circuit 12, the multi-input PMOS logic circuit 12
P-channel MOSFET in logic circuit 12 (not shown)
Turn off.

According to the precharge circuit of the eighth embodiment,
This is a circuit in which input data DATA2 precharged through the seventh N-channel MOSFET 26 and having a high level lower than the power supply voltage high level VDD and input data DATA having a high level equal to the power supply voltage high level VDD are mixed and transmitted. However, the NMOS precharge circuit 1
Can be appropriately inserted and used.

FIG. 11 is a circuit diagram showing the configuration of a ninth embodiment of the present invention, in which an NMOS drive circuit is connected to the next stage of the NMOS precharge circuit 1.

In FIG. 11, reference numeral 28 denotes an NMOS drive circuit, 29 denotes an eighth N-channel MOSFET, and 30 denotes a ninth MOSFET.
N-channel MOSFET, 31 is the 10th N-channel MO
SFET, 32 is a seventh P-channel MOSFET, 33 is a third inverting circuit, and other components that are the same as those shown in FIG.

The NMOS drive circuit 28 includes an eighth N-channel MOSFET 29 and a ninth N-channel MOSFET 29 between the power supply voltage high level VDD and the power supply voltage low level VSS.
The OSFET 30 is connected in series, and the power supply voltage high level V
A seventh P-channel MO is provided between DD and input data OUT1.
The SFET 32 and the tenth N-channel MOSFET 31 are connected in series. Output data OUT is derived from a connection point (output node) between the eighth N-channel MOSFET 29 and the ninth N-channel MOSFET 30. Seventh P-channel MOSFET 32 and tenth N-channel MOSFET 3
The connection point 1 (intermediate node) is directly the eighth N-channel MOS
It is connected to the gate of the FET 29 and to the gate of the ninth N-channel MOSFET 30 via the third inverting circuit 33. The gate of the seventh P-channel MOSFET 32 is connected to the gate of the ninth N-channel MOSFET 30, and the power supply voltage high level VDD is supplied to the gate of the tenth N-channel MOSFET 31.

In the NMOS drive circuit 28, when the output data OUTI of the NMOS precharge circuit 1 serving as input data changes from a low level to a high level by the precharge operation of the NMOS precharge circuit 1, the intermediate node is turned on. A certain 10N channel MO
The signal changes from a low level to a high level via the SFET 31. When the intermediate node goes to a high level, the high level is converted to a low level by the third inverting circuit 33, and then supplied to the gate of the seventh P-channel MOSFET 32 to turn on the seventh P-channel MOSFET 32,
The high level of the intermediate node is raised to the power supply voltage high level VDD. At this time, the high level of the intermediate node is connected to the gate of the eighth N-channel MOSFET 29, and the low level of the output of the third inverting circuit 33 is set to the ninth N-channel MOSFET.
Is supplied to the gate of T30, and the eighth N-channel MOSFET
T29 is turned on, the ninth N-channel MOSFET 30 is turned off, and the output node is precharged. In this case, the precharge voltage of the output node is a voltage (VDD-Vth) obtained by subtracting the threshold voltage (VthN) of the eighth N-channel MOSFET 29 from the power supply voltage high level VDD.
N), and the high level of the output data OUT also becomes the same voltage (VDD-VthN).

When the output data OUT1 changes from the high level to the low level, the output data OUT1 and the level of the intermediate node are both at the power supply voltage low level VSS, that is,
It drops to the ground voltage. At this time, the 8th N-channel MO
The SFET 29 is turned off, and the ninth N-channel MOSFE
T30 is turned on to discharge the precharge voltage of the output node and output data OUT to the voltage (VD
D-VthN) to the ground voltage.

According to the precharge circuit of the ninth embodiment,
In the case where the NMOS precharge circuit 1 is connected in multiple stages, if the preceding stage is constituted by the NMOS precharge circuit 1, even if the subsequent stage is constituted by the NMOS drive circuit 28 which does not require the clock signal CK1, the NMO is not required.
A function equivalent to a high-speed operation and low power consumption achieved when the S precharge circuits 1 are connected in multiple stages is achieved.

More specifically, this point is described in NMO
When the S precharge circuit 1 performs the precharge operation, the successively connected NMOS drive circuit 28 also performs the charge operation of the output node, and the high level of the output data OUT changes from the power supply voltage high level VDD to the eighth N-channel MOSFET 29. (Vth-VthN) minus the threshold voltage (VthN). On the other hand, when the output data OUT1 of the NMOS precharge circuit 1 changes to the low level, the output data O of the NMOS drive circuit 28 becomes low.
The UT changes to a low level equal to the power supply voltage low level VSS. As described above, the output data OUT of the NMOS drive circuit 28 both changes to the high level and changes to the low level depending on the change of the output data OUT1 of the preceding NMOS precharge circuit 1. Therefore, when considering the clock signal CK1 supplied to the NMOS precharge circuit 1, the charging operation when the output data OUT changes to the high level is slightly delayed. It does not affect the critical path delay and does not cause much problem. In addition, the discharge operation when the output data OUT changes to low level does not cause a noticeable delay as compared with the case where the NMOS precharge circuits 1 are connected in multiple stages.

Further, according to the precharge circuit of the ninth embodiment, the clock signal CK is supplied to the NMOS drive circuit 28 connected to the second and subsequent stages of the NMOS precharge circuit 1.
1 need not be supplied, and the clock signal supply circuit system can be simplified.

FIG. 12 is a circuit diagram showing the configuration of the tenth embodiment of the present invention, in which a non-inverting circuit of a CMOS static circuit is connected to the next stage of the NMOS precharge circuit 1. It is.

In FIG. 12, reference numeral 34 denotes a non-inverting circuit;
Is a fourth inverting circuit, 36 is a fifth inverting circuit, and
The same components as those shown in FIG. 1 are denoted by the same reference numerals.

The non-inverting circuit 34 is composed of a cascade-connected fourth inverting circuit 35 and a fifth inverting circuit 36, and the output data OUT1 of the NMOS precharge circuit 1 is supplied to the input of the fourth inverting circuit 35. , The output data OUT is derived from the output of the fifth inversion circuit 36.

According to the precharge circuit of the tenth embodiment, the NMOS precharge circuit 1 changes the high level of the output data OUT1 from the power supply voltage high level VDD to the threshold voltage (VthN) of the first N-channel MOSFET 2 during the precharge period. ) Is subtracted (VDD−Vth)
N), a through current flows through the non-inverting circuit 34. When the output data OUT1 changes to low level during the logic operation period, the NMOS precharge circuit 1 also changes the output data OUT of the non-inverting circuit 34 from high level to low level. To be driven. At this time, the P-channel MOSFET in the fourth inverting circuit 35 in the non-inverting circuit 34 is in an operating state, but the load driven by this P-channel MOSFET is only the input of the fifth inverting circuit 36 in the next stage. The effect of causing the critical path delay is small. As described above, the precharge circuit of the tenth embodiment does not require a strict design for power consumption, and can achieve high-speed operation by using a simple circuit configuration.

FIG. 13 is a circuit diagram showing a configuration of a precharge circuit according to an eleventh embodiment of the present invention.
This shows an example in which a second NMOS drive circuit is connected to the next stage of the PMOS precharge circuit instead of the OS precharge circuit.

In FIG. 13, 1P is a PMOS precharge circuit, 37 is a second NMOS drive circuit, 38 is an 11th N-channel MOSFET, 39 is a 12th N-channel MOSFET, 40 is a sixth inverting circuit, and others are shown in FIG. The same components as those described above are denoted by the same reference numerals.

Then, the PMOS precharge circuit 1P
Is a configuration in which the first N-channel MOSFET 2 is omitted from the NMO precharge circuit 1 of the fifth embodiment shown in FIG. 6, and the other configuration is the same as that of the NMO precharge circuit 1 of the fifth embodiment. . The second NMOS drive circuit 37 is connected between the power supply voltage high level VDD and the power supply voltage low level VSS.
Eighth, the twelfth N-channel MOSFET 39 is connected in series, and output data OUT is output from a connection point (output node) between the eleventh N-channel MOSFET 38 and the twelfth N-channel MOSFET 39. 11th N channel MOSF
The output data OUT1 of the preceding PMOS precharge circuit 1P is supplied to the gate of the ET38, and the output data OUT of the PMOS precharge circuit 1P is supplied to the gate of the twelfth N-channel MOSFET 39 via the sixth inverting circuit 40.
1 is supplied.

The precharge circuit of the eleventh embodiment has a PM
In the OS precharge circuit 1P, the clock signal CK
When 1 is at low level, the fourth P-channel MOSFET
17 is turned on to perform a precharge operation, the load capacitance 5 is precharged to a voltage equal to the power supply voltage high level VDD, and the output data OUT1 becomes high level. on the other hand,
When the clock signal CK1 is at a high level, the second N-channel MOSFET 3 is turned on, and when the multi-input NMOS logic circuit 18 is turned on by the level state of each input data applied to each input of the multi-input NMOS logic circuit 18, the load capacitance 5 Of the multi-input NMOS logic circuit 18
And the data is discharged via the second N-channel MOSFET 3, and the output data OUT1 becomes low level. In the NMOS drive circuit 37, when the input output data OUT1 is at the high level, the eleventh N-channel MOSFET 38 is turned on by the supply of the high level, and the twelfth N-channel MOSFET 39 outputs the high-level output data OUT1 with the sixth inversion circuit. The output node is turned off because it is inverted and supplied as a low level at 40, and the output node changes from the power supply voltage high level VDD to the 11th Nth channel M
It is charged to a voltage (VDD-VthN) obtained by subtracting the threshold voltage (VthN) of the OSFET 38. on the other hand,
When the output data OUT1 is at the low level, the eleventh N-channel MOSFET 38 is turned off by the supply of the low level, and the twelfth N-channel MOSFET 39 is inverted at the low-level output data OUT1 by the sixth inverting circuit 40 and supplied as the high level. Therefore, the output node is turned on, and the output node drops to the ground voltage equal to the power supply voltage low level VSS. For this reason, the output data OUT changes from the power supply voltage high level VDD to the 11th N-th channel M
At a voltage (VDD-VthN) obtained by subtracting the threshold voltage (VthN) of the OSFET 38, the low level becomes the power supply voltage low level VSS.

According to the precharge circuit of the eleventh embodiment, when the load capacitance 5 is relatively light, the P-channel MOS
When the load capacitance 5 is charged to a high level by the FET 17 and the load capacitance is relatively heavy, an N-channel MOS
By charging the load capacitance to a high level by the FET 38, the delay overhead due to the use of the level conversion circuit can be reduced.

FIG. 14 is a configuration diagram showing an embodiment in which a large-scale semiconductor integrated circuit (LSI) is configured using the precharge circuit of the present invention.

In FIG. 14, reference numeral 41 denotes an LSI chip, 4
2 is a first logical block, 43 is a second logical block, 44
Is a third logic block, 45 is a first driver circuit, 46 is a second driver circuit, 47 is a first receiver circuit, 48 is a second receiver circuit, 49 is a first relay buffer circuit, 50 is a second relay buffer circuit, Reference numeral 51 denotes a wiring path.

The LSI chip 41 includes therein a first logic block 42, a second logic block 43, a third logic block 44, a first relay buffer circuit 49, and a second relay buffer circuit 50. . The first logic block 42 contains a first driver circuit 45, the second logic block 43 contains a second driver circuit 46, and the third logic block 44 contains a first receiver circuit 47 and a second receiver circuit 48. ing. The output of the first driver circuit 45 and the input of the first receiver circuit 47 are connected by a wiring path 51, and between the output of the second driver circuit 46 and the input of the second receiver circuit 48 are two first The relay buffer circuit 49 and the second relay buffer circuit 50 are connected via a wiring path 51. In this case, the first driver circuit 45, the second driver circuit 46, the first receiver circuit 4
7, second receiver circuit 48, first relay buffer circuit 4
9. The precharge circuit according to the present invention is incorporated in all of the second relay buffer circuits 50.

The output data derived from each wiring path 51, that is, the output data of the first driver circuit 45,
The output data of the driver circuit 46, the output data of the first relay buffer circuit 49, and the output data of the second relay buffer circuit 50 all have a high level of the power supply voltage high level VD.
D to N-channel MOSFET threshold voltage (Vth
N) is set to be a voltage (VDD-VthN) obtained by subtracting (N).

According to this embodiment, when driving a long-distance wiring path such as the wiring path 51 connecting the respective logic blocks 42, 43, and 44 arranged in the LSI chip 41, the operation is speeded up and the power consumption is reduced. Electricity can be realized.

[0105]

As described above, according to the present invention, the first N channel M depends on one polarity of the supplied clock signal.
During the precharge period when the OSFET is turned on, the first
The first circuit including the N-channel MOSFET operates to precharge the load to a high level, and during the logic operation period, the second circuit including the second N-channel MOSFET includes a combination of the other polarity of the clock signal and each polarity of the data signal. The circuit is activated or deactivated, and the high level of the load is changed to a low level or switched so as to maintain the high level. The precharge voltage of the load is changed from the high level of the power supply to the first N-channel MOSFET. Since the load is lowered by the threshold voltage, the load discharge operation can be speeded up by the low threshold voltage. When the signal amplitude of the load is reduced by the low threshold voltage, the amount of charge for precharging and discharging the load is reduced, so that there is an effect that power consumption can be reduced.

According to the present invention, when the second circuit including the second N-channel MOSFET operates during the logic operation period, the precharge voltage of the load is changed to the second N-channel MOSFET.
Since the discharge is performed to the power supply low level side (ground point) via the OSFET, even if a simple circuit configuration is used, the discharge can be performed quickly and an inexpensive pre-charge circuit having a good data signal delay characteristic can be obtained. There is an effect that a charge circuit can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a first embodiment of a precharge circuit according to the present invention.

FIG. 2 is a characteristic diagram showing an example of a time change of a voltage state of each unit in the NMOS precharge circuit 1 of the first embodiment.

FIG. 3 is a circuit diagram showing a configuration of a second embodiment of the precharge circuit according to the present invention.

FIG. 4 is a circuit diagram showing a configuration of a third embodiment of the precharge circuit according to the present invention.

FIG. 5 is a circuit diagram showing a configuration of a fourth embodiment of the precharge circuit according to the present invention.

FIG. 6 is a circuit diagram showing a configuration of a fifth embodiment of the precharge circuit according to the present invention.

FIG. 7 is a circuit diagram showing a configuration of a sixth embodiment of the precharge circuit according to the present invention.

FIG. 8 is a circuit diagram showing a configuration of a seventh embodiment of the precharge circuit according to the present invention.

FIG. 9 is an operation explanatory diagram showing an example of a voltage state during operation in the level conversion circuit of the seventh embodiment.

FIG. 10 is a circuit diagram showing a configuration of an eighth embodiment of the precharge circuit according to the present invention.

FIG. 11 is a circuit diagram showing a configuration of a ninth embodiment of a precharge circuit according to the present invention.

FIG. 12 is a circuit diagram showing a configuration of a tenth embodiment of a precharge circuit according to the present invention.

FIG. 13 is a circuit diagram showing a configuration of an eleventh embodiment of a precharge circuit according to the present invention.

FIG. 14 is a main part configuration diagram showing an embodiment in which a large-scale semiconductor integrated circuit (LSI) is configured using the precharge circuit of the present invention.

[Explanation of symbols]

1, 1 ′ NMOS precharge circuit 1P PMOS precharge circuit 2, 2 ′ 1st N-channel MOSFET 3, 3 ′, 3 ₁ , 3 ₂ , 3 ₃ 2nd N-channel MOSF
ET 4, 4 'NOR circuit (logic circuit) 5, 5' Load capacitance 6 First P-channel MOSFET 7 Second P-channel MOSFET 8 Third N-channel MOSFET 9 Fourth N-channel MOSFET 10 Pre-charge circuit 11 Third P-channel MOSFET 12 Many Input PMOS logic circuit 13 Fifth N-channel MOSFET 14, 15, 16 Multi-input logic circuit 17 Fourth P-channel MOSFET 18 Multi-input NMOS logic circuit 19 Inverting circuit 20 Inverting logic circuit 21 Level conversion circuit 22 Fifth P-channel MOSFET 23 Sixth N-channel MOSFET 24 second level conversion circuit 25 sixth P-channel MOSFET 26 seventh N-channel MOSFET 27 second inverting circuit 28 NMOS drive circuit 29 eighth N-channel MOSFET 30 ninth N-channel MO SFET 31 10th N-channel MOSFET 32 7th P-channel MOSFET 33 3rd inversion circuit 34 non-inversion circuit 35 4th inversion circuit 36 5th inversion circuit 37 2nd NMOS drive circuit 38 11th N-channel MOSFET 39 12th N-channel MOSFET 40 6th inversion circuit 41 LSI chip 42 First logic block 43 Second logic block 44 Third logic block 45 First driver circuit 46 Second driver circuit 47 First receiver circuit 48 Second receiver circuit 49 First relay buffer circuit 50 Second relay buffer circuit 51 Wiring path CK1, CK2 Clock signal DATA, DATA1, DATA2 Input data OUT, OUT1, OUT2 Output data VDD Power supply high level voltage VSS Power supply low level voltage

Continuing from the front page (72) Inventor Ryo Yamagata 1 Horiyamashita, Hadano-shi, Kanagawa Pref. General-purpose computer division of Hitachi, Ltd. General-purpose computer division

Claims (9)

[Claims] 1. A clock signal and data are inputted, a precharge period for precharging a load when one polarity of the clock signal arrives, and a logic operation corresponding to the data when the other polarity of the clock signal arrives. In the precharge circuit in which the logic operation period is executed alternately,
A first circuit connected between a power supply high-level terminal and the load and including at least one first N-channel MOSFET, connected between the load and the power supply low-level terminal;
A second circuit including at least one second N-channel MOSFET; and a logic circuit selectively connected to the clock signal and the data connected to the second N-channel MOSFET. The circuit operates, the load is precharged to a high level, and during the logic operation period, the combination of the clock signal and the data activates or deactivates the second circuit, thereby changing the high level of the load. A precharge circuit that is switched to change to a low level or to maintain a high level. 2. The logic circuit according to claim 1, wherein said logic circuit is a precharge logic circuit for precharging a load of said logic circuit. When the load is precharged to a high level during said precharge period, an output load of said precharge logic circuit is provided. 2. The precharge circuit according to claim 1, wherein the precharge circuit operates so as to precharge to a low level. 3. The precharge type logic circuit is a multi-input logic circuit, wherein different data is input to each input of the multi-input logic circuit.
3. The precharge circuit according to 1. 4. The logic circuit includes a plurality of multi-input logic circuits, wherein different data are input to respective inputs of the plurality of multi-input logic circuits, and the second circuit includes a plurality of the multi-input logic circuits. A plurality of second N-channel MOSFETs each having an input connected to a corresponding output of the logic circuit, wherein the plurality of second N-channel MOSFETs are:
2. The precharge circuit according to claim 1, wherein the precharge circuit is connected between the load and the low-level terminal of the power supply alone or in series with another second N-channel MOSFET. 3. 5. The first circuit includes: a first N-channel MOSFET supplied with a power supply voltage at an input terminal; and a P-channel MOSFET supplied with the clock signal at an input terminal connected in series to the first N-channel MOSFET. The precharge circuit according to claim 1, wherein: 6. The second circuit comprises the second N-channel MOSFET to which the clock signal is supplied to an input terminal, and the logic circuit receives a different data signal at each input, and the second N-channel MOSFET 6. The precharge circuit according to claim 5, comprising a multi-input NMOS logic circuit connected in series to the NMOS transistor. 7. The precharge circuit according to claim 1, wherein said data is supplied through a level conversion circuit which makes its high level equal to the voltage of said power supply high level terminal. 8. An NMO for driving a next stage load to the load
An S drive circuit is connected, and the NMOS drive circuit includes a third N-channel MOSFET for precharging the next-stage load and a fourth N-channel MOSFET for discharging the next-stage load. 8. The load of the next stage is precharged via the third N-channel MOSFET, and the load of the next stage is discharged via the fourth N-channel MOSFET during a discharge period of the load. 3. The precharge circuit according to 1. 9. A plurality of logic blocks including the precharge circuit according to claim 1 are arranged in a large-scale integrated circuit chip, and a signal interface in each of the logic blocks has a high level of a power supply high level. CMO equal to
A semiconductor integrated circuit device using an S-level data signal, wherein the signal interface between the logic blocks uses a data signal in which a high level is the power supply high level precharged through a first N-channel MOSFET.