JPH11354544A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device with a multi-stage recess structure and its manufacturing method, along with good recess width and recess depth under control. SOLUTION: A first recess etching stopper layer 5 is formed on a conductive compound semiconductor layer, and a first semiconductor layer 6 is formed on the first recess etching stopper layer 5. A second recess etching stopper layer 7 is formed on the first semiconductor layer 6. A second semiconductor layer 8 is formed on the second recess etching stopper layer 7. In this case, an etching solution made of citric acid solution and hydrogen peroxide solution is used as an anisotropic etching solution for the first and second semiconductor layers 6 and 8.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compound semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a multi-stage recess structure and a method of manufacturing the same.

[0002]

2. Description of the Related Art Improvement of gate breakdown voltage, reduction of source resistance,
HJ to suppress short channel effect and surface effect
In order to realize an LDD structure with an FET, it is necessary to form a multi-stage recess structure.
It was done individually at the time of the meeting. Also, Japanese Patent Application Laid-Open No. 4-1
As disclosed in Japanese Patent No. 37737, by selectively side-etching the mask using a multilayer mask, the controllability in the lateral direction is improved to realize a two-step recess structure.

[0003]

However, when the two-step recess is performed by two times of alignment, misalignment becomes a problem, and it has been difficult to control or shorten the distance between the gate and the n ⁺ region. Further, even if the controllability in the lateral direction is improved by using a multilayer mask as disclosed in Japanese Patent Application Laid-Open No. 4-137737, the etching is also performed in the lateral direction at the time of the recess etching, so that the gate length can be reduced and the recess can be reduced. There was a problem with the controllability of the width.

Further, when considering the depth direction at the time of recess etching, the recess depth of the first step and the recess depth of the second step are time-controlled, and there is a problem in reproducibility and controllability. There was a problem of getting worse.

An object of the present invention is to provide a semiconductor device capable of manufacturing a recess width and a recess depth with good controllability and a method of manufacturing the same.

[0006]

In order to achieve the above object, a semiconductor device according to the present invention is a semiconductor device having a semiconductor multi-layer structure, wherein the semiconductor multi-layer structure has a first structure on a conductive layer of a compound semiconductor. Providing a recess etching stopper layer; providing a first semiconductor layer on the recess etching stopper; providing a second recess etching stopper layer on the first semiconductor layer; In this case, two semiconductor layers are provided.

[0007] Further, GaAs, InAs, Al _x Ga _{1 -x} As (0 ≦ x <
1), Al _y In _1-y As (0 ≦ y <1), InP, Ga
P and a compound semiconductor composed of these compounds.

In addition, as the first and second etching stopper layers, AlAs or Al _z Ga _{1 -z} As having an Al composition higher than the composition of Al _x Ga _{1 -x} As (0 <z ≦
1) Al _w In having an Al composition higher than that of Al _y In _1-y As
_1-w As (0 <w ≦ 1) is used.

A semiconductor device formed on a (100) substrate, wherein a gate provided in the semiconductor multilayer structure is
Parallel to (011), the recess etching surface is (1
(00) plane and (111) plane.

Further, a method of manufacturing a semiconductor device according to the present invention is directed to a semiconductor multi-layer structure including a mask forming step, a patterning step, a first anisotropic etching step, and a second anisotropic etching step. A method of manufacturing a semiconductor device, comprising: a semiconductor multilayer structure, comprising: a first recess etching stopper layer provided on a conductive layer of a compound semiconductor; and a first semiconductor layer provided on the first recess etching stopper. A second recess etching stopper layer provided on the first semiconductor layer, and a second semiconductor layer provided on the second recess etching stopper layer. The first mask layer and the second mask layer having different etching rates are provided on the structure. The patterning step includes patterning the second mask layer. The first anisotropic etching step is a process of patterning a first mask layer using the first and second mask layers. In the second anisotropic etching step, the recess etching stopper layer in the opening is removed, and the opening width of the first mask layer is selectively etched by side etching. Then, the second semiconductor layer and the first semiconductor layer are subjected to anisotropic etching up to the first and second recess etching stopper layers.

Further, as the etching solution for anisotropically etching the first and second semiconductor layers, an etching solution comprising a mixed solution of a citric acid aqueous solution and a hydrogen peroxide solution is used.

[0012]

A first mask layer 9 and a second mask layer 10 having different etching rates are provided on a semiconductor multilayer structure (FIG. 1).
(B)) The second mask layer 10 is patterned, and the first mask layer 9 is patterned using the patterned second mask layer 10. This first and second
The second semiconductor layer 8 is anisotropically etched to the second recess etching stopper layer 7 using the mask layers 9 and 10 of FIG.

When performing anisotropic etching to the second recess etching stopper layer 7, an etching solution comprising a mixed solution of a citric acid aqueous solution and a hydrogen peroxide solution is used. A citric acid-based etchant is formed by mixing a semiconductor layer such as GaAs with AlA
Not only is it possible to selectively etch the stopper layer such as s, but also the etching rate of the (111) B plane can be kept extremely low. Side etching hardly occurs and is determined by (111) B, and etching in the depth direction determined by the stopper layer 7 becomes possible.

By using the above-described etching method, the depth and opening width of the first step are determined by the size of the second mask layer 2 and the position of the stopper layer 7, and hardly depend on the etching time.

Furthermore, by taking the gate parallel to (011), the shape of the opening is limited by the (111) B plane, so that the size of the second-stage opening can be smaller than the size of the second mask layer 9. It is possible (FIG. 2 (e)).

After that, the recess etching stopper layer 7 at the opening is removed, and the opening width of the first mask layer 9 is selectively widened by side etching, and then the first and second recess etching stopper layers 5 and 5 are formed. 7, the second semiconductor layer 8 and the first semiconductor layer 6 are again subjected to anisotropic etching with a citric acid-based etchant (FIG. 3).
(I)).

At this time, since only the opening of the second semiconductor layer 8 is shaved by the presence of the stopper layer 7, a two-step recessed shape can be easily formed. The opening width of the second stage is already determined by the recess width of the first stage.
The width of the opening narrowed by the recess etching of the first stage by taking parallel to 1) is further reduced by the etching of the second stage.

The carrier concentration of the first semiconductor layer is set lower than the carrier concentration of the second semiconductor layer, the gate electrode and the first semiconductor layer are short-circuited, and the distance between the gate electrode and the second high-concentration semiconductor layer is increased. Thus, a high drain withstand voltage can be obtained while avoiding the influence of the surface such as the gate lag. Moreover, it can be easily manufactured in a self-aligned manner. Horizontal 2
The width of the recess at the first stage is the width of the first mask opening,
And the depth of the stopper layer also in the etching depth direction. The width of the first recess can be controlled by the amount of side etching of the first mask layer, and its depth is determined by the stopper layer. Therefore, controllability, uniformity, and reproducibility of the threshold voltage Vt are improved. Further, when the gate is taken parallel to (011), the channel can be shortened from the mask dimension by an amount controlled by the thickness of the first and second semiconductor layers, which leads to an improvement in device characteristics.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 1 to 3 taking a heterojunction field effect transistor as an example.

As shown in FIG. 1A, semi-insulating GaAs
An i-GaAs buffer layer 2 having a thickness of 500 nm and a channel layer
15 nm i-InGaAs layer, n-AlGaAs
The s layer 4 is provided at 2 × 10 ¹⁸ cm ⁻³ at 33 nm, and the n-AlAs layer 2 is formed as the first recess etching stopper layer 5.
2 × 10 ¹⁸ cm ⁻³ , and a low concentration n-GaAs as the first semiconductor layer 6 on the recess etching stopper layer 5.
An s layer is provided at 1 × 10 ¹⁸ cm ⁻³ and 150 nm. And n
An n-AlAs layer as a second recess etching stopper layer 7 on the GaAs layer 6 at 2 × 10 ¹⁸ cm ^-3 at 2 nm;
And a second recess etching stopper layer 7
4 × 10 ¹⁸ high-concentration n-GaAs layer as the semiconductor layer 8
By providing 50 nm at cm ^-3 , the semiconductor multilayer structure of the present invention is manufactured.

A method of manufacturing a semiconductor device according to the present invention will be described using this compound semiconductor multilayer structure. An SiO ₂ layer having a thickness of 50 nm is formed as a first mask layer 9 having a different etching rate on the semiconductor multilayer structure, and a photoresist is provided as a second mask layer 10 (FIG. 1B).

Next, the photoresist as the second mask layer 10 is patterned (FIG. 1C), and the first mask layer 9 is formed using the patterned second mask layer 10.
Performing patterning of SiO ₂ (FIG. 1 (d)).

Using the first and second mask layers 9 and 10, the n-GaAs layer of the second semiconductor layer 8 is anisotropically etched to AlAs as the second recess etching stopper layer 7. The etching is performed using an etching solution composed of a mixture of a citric acid aqueous solution in which citric acid-hydrate is dissolved in water of the same weight and a 30% hydrogen peroxide solution at a ratio of 3: 1 as the etching solution ( FIG.
(E)).

Thereafter, the AlAs layer of the recess etching stopper layer 7 at the opening is removed, and the opening width of SiO ₂ as the first mask layer 9 is selectively etched by using buffered hydrofluoric acid in the lateral direction. Spread, AlA of first and second recess etching stopper layers 5 and 7
Anisotropic etching of the n-GaAs layer as the second semiconductor layer 8 and the n-GaAs layer 6 as the first semiconductor layer 6 up to the s layer is performed again with a citric acid-based etchant (FIG. 2).
(F), (g), (h)).

Further, after the portions of the etching stopper layers 5 and 7 exposed on the surface of the AlAs layer are removed with dilute hydrochloric acid (FIG. 3 (i)), the gate metal is removed using a photoresist as the first mask layer 9. Then, Ti / Pt / Au is deposited, and a gate electrode 11 is formed by a lift-off method (FIGS. 3 (j) and 3 (k)). The semiconductor device is completed by forming an ohmic electrode 12 having a normal size.

The citric acid-based etchant is composed of GaAs and a
In addition to being able to selectively etch lGaAs, at low temperatures,
The etching rate of the (111) B plane can be extremely suppressed. Specifically, the opening width and depth of the first step of the recess etching are determined by the opening size after the side etching of the first mask layer and the position of the stopper layer, and the opening width and the depth of the second step are: It is determined by the opening size of the first mask layer before the side etching and the position of the stopper layer. For this reason, the etching is determined in the lateral direction by the (111) B plane defined by the mask, and almost no side etching is caused. In the depth direction, the etching depth is determined by the stopper layer. Devices can be fabricated with little dependence.

Since the opening shape is rate-determined in the lateral direction by the (111) B plane, the width of the bottom of the recess etching is made larger than the initial mask opening width by taking the gate parallel to (011). It becomes thinner accordingly.

In the case of the present invention, the opening width narrowed by the first recess etching from the opening width of the second mask layer before the first side etching is further reduced by the AlGaAs opening of the electron supply layer by the second etching. Part becomes thinner.

As a result, the channel length can be easily reduced, and the device characteristics can be improved. In the case of the present embodiment, when the initial opening width of the second mask layer is 0.5 μm, the gate is shortened by an amount inclined by 0.14 μm from the side, so that a gate of 0.22 μm is manufactured.

In the semiconductor device manufactured in this manner, the gate electrode 11 and the low-concentration first semiconductor layer 6 can be short-circuited or the distance can be reduced with good controllability. it can.

Since the distance between the gate electrode 11 and the high-concentration second semiconductor layer 8 depends on the width of the opening and the layer thickness of the first mask layer by selective etching, the distance can be formed in a self-aligned manner.
The distance can be easily controlled, and the source resistance can be reduced while maintaining a high drain withstand voltage by designing the distance and concentration to the second semiconductor layer 8.

In the step of forming the recess, the lateral etching accuracy is improved because side etching is not performed, and the depth is determined by the stopper layer also in the etching depth direction.
Controllability, uniformity, and reproducibility of the threshold voltage Vt are also improved. Since the process is a wet process, the apparatus is simple and the cost is improved.

In the embodiment of the present invention, AlAs is used as the stopper layer. However, AlGaAs having a composition within a range that can obtain an etching selectivity with GaAs may be used. In this embodiment, the composition of the etchant is also 3: 1. However, the composition is not limited to this as long as the selectivity and the anisotropy can be obtained, and ammonium citrate or the like may be added as a buffer solution. Although the photoresist and SiO ₂ are used as the mask layer, a selectively etchable mask material such as SiO ₂ and SiON may be used. This embodiment is also applicable to a material system of AlGaAs / InGaAs / GaAs.
Although the s type is taken as an example, the present invention can be applied to an AlInAs / GaInAs type, an AlInAs / InGaAs / InGaP type, and the like.

[0034]

As described above, according to the present invention, the lateral direction is determined by the (111) B plane defined by the mask,
Since etching can be performed with almost no side etching, and the etching depth is determined by the stopper layer in the depth direction, a device can be manufactured almost independently of the etching time. Therefore, the threshold voltage Vt
Controllability, uniformity, and reproducibility can also be improved. Further, since the process is a wet process, the apparatus is simple and the cost can be improved.

As for device characteristics, in the semiconductor device, the gate electrode and the low-concentration semiconductor layer can be short-circuited or the distance can be reduced with good controllability, so that the influence of the surface such as gate lag can be avoided.

The distance between the gate electrode and the high-concentration semiconductor layer depends on the width and thickness of the mask layer, and a two-step recess can be easily formed in a self-aligned manner with good controllability. In addition, the source resistance can be reduced.

Further, by taking the gate in the (011) direction, the gate can be easily shortened, so that the device characteristics can be improved.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention in the order of manufacturing steps.

FIG. 2 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of manufacturing steps.

FIG. 3 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of manufacturing steps.

FIG. 4 is a cross-sectional view showing a conventional manufacturing method in the order of manufacturing steps.

[Explanation of symbols]

 Reference Signs List 1 substrate 2 buffer layer 3 channel layer 4 hetero barrier layer 5 first recess etching stopper layer 6 first semiconductor layer 7 second recess etching stopper layer 8 second semiconductor layer 9 first mask layer 10 second mask Layer 11 Gate electrode 12 Ohmic electrode

Claims (6)

[Claims] 1. A semiconductor device having a semiconductor multilayer structure formed on a (100) substrate, wherein the semiconductor multilayer structure includes a first recess etching stopper layer provided on a conductive layer of a compound semiconductor; A first semiconductor layer is provided on the stopper, a second recess etching stopper layer is provided on the first semiconductor layer, and a second semiconductor layer is provided on the second recess etching stopper layer. The semiconductor multi-layer structure has a two-step recess shape with the (111) B plane of the first semiconductor layer and the second semiconductor layer as side surfaces. The contacting gate electrode is (011)
A semiconductor device which is mounted on the first semiconductor layer along a direction and with a gap from the second semiconductor layer. 2. The method according to claim 1, wherein the first and second semiconductor layers are:
GaAs, InAs, Al _x Ga _{1 -x} As (0 ≦ x <
1), Al _y In _1-y As (0 ≦ y <1), InP, Ga
2. The semiconductor device according to claim 1, wherein P and a compound semiconductor composed of these compounds are used. Wherein the first and second etching stopper layer, AlAs or Al _x Ga _1-x higher Al composition than the composition of _{As Al z Ga 1-z As} (0 <z ≦ 1),,
Al _w In _1-w As having an Al composition higher than A _y In _1-y As
3. The semiconductor device according to claim 1, wherein (0 <w ≦ 1) is used. 4. A semiconductor multilayer structure having a two-stage recess on a (100) substrate, comprising a mask forming step, a patterning step, a first anisotropic etching step, and a second anisotropic etching step. A method for manufacturing a semiconductor device, comprising: a first recess etching stopper layer provided on a conductive layer of a compound semiconductor;
A first semiconductor layer provided on the recess etching stopper, a second recess etching stopper layer provided on the first semiconductor layer, and a second semiconductor provided on the second recess etching stopper layer. The mask forming step is a step of providing a first mask layer and a second mask layer having different etching rates on the semiconductor multilayer structure, and the patterning step is to form the second mask layer by (011 Patterning into a gate shape parallel to
This is a process of patterning the first mask layer by using this, and the first anisotropic etching step is to perform the second recess etching of the second semiconductor layer using the first and second mask layers. The second anisotropic etching step removes the recessed etching stopper layer at the opening, and further removes the first mask layer. Is selectively widened by side etching, and then the second semiconductor layer and the first semiconductor layer are anisotropically shaped so that the side surfaces are (111) B planes up to the first and second recess etching stopper layers. A method for performing semiconductor etching. 5. Following the second anisotropic etching step, the exposed portions of the surfaces of the first and second etching stopper layers are removed, and the compound is self-aligned using the second mask layer. 5. The method of manufacturing a semiconductor device according to claim 4, further comprising a step of forming a gate electrode connected to a semiconductor conductive layer and having a gap with said second semiconductor layer. 6. The method according to claim 1, wherein in the step of anisotropically etching the first or second semiconductor layer, an etching solution comprising a mixture of a citric acid aqueous solution and a hydrogen peroxide solution is used as an etching solution. 6. The etching according to claim 4, wherein the first or second semiconductor layer can be selectively etched with respect to the stopper layer, and the etching is performed under such a condition that the etching rate of the (111) B plane is reduced. 13. The method for manufacturing a semiconductor device according to item 5.