JPH11353497A - グラフィックスメモリシステム - Google Patents

グラフィックスメモリシステム

Info

Publication number
JPH11353497A
JPH11353497A JP11052283A JP5228399A JPH11353497A JP H11353497 A JPH11353497 A JP H11353497A JP 11052283 A JP11052283 A JP 11052283A JP 5228399 A JP5228399 A JP 5228399A JP H11353497 A JPH11353497 A JP H11353497A
Authority
JP
Japan
Prior art keywords
memory
pixel
coordinate
controller
color
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11052283A
Other languages
English (en)
Japanese (ja)
Other versions
JPH11353497A5 (enExample
Inventor
W Reynolds Gerald
ジェラルド・ダブリュー・レイノルズ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of JPH11353497A publication Critical patent/JPH11353497A/ja
Publication of JPH11353497A5 publication Critical patent/JPH11353497A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/00—3D [Three Dimensional] image rendering
    • G06T15/10—Geometric effects
    • G06T15/40—Hidden part removal
    • G06T15/405—Hidden part removal using Z-buffer

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Geometry (AREA)
  • Computer Graphics (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Image Generation (AREA)
JP11052283A 1998-03-13 1999-03-01 グラフィックスメモリシステム Pending JPH11353497A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US042291 1987-04-24
US09/042,291 US6747645B1 (en) 1998-03-13 1998-03-13 Graphics memory system that utilizes detached-Z buffering in conjunction with a batching architecture to reduce paging overhead

Publications (2)

Publication Number Publication Date
JPH11353497A true JPH11353497A (ja) 1999-12-24
JPH11353497A5 JPH11353497A5 (enExample) 2006-04-27

Family

ID=21921083

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11052283A Pending JPH11353497A (ja) 1998-03-13 1999-03-01 グラフィックスメモリシステム

Country Status (2)

Country Link
US (3) US6747645B1 (enExample)
JP (1) JPH11353497A (enExample)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6747645B1 (en) * 1998-03-13 2004-06-08 Hewlett-Packard Development Company, L.P. Graphics memory system that utilizes detached-Z buffering in conjunction with a batching architecture to reduce paging overhead
US6559852B1 (en) * 1999-07-31 2003-05-06 Hewlett Packard Development Company, L.P. Z test and conditional merger of colliding pixels during batch building
US6628292B1 (en) * 1999-07-31 2003-09-30 Hewlett-Packard Development Company, Lp. Creating page coherency and improved bank sequencing in a memory access command stream
US6633298B2 (en) * 1999-07-31 2003-10-14 Hewlett-Packard Development Company, L.P. Creating column coherency for burst building in a memory access command stream
US6473086B1 (en) * 1999-12-09 2002-10-29 Ati International Srl Method and apparatus for graphics processing using parallel graphics processors
US7468985B2 (en) * 2001-12-31 2008-12-23 Stmicroelectronics, Inc. System independent and scalable packet buffer management architecture for network processors
AUPS028702A0 (en) * 2002-02-01 2002-02-28 Canon Kabushiki Kaisha Efficient display update from changing object graphics
US20030164842A1 (en) * 2002-03-04 2003-09-04 Oberoi Ranjit S. Slice blend extension for accumulation buffering
US20030204410A1 (en) * 2002-04-26 2003-10-30 Clariant International, Ltd. Method and apparatus for approving color samples
US9330060B1 (en) 2003-04-15 2016-05-03 Nvidia Corporation Method and device for encoding and decoding video image data
US8660182B2 (en) * 2003-06-09 2014-02-25 Nvidia Corporation MPEG motion estimation based on dual start points
JP4613034B2 (ja) * 2004-06-03 2011-01-12 パナソニック株式会社 表示パネルドライバ装置
US8731071B1 (en) * 2005-12-15 2014-05-20 Nvidia Corporation System for performing finite input response (FIR) filtering in motion estimation
US8724702B1 (en) 2006-03-29 2014-05-13 Nvidia Corporation Methods and systems for motion estimation used in video coding
US9076265B2 (en) * 2006-06-16 2015-07-07 Ati Technologies Ulc System and method for performing depth testing at top and bottom of graphics pipeline
FR2902906A1 (fr) * 2006-06-21 2007-12-28 St Microelectronics Sa Gestion de donnes pour un traitement d'images
US8660380B2 (en) * 2006-08-25 2014-02-25 Nvidia Corporation Method and system for performing two-dimensional transform on data value array with reduced power consumption
US8756482B2 (en) * 2007-05-25 2014-06-17 Nvidia Corporation Efficient encoding/decoding of a sequence of data frames
US20080291209A1 (en) * 2007-05-25 2008-11-27 Nvidia Corporation Encoding Multi-media Signals
US9118927B2 (en) * 2007-06-13 2015-08-25 Nvidia Corporation Sub-pixel interpolation and its application in motion compensated encoding of a video signal
US8873625B2 (en) * 2007-07-18 2014-10-28 Nvidia Corporation Enhanced compression in representing non-frame-edge blocks of image frames
US20090083411A1 (en) * 2007-09-20 2009-03-26 Sawa Takano System and method for remote control of multiple devices
US8666181B2 (en) * 2008-12-10 2014-03-04 Nvidia Corporation Adaptive multiple engine image motion detection system and method
US20130222422A1 (en) * 2012-02-29 2013-08-29 Mediatek Inc. Data buffering apparatus capable of alternately transmitting stored partial data of input images merged in one merged image to image/video processing device and related data buffering method
KR101987160B1 (ko) 2012-09-24 2019-09-30 삼성전자주식회사 디스플레이 드라이버 집적회로, 그것을 포함하는 디스플레이 시스템 및 그것의 디스플레이 데이터 처리 방법
TWI463432B (zh) * 2012-10-05 2014-12-01 Genesys Logic Inc 圖像資料處理方法
US9489710B2 (en) 2015-02-10 2016-11-08 Qualcomm Incorporated Hybrid rendering in graphics processing
US10553167B2 (en) * 2017-06-29 2020-02-04 Japan Display Inc. Display device

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5043921A (en) * 1989-10-23 1991-08-27 International Business Machines Corporation High speed Z-buffer control
US5621866A (en) * 1992-07-24 1997-04-15 Fujitsu Limited Image processing apparatus having improved frame buffer with Z buffer and SAM port
GB2293079B (en) * 1993-05-10 1997-07-02 Apple Computer Computer graphics system having high performance multiple layer z-buffer
US5596686A (en) * 1994-04-21 1997-01-21 Silicon Engines, Inc. Method and apparatus for simultaneous parallel query graphics rendering Z-coordinate buffer
US5767856A (en) * 1995-08-22 1998-06-16 Rendition, Inc. Pixel engine pipeline for a 3D graphics accelerator
US6150679A (en) * 1998-03-13 2000-11-21 Hewlett Packard Company FIFO architecture with built-in intelligence for use in a graphics memory system for reducing paging overhead
US6747645B1 (en) * 1998-03-13 2004-06-08 Hewlett-Packard Development Company, L.P. Graphics memory system that utilizes detached-Z buffering in conjunction with a batching architecture to reduce paging overhead
US6078336A (en) * 1998-05-12 2000-06-20 Hewlett-Packard Company Graphics memory system that utilizes look-ahead paging for reducing paging overhead
US6920526B1 (en) * 2000-07-20 2005-07-19 Silicon Graphics, Inc. Dual-bank FIFO for synchronization of read data in DDR SDRAM

Also Published As

Publication number Publication date
US20010020941A1 (en) 2001-09-13
US6747645B1 (en) 2004-06-08
US20040212624A1 (en) 2004-10-28
US7126601B2 (en) 2006-10-24
US6317124B2 (en) 2001-11-13

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