JPH11352197A - Semiconductor testing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor testing device capable of coping with test conditions which cannot be assumed at a design step of an IC tester by writing a set condition from the CPU without enlarging a function of the IC tester. SOLUTION: A semiconductor testing device is provided with a test pattern memory circuit 4 storing a test pattern data and generating the test pattern data in every testing period; a test corrugation forming circuit 31 forming a test corrugation based on the test pattern data from the test pattern memory circuit 4; and a test pattern information conversion circuit 30 previously memorizing a control information and controlling a test corrugation forming means based on the control information making the test pattern data as an address.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor test apparatus for testing electrical characteristics of an IC or the like.

[0002]

2. Description of the Related Art A conventional semiconductor test apparatus, for example, an IC tester outputs an arbitrary electric signal to an IC under test and
By inputting an electric signal from C and comparing / determining at an arbitrary voltage and an arbitrary time, the electric characteristics of the IC under test are tested. An IC tester generally has a plurality of channels having the above functions, and can output signals under different conditions to an IC having a plurality of input / output terminals, and can perform comparison / judgment.

[0005] FIG. 5 is a configuration diagram schematically showing one channel of an IC tester having a plurality of channels as a conventional semiconductor test apparatus. In FIG. 1, reference numeral 1 denotes an IC tester control CPU in which a test flow and test conditions are programmed in accordance with the test specifications of the IC under test 20, and connected to each circuit of the IC tester via an IC tester control signal transmission bus 13 as necessary. Set the data. 2 is I
A C tester control circuit, which forms an operation reference signal of an IC tester, generates a condition change cycle of a test waveform (hereinafter, referred to as a test cycle), and generates an address designation signal of each storage circuit described later for each test cycle. Occurs.

Reference numeral 3 denotes a reference signal delay circuit for generating a change timing of a test waveform, and has a function of programmably delaying a test cycle generated by the IC tester control circuit 2. The amount of delay is set in advance by the CPU 1 in the storage circuit of the reference signal delay circuit 3 for the type required for the test, and is determined according to each test cycle by an address signal input from the IC tester control circuit 2 for each test cycle. Can be changed. Reference numeral 4 denotes a test pattern storage circuit, similar to the reference signal delay circuit 3, in which a test pattern is set in advance by the CPU 1;
According to the address signal input from the tester control circuit 2,
The required test pattern is output for each test cycle.

Reference numeral 5 denotes a test waveform forming circuit which synthesizes a part of the timing signal output from the reference signal delay circuit 3 and a part of the test pattern output from the test pattern storage circuit 4 for each test cycle, and performs a test. Form a waveform. Reference numeral 6 denotes a test waveform output circuit 7 described later from a part of the timing signal and a part of the test pattern as in the test waveform forming circuit 5.
Is a test waveform input control circuit for forming an ON / OFF switching signal of the test waveform.

The test waveform output circuit 7 has an ON (voltage output state) / OFF (high resistance state) switching function. Based on an ON / OFF switching signal from the test waveform input control circuit 6, the test waveform forming circuit 5 Is amplified based on the voltage value generated by the voltage supply circuits 8a and 8b, and the IC under test 20 is
Output the test waveform. Voltage supply circuits 8a and 8b
Is D / which converts digital data into an analog voltage value.
The A / D converter is configured to generate an analog voltage value in accordance with digital information set by the CPU 1 in advance.
In addition, since the test includes the definition of the Hi voltage and the Lo voltage,
A voltage supply circuit 8a for generating i voltage and a voltage supply circuit 8b for generating Lo voltage are provided. These components 1 to 8 are portions that substantially form a test waveform to be output to the IC under test.

Reference numerals 9a and 9b denote comparison circuits for comparing an electric signal input from the IC under test 20 with a reference voltage generated by the D / A conversion circuits 10a and 10b. In general, a Hi voltage comparison circuit 9a and a Lo voltage comparison circuit 9b are provided to determine the level and the Lo level. Numeral 11 denotes a judgment circuit for judging the comparison result outputted by the voltage comparison circuits 9a and 9b at an arbitrary time, which substantially includes a Hi judgment circuit and a Lo judgment circuit, and each signal of the Hi level judgment and the Lo level judgment. A determination is made using a part of the test pattern output from the test pattern storage circuit 4 and a determination timing signal output from the reference signal delay circuit 3, and the determination result is transmitted to the CPU 1 via the data line 14. It is.

Reference numeral 12 denotes voltage comparison circuits 9a and 9b
Is an intermediate value determination circuit that performs an intermediate value determination at an arbitrary time using the comparison result output from the IC, that is, determines that the output voltage of the IC under test 20 is between the Hi comparison voltage and the Lo comparison voltage. , Is often used to determine the high or low resistance state of an IC. The intermediate value judgment circuit 12 is also the judgment circuit 1
The determination result is transmitted to the CPU 1 in the same manner as in (1). These components 9 to 15 are portions that substantially compare / determine signals input from the IC under test 20.

Next, the operation will be described with reference to FIG. The logic table shown in FIG. 6 shows a test waveform forming circuit 5, a test waveform input control circuit 6, and a decision circuit 11 for the bit information (eight kinds of 000 to 111) of the test pattern data.
And the control state of the intermediate value determination circuit 12, which forms a test waveform or makes a determination by combining bit information of test pattern data. Test waveform forming circuit 5
Is a timing signal (a dedicated timing signal for forming a Hi / Lo switching time of a test waveform) in which the reference signal delay circuit 3 outputs information of the 0th bit of the test pattern data.
A test waveform is formed by triggering on.

The test waveform input control circuit 6 outputs a timing signal (ON of the test waveform output circuit 7) for outputting the information of the first bit of the test pattern data from the reference signal delay circuit 3.
An ON / OFF control waveform of the test waveform is formed by latching with a dedicated timing signal for forming an / OFF switching time). The Hi determination circuit of the determination circuit 11 performs a logical product of the inversion information of the 0th bit of the test pattern data, the information of the 2nd bit, and the timing signal output from the reference signal delay circuit 3 (the timing signal forming the determination time). (AN
D) to form a Hi determination timing signal,
The Hi determination result information is formed by triggering the Hi voltage comparison result input from the comparison circuit 9a by the i determination timing signal.

The Lo determination circuit of the determination circuit 11 obtains the logical product of the 0th bit information and the 2nd bit information of the test pattern data and the timing signal output from the reference signal delay circuit 3 to obtain a Lo determination timing signal. To form Lo
L input from the comparison circuit 9b according to the determination timing signal
Triggering the o voltage comparison result forms Lo determination result information.

The intermediate value judging circuit 12 calculates the logical product of the inversion information of the 0th bit and the 1st bit, the inversion information of the 2nd bit of the test pattern data, and the timing signal output from the reference signal delay circuit 3. , Hiz determination timing signal, and triggering an intermediate value determination signal generated from the Hi voltage comparison result and the Lo comparison result, thereby forming the Hiz determination result information. In addition, Hiz means high impedance, and Hiz judgment is high level (Hi) and low level.
It is often determined that the value is an intermediate value of (Lo). The respective pieces of determination result information are synthesized by the OR circuit 15 and are output as error information in units of pins via the signal line 14 to the CPU.
1 and the CPU 1 can detect the failure information of the IC under test 20.

[0013]

By the way, in the case of the conventional device, once the internal circuit of the IC tester is determined as described above, it becomes impossible to change the decode information of the test pattern data. However, there is a problem that the only way to perform a more complicated test is to extend the functions of the IC tester.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and can flexibly cope with test conditions that cannot be assumed in the design stage of an IC tester by merely writing setting conditions from a CPU. It is an object of the present invention to provide a semiconductor test apparatus capable of performing such a test.

[0015]

According to a first aspect of the present invention, there is provided a semiconductor test apparatus which stores test pattern data and generates test pattern data for each test cycle. Test waveform forming means for forming a test waveform based on the test pattern data, and test pattern information conversion for storing control information in advance and controlling the test waveform forming means based on the control information using the test pattern data as an address And a circuit.

According to a second aspect of the present invention, there is provided a semiconductor test apparatus, comprising:
In the invention of claim 1, the test pattern information conversion circuit can change its contents as needed.

According to a third aspect of the present invention, there is provided a semiconductor test apparatus comprising:
The invention according to claim 1 or 2, further comprising a judging means for outputting judgment result information on the device under test based on the control information from the test pattern information conversion circuit and the output of the test pattern storage means.

According to a fourth aspect of the present invention, there is provided a semiconductor test apparatus comprising:
In the invention according to claim 3, the determination means takes a logical product of the logically high-level control information from the test pattern information conversion circuit and the timing signal from the test pattern storage means, thereby obtaining a logically high level. A first determination circuit forming level determination result information, and a logical product of logically low level control information from the test pattern information conversion circuit and a timing signal from the test pattern storage means. And a second determination circuit for forming low-level determination result information.

According to a fifth aspect of the present invention, there is provided a semiconductor test apparatus, comprising:
5. The invention according to claim 4, wherein said determination means has a third determination circuit for forming determination result information on an intermediate value based on an output of said first determination circuit and an output of said second determination circuit. It is.

According to a sixth aspect of the present invention, there is provided a semiconductor test apparatus, comprising:
6. The test pattern storage device according to claim 1, wherein said test pattern storage means includes a reference signal delay circuit for generating a test waveform change timing signal, and a test pattern required for each test cycle based on an external address signal. And a test pattern storage circuit that outputs the test pattern.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. Embodiment 1 FIG. FIG. 1 is a configuration diagram showing Embodiment 1 of the present invention. In FIG. 1, portions corresponding to FIG. 5 are denoted by the same reference numerals, and detailed description thereof will be omitted. In the figure,
Reference numeral 30 denotes a test pattern information conversion circuit, which inputs a test pattern data as an address and outputs information stored in advance from the CPU 1 so that a test waveform forming circuit 31, a test waveform input control circuit 32, and a determination circuit 3
3 and a control signal to an Hiz determination circuit 34 as an intermediate value determination circuit. The test waveform forming circuit 31 forms a test waveform by triggering a test waveform forming circuit control signal output from the test pattern information conversion circuit 30 with a timing signal output from the reference signal delay circuit 3.

The test waveform input control circuit 32 triggers a control signal for the test waveform input control circuit output from the test pattern information conversion circuit 30 with a timing signal output from the reference signal delay circuit 3 to turn on / off the test waveform. OF
Form an F control waveform. The determination circuit 33 includes a Hi determination circuit as a first determination circuit and a Lo determination circuit as a second determination circuit.
A decision circuit is included.

The Hi determination circuit performs a logical product (AN) of the control signal for the Hi determination circuit output from the test pattern information conversion circuit 30 and the timing signal output from the reference signal delay circuit 3.
D) to form a Hi determination timing signal,
The Hi determination result information is formed by triggering the Hi voltage comparison result input from the comparison circuit 9a by the i determination timing signal. The Lo determination circuit forms a Lo determination timing signal by calculating the logical product of the control signal for the Lo determination circuit output from the test pattern information conversion circuit 30 and the timing signal output from the reference signal delay circuit 3.
L input from the comparison circuit 9b according to the determination timing signal
Triggering the o voltage comparison result forms Lo determination result information.

Hiz determination circuit 3 as third determination circuit
Reference numeral 4 denotes a logical product of the control signal for the intermediate value determination circuit output from the test pattern information conversion circuit 30 and the timing signal output from the reference signal delay circuit 3, thereby forming a Hiz determination timing signal and comparing the Hi voltage. By triggering the intermediate value judgment signal generated from the result and the Lo comparison result, H
iz determination result information is formed. The reference signal delay circuit 3 and the test pattern storage circuit 4 constitute a test pattern storage unit, and the test waveform forming circuit 31 and the test waveform input control circuit 32 constitute a test waveform forming unit. Also,
The judgment circuit 33 including the Hi judgment circuit and the Lo judgment circuit and Hi
The z determination circuit 34 forms a determination unit.

Next, the operation will be described with reference to FIGS. Here, the test pattern information conversion circuit 3
By setting the contents to 0 as necessary from the CPU 1 via the data bus 13 before the test, the decoding condition of the test pattern data can be controlled. For example, by storing the information shown in FIGS. 2 and 3,
An IC tester capable of performing the same operation as that described above can be obtained. That is, if the bit information of the test pattern data is “000”, a Lo output control signal is output to the test waveform forming circuit 31, and an OFF control signal is output to the test waveform input control circuit 32, the determination circuit 33, and the Hiz determination circuit 34. I do. As a result, the test waveform output is turned off, and the Hi / Lo / Hiz determination is realized as OFF.

In the same test cycle, the IC under test 2
After inputting the Hi-level test waveform to 0 (see FIG. 5), the test waveform output circuit 7 is turned off by 0FF to perform Lo determination, or after inputting the Lo-level test waveform to the IC under test 20, the Hi-level determination is performed. When a special test such as a test is required, the contents shown in FIG. 3 are stored, so that the test can be realized without changing the circuit configuration of the IC tester.

The operation when the test pattern data "6" shown in FIG. 3 and the data "7" correspond to the above conditions and the data "6" is used will be described.
In order to form the test waveform shown in (1), data "2" or data "3" (in the embodiment, data "3" is used and set to the Hi level) in the (N-1) th cycle, and the test waveform output circuit is used. 7 is turned on to change to the Lo output state in the Nth cycle. Thereafter, the test waveform output circuit 7 is changed to the OFF state, and a judgment is made by the Hi judgment circuit, so that the output voltage of the IC under test 20 can be compared and judged. That is, in the (N-1) th cycle, the test waveform change timing (CLKIN) latches the test waveform forming circuit control information (1), determines the Hi state of the test waveform output circuit 7, and sets the test waveform output control timing (IOCI).
N) latches the test waveform output circuit control information (1), and the test waveform output circuit 7 starts outputting the Hi voltage.

In the Nth cycle, CLKIN latches 0 information and changes the test waveform output circuit 7 to Lo level, and IOCIN latches 0 information and turns off the test waveform output circuit 7. Thereafter, the determination timing (ST
A signal that is the logical product of the BIN) and the Hi determination circuit control information triggers the Hi comparison result, and determines the output voltage level of the IC under test 20. This is the IC under test 20
Can be applied to a test when the test terminal changes from a signal input state to an output state. Thus, according to the present embodiment, a semiconductor test apparatus that can flexibly cope with test conditions that cannot be assumed in the design stage of the IC tester by simply writing the setting conditions from the CPU can be obtained.

[0029]

According to the first aspect of the present invention, test pattern storage means for storing test pattern data and generating test pattern data for each test cycle, and based on the test pattern data from the test pattern storage means. A test waveform forming means for forming a test waveform; and a test pattern information converting circuit for storing control information in advance and controlling the test waveform forming means based on the control information using the test pattern data as an address.
For test conditions that cannot be assumed at the tester design stage,
By simply writing the setting conditions from the CPU, the function of the IC tester can be flexibly supported without extending the function, and there is an effect that a versatile and inexpensive semiconductor test apparatus can be obtained.

According to the second aspect of the present invention, the contents of the test pattern information conversion circuit can be changed as needed, so that there is an effect that the test pattern information conversion circuit can easily cope with the test purpose.

According to the third aspect of the present invention, there is provided the determination means for outputting the determination result information on the device under test based on the control information from the test pattern information conversion circuit and the output of the test pattern storage means. Thus, it is possible to select a necessary judgment condition from various test conditions, and it is possible to perform a flexible semiconductor test.

According to the fourth aspect of the present invention, the determining means calculates the logical product of the logically high level control information from the test pattern information conversion circuit and the timing signal from the test pattern storage means. And a first determination circuit for forming logically high-level determination result information, and a logical product of the logically low-level control information from the test pattern information conversion circuit and the timing signal from the test pattern storage means. And a second determination circuit that logically forms low-level determination result information, so that necessary determination conditions can be selected from various test conditions, and a flexible semiconductor test can be performed. effective.

According to the fifth aspect of the present invention, the determination means forms the determination result information on the intermediate value based on the output of the first determination circuit and the output of the second determination circuit. Since the determination circuit is provided, a necessary determination condition can be selected from various test conditions, and there is an effect that a flexible semiconductor test can be performed.

According to the present invention, the test pattern storage means includes a reference signal delay circuit for generating a test waveform change timing signal, and a test pattern required for each test cycle based on an external address signal. And a test pattern storage circuit that outputs the test data, so that the semiconductor test can be efficiently performed.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing an example of information stored in a test pattern data information conversion circuit according to the first embodiment of the present invention.

FIG. 3 is a diagram showing another example of the storage information of the test pattern data information conversion circuit according to the first embodiment of the present invention.

FIG. 4 is a diagram showing an example of a test waveform according to the first embodiment of the present invention.

FIG. 5 is a configuration diagram showing a conventional semiconductor test apparatus.

FIG. 6 is a diagram showing a decode logic table of test pattern data in a conventional semiconductor test apparatus.

[Explanation of symbols]

Reference Signs List 1 IC tester control CPU, 2 IC tester control circuit, 3 reference signal delay circuit, 4 test pattern storage circuit, 7 test waveform output circuit, 8a, 8b voltage supply circuit, 9a Hi voltage comparison circuit, 9b Lo voltage comparison circuit, 10a , 10b A / D conversion circuit, 30 test pattern information conversion circuit, 31 test waveform formation circuit, 32 test waveform input control circuit, 33 Hi /
Lo judgment circuit, 34 Hiz judgment circuit.

Claims (6)

[Claims] 1. Test pattern storage means for storing test pattern data and generating test pattern data for each test cycle, and test waveform forming means for forming a test waveform based on the test pattern data from the test pattern storage means And a test pattern information conversion circuit for storing control information in advance and using the test pattern data as an address to control the test waveform forming means based on the control information. 2. The semiconductor test apparatus according to claim 1, wherein the content of the test pattern information conversion circuit can be changed as needed. 3. The apparatus according to claim 1, further comprising: determination means for outputting determination result information on the device under test based on control information from the test pattern information conversion circuit and an output of the test pattern storage means. Or the semiconductor test apparatus according to 2. 4. The logic circuit according to claim 1, wherein the determination means calculates a logical product of the logically high level control information from the test pattern information conversion circuit and the timing signal from the test pattern storage means. The first determination circuit forming the determination result information, and the logical product of the logically low level control information from the test pattern information conversion circuit and the timing signal from the test pattern storage means are logically obtained. 4. The semiconductor test apparatus according to claim 3, further comprising a second determination circuit for forming low-level determination result information. 5. The method according to claim 1, wherein the determining means includes a third determining circuit that forms determination result information on an intermediate value based on an output of the first determining circuit and an output of the second determining circuit. The semiconductor test apparatus according to claim 4, wherein 6. The test pattern storage means includes: a reference signal delay circuit for generating a test waveform change timing signal; and a test pattern storage circuit for outputting a required test pattern for each test cycle based on an external address signal. The semiconductor test apparatus according to any one of claims 1 to 5, comprising: