JP2001289915A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of testing its own circuit operating at a high speed by using a general low speed LSI tester. SOLUTION: This semiconductor device 1 having a testing circuit 2 operating at a high speed, internally stores a high speed pattern generating circuit 3 for coverting a low speed test pattern of a reference clock, an input signal and an output expected value signal inputted from the low speed LSI tester into a test pattern of a speed adapted to the testing circuit 2 operating at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a circuit for testing its own circuit operating at high speed.

[0002]

2. Description of the Related Art Conventionally, a test of a semiconductor device whose operation of a test circuit is guaranteed at a high speed is performed based on a clock obtained by multiplying a clock of a semiconductor test device of a low-speed operation (hereinafter referred to as a low-speed LSI tester) by a PLL built in the semiconductor device. A test circuit and a circuit having a complicated configuration (generally called a BIST circuit) that generates a high-speed logic pattern by itself are operated at a high speed.

[0003]

However, in recent years, as the operation clock of the semiconductor circuit has been accelerated, a semiconductor device which operates at a high speed exceeding the operation guarantee limit of a conventionally used low-speed LSI tester has been developed. is increasing.

Therefore, when testing a semiconductor device whose operation of the test circuit is guaranteed at a high speed, an expensive high-speed LSI is required.
Although a tester has been introduced or a low-speed LSI tester has been modified so as to be faster, the test cost has been increased.

[0005] The present invention solves the above-mentioned problems.
It is an object of the present invention to provide a semiconductor device capable of testing its own circuit operating at high speed using a general low-speed LSI tester.

[0006]

SUMMARY OF THE INVENTION The present invention provides an external low speed L.
A high-speed test pattern generation circuit that generates a high-speed test pattern based on a reference clock, input signal, and expected output signal (hereinafter referred to as a test pattern) input from an SI tester is implemented to enable high-speed testing of high-speed logic circuits. It was done.

According to the present invention, a high-speed test of a semiconductor device on which a high-speed logic circuit is mounted can be performed without incorporating a BIST circuit for self-generating a high-speed logic pattern as in the prior art.
The test can be performed using the logic pattern of the conventional test method, so that there is no need to prepare an expensive high-speed LSI tester or to modify a low-speed LSI tester to increase the speed.

[0008]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a semiconductor device according to one embodiment of the present invention, and FIG. 2 is a block diagram showing a specific configuration of a high-speed pattern generating circuit according to one embodiment of the semiconductor device of the present invention. is there.

A test circuit 2, a high-speed pattern generation circuit 3, a comparator 4, test terminals 5, 6, 7 and a delay selector control terminal 8 are mounted on the semiconductor device 1 which operates at high speed (see FIG. 1).

A semiconductor test apparatus (hereinafter referred to as a low-speed LSI tester) 12 whose operation guarantee limit is low is provided with an input signal driver (hereinafter referred to as DR) 9, a test pattern generator (hereinafter referred to as PG) 10, and an output signal comparator (hereinafter referred to as PG). (Hereinafter referred to as CP) 11 is mounted (see FIG. 1).

Further, the high-speed pattern generation circuit 3 for accelerating the low-speed test pattern of the low-speed LSI tester 12 includes:
PLL 13, delay control selector 14, first test pattern memory 15, second test pattern memory 16,
The delay adjustment circuit 17, the bus 18, the bus 19, the bus 20, the bus 21, and the bus 22 are mounted (see FIG. 2).

The configurations of the semiconductor device 1 and the low-speed LSI tester 12 will be described in more detail. The low-speed LSI tester 12 includes a reference clock, an input signal, and an expected output signal (hereinafter referred to as a test pattern) output by the PG 10.
From the DR 9 to the test terminal 5 of the semiconductor device 1,
1 to the test terminal 6 of the semiconductor device 1 and the data output from the comparator 4 of the semiconductor device 1 via the test terminal 7 are processed by the test result determination function.

The PLL 13 of the semiconductor device 1 is connected to a low-speed LSI tester 12 input to a bus 18 via a test terminal 5.
Is multiplied to a frequency corresponding to the operation speed of the test circuit 2 and output to the first test pattern memory 15 and the second test pattern memory 16 as an operation clock.

The first test pattern memory 15 of the semiconductor device 1 stores, in a temporary memory, an input signal pattern of the low-speed LSI tester 12 input to the bus 18 via the test terminal 5, and stores an operation clock output by the PLL 13. The signal is output from the bus 20 to the test circuit 2 as a synchronized high-speed input signal pattern.

The second test pattern memory 16 of the semiconductor device 1 temporarily stores the low-speed output expected value pattern of the low-speed LSI tester 12 input to the bus 22 via the test terminal 6 in a temporary memory, and outputs the pattern from the PLL 13. It is output as a high-speed expected comparison pattern synchronized with the operation clock.

The delay adjustment circuit 17 of the semiconductor device 1 has n
(N = 1, 2, 3,...), N tristate buffers are connected in series at the stage, and these stages are connected to the second stage.
Are connected in parallel to the output terminals of the test pattern memory 16 and the control terminals of the tri-state buffers in the n-th column of each stage are connected in parallel to the output terminals of each column of the delay control selector 14.

The delay control selector 14 of the semiconductor device 1
By controlling the number of operating stages of the tri-state buffer according to the test pattern of the low-speed LSI tester 12 input to the bus 19 via the delay selector control terminal 8,
The path of the comparison expected value pattern output from the second test pattern memory 16 is selected, and the output timing of the comparison expected value pattern from the bus 21 is controlled.

The comparator 4 of the semiconductor device 1 outputs an output value pattern output from the test circuit 2 based on the accelerated input signal pattern output from the first test pattern memory 15 and an output value pattern output from the bus 21. By comparing the pattern with the expected comparison value pattern, an L signal is output when the operation of the test circuit 2 is normal, and an H signal is output when the test circuit 2 has a failure.

Next, the operation of the semiconductor device 1 of the present invention will be described.

The low-speed test pattern input from the DR 9 of the low-speed LSI tester 12 to the test terminal 5 of the semiconductor device 1 is transferred to the first test pattern memory 1 via the bus 18.
5 and temporarily stored in C of the low-speed LSI tester 12.
The low-speed test pattern input to the test terminal 6 of the semiconductor device 1 from P11 is temporarily stored in the second test pattern memory 16 via the bus 22.

In the PLL 13, the test circuit 2 based on the low-speed test pattern input from the bus 18 is used.
When the clock multiplied and speeded up so as to match the operation speed of the first test pattern memory 15 and the second test pattern memory 16 is output as the operation clock of the first test pattern memory 15 and the second test pattern memory 16, The second test pattern memories 16 operate at high speed, respectively,
The test pattern memory 15 outputs the accelerated input signal pattern, and the second test pattern memory 16 outputs the accelerated comparison expected value pattern.

Incidentally, the first test pattern memory 1 is stored in the test circuit 2 which operates at a high speed based on the description of the logical pattern.
5 is delayed until the input signal pattern input from the test circuit 2 is output from the test circuit 2 as an output value pattern. , The comparison result becomes unstable.

Therefore, based on a control signal input to the selector delay control 14 via the delay selector control terminal 8 of the semiconductor device 1, the delay adjustment circuit 17 for the comparison expected value pattern output from the second test pattern memory 16 , And by switching the number of stages of the tristate buffer, the bus 21 of the comparison expected value pattern
Is delayed by a desired time.

Therefore, the comparator 4 compares the output value pattern output from the test circuit 2 with the expected comparison value pattern output from the bus 21. When the operation of the test circuit 2 is normal, the L signal is output. When a fault location exists in the test circuit 2, an H signal is output from the test terminal 7. Then, the low-speed LSI tester 12 determines the signal output from the test terminal 7 by the test result determination function, and determines whether the test circuit 2 is good or not (PASS / FAIL determination).

As described above, according to the present embodiment, even when testing the test circuit 2 which needs to operate at a frequency exceeding the guaranteed operation of the low-speed LSI tester 12, the logic pattern of the conventional test method is utilized. BIS that enables self-generation of high-speed logic patterns
It is not necessary to incorporate a T circuit into the semiconductor device to be measured. In addition, an expensive high-speed LSI
Since there is no need to modify the tester 12 to increase the speed, a high-speed test of a semiconductor device having a built-in high-speed logic circuit can be performed by a low-speed LSI tester. Can be realized.

[0027]

As described above, according to the present invention, a high-speed test of a semiconductor device having a built-in high-speed logic circuit can be performed without using a BIST circuit for generating a high-speed logic pattern by itself. Since a test can be performed using a logic pattern of a test method, there is no need to prepare an expensive high-speed LSI tester or to modify a low-speed LSI tester to increase the speed. The high-speed test can be performed by a low-speed LSI tester, so that a new capital investment is not required, and an effect that a low-cost test can be realized is achieved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a semiconductor device according to an embodiment of the present invention;

FIG. 2 is a block diagram showing a specific configuration of a high-speed pattern generation circuit in one embodiment of the semiconductor device of the present invention;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Test circuit 3 High-speed pattern generation circuit 4 Comparator 5, 6, 7 Test terminal 8 Delay selector control terminal 9 Input signal driver 10 Test pattern generator (DR) 11 Output signal comparator (PG) 12 Low-speed LSI tester ( CP) 13 PLL 14 Delay control selector 15 First test pattern memory 16 Second test pattern memory 17 Delay adjustment circuit 18, 19, 20, 21, 22 bus

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H01L 21/66 G01R 31/28 Q

Claims (4)

[Claims] In a semiconductor device using a high-speed logic circuit as a test circuit, a high-speed pattern generation circuit that generates a high-speed test pattern based on a low-speed test pattern input from an external low-speed LSI tester is mounted. Characteristic semiconductor device. 2. The high-speed pattern generation circuit generates a high-speed test pattern adapted to a test speed of the high-speed logic circuit based on a low-speed test pattern input from the low-speed LSI tester. 2. The semiconductor device according to 1. 3. A delay adjustment circuit for delaying an output value pattern output from the high-speed logic circuit and adjusting timing with a comparison expected value pattern output from the high-speed pattern generation circuit is further mounted. The semiconductor device according to claim 1, wherein: 4. A comparator for comparing an output value pattern output from the high-speed logic circuit with a comparison expected value pattern output from the high-speed pattern generation circuit. 13. The semiconductor device according to claim 1.