JPH11345091A - Data transfer controller and optical disk device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute a normal restoration treatment without inviting a defective situation at the time of performing restoration from repetitive operations under transfer condition monitoring even in the case that data transfer following an ATAPI command is delayed. SOLUTION: This data transfer controller receives the ATAPI command from a host and monitors the transfer condition of data following the command by starting an interruption transfer processing corresponding to the ATAPI command at the time of the interruption transfer processing. After receiving the ATAPI command (S3: YES), a CPU repeatedly examines whether or not the transfer of the data is completed with the host under data transfer condition monitoring (S4). During the repetitive examination of S4, at the time of detecting the generation of a reset factor different from the interruption transfer processing (S13: YES), the CPU shifts to a reset processing different from the interruption transfer processing (S14).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a data transfer control device incorporated in an optical disk device (including a magneto-optical disk device) used as an external storage device of a computer and a control program of the data transfer control device. The present invention relates to an optical disk device that operates based on the information.

[0002]

2. Description of the Related Art Conventionally, an optical disk device connected to a personal computer or the like as a host has a function as a data transfer control device for monitoring data transfer when data is transferred from the host.

In this type of optical disk device, ATAPI (ATAP) is one of the interface standards.
(ACKET INTERFACE) standard has been widely adopted, and the optical disk device is configured to include a CPU for controlling data transfer with a host in accordance with the ATAPI standard.

[0004] The operation of the conventional optical disk device conforming to the ATAPI standard will be described in detail. Prior to data transfer from a host, the optical disk device transmits a transfer control command (hereinafter referred to as an "ATA") issued by the host.
PI command ”). This ATAPI
After receiving the command, the CPU of the optical disc device
By executing the command interrupt processing, packet data transferred from the host via the data bus following the ATAPI command is received.

[0005] The packet data referred to here is ATAP.
This is continuous data of a predetermined number of bytes indicating the contents of the I command and the like, and is usually data transferred from the host almost simultaneously following the ATAPI command. Therefore, the CPU monitors the data transfer in the interrupt hierarchy by repeatedly testing the completion of the data transfer after starting the execution of the command interrupt process, and instantaneously confirms the transfer completion test result in the repeated test. , The command interrupt process for data transfer is completed, and the process proceeds to an operation waiting process belonging to the next idle layer or the like.

Here, as a program for executing a command interruption process relating to data transfer in the interrupt hierarchy, that is, for monitoring the data transfer status by repeatedly verifying the completion of data transfer, other commands are used. It has a programming structure that cannot accept interrupts. Thereby, the CP of the optical disc device is
U cannot perform reset processing or the like until the data transfer is completed after the ATAPI command is input from the host, and after the data transfer is completed, the CPU outputs the data in response to a key input or the like. It is possible to shift to another process in response to a reset command or the like.

[0007]

However, some of the diversified personal computers nowadays usually include ATA.
There is a case where the data transfer is started almost simultaneously after the issuance of the PI command, but the start of data transfer is delayed for a considerable time after the issuance of the ATAPI command. In such a conventional optical disk device connected with a personal computer as a host, immediately after an ATAPI command is input from the host, an interrupt process in which another command interrupt or the like cannot be accepted in the interrupt hierarchy is started. Therefore, the repetitive operation for monitoring the transfer of data from the host is permanently continued until the transfer is completed. As a result, after accepting the ATAPI command, even if a reset command is issued by a key input or the like in response to a trouble on the data bus or the like, the reset process cannot be executed. In such a case,
If a power-down method is used as a final method to recover a CPU that has been repeatedly operated, data on an optical disk may be destroyed.

The present invention has been proposed in view of the above points, and even if data transfer following a transfer control command from a host is delayed, another processing is performed under monitoring of the transfer status. And a data transfer control device capable of performing a normal recovery procedure without causing a malfunction when recovering from a repetitive operation under transfer status monitoring, and the data transfer control device It is an object of the present invention to provide an optical disk device that operates based on the above control program.

[0009]

DISCLOSURE OF THE INVENTION In order to achieve the above object, the present invention employs the following technical means.

That is, the data transfer control device provided according to the first aspect of the present invention receives a transfer control command from a host and transfers the transfer control command before data is transferred to the host. A data transfer control device that monitors a data transfer status by executing an interrupt transfer process in response to the transfer control command. Transfer completion verification means for repeatedly verifying whether or not the data transfer has been completed; and during the repeated verification by the transfer completion verification means, a transition is made to another processing in accordance with an interrupt factor different from the interrupt transfer processing. And a separate processing shift unit.

According to such a data transfer control device,
After receiving the transfer control command from the host, whether or not the data transfer with the host is completed is repeatedly verified under the monitoring of the data transfer status. Subsequent data transfer may be significantly delayed. In such a situation, when an interrupt factor different from the interrupt transfer process using the transfer control command as the interrupt factor occurs, the process shifts to another process according to the other interrupt factor. In other words, if the repetitive operation for verifying the transfer completion under the transfer status monitoring is permanently continued, in order to recover from such repetitive operation to the original operation state, for example, a measure to issue a reset command etc. If this is done, the reset command etc. will be transferred to the reset processing as another interrupt factor, and the normal recovery measures will be performed without the need to take the final measures such as power cut-off that causes a bad situation such as data destruction can do.

In a preferred embodiment, the separate process shift means detects a reset factor as an interrupt factor different from the interrupt transfer process, and when the reset factor is detected, the interrupt process is performed. The execution of the transfer process is stopped and the process proceeds to the reset process.

According to such a data transfer control device,
When a reset factor, which is another interrupt factor different from the interrupt transfer process, is detected, the repetitive operation in the interrupt transfer process is stopped and the process is shifted to another reset process. When the operation state is restored, if a measure for issuing a reset command as a reset factor is performed, the reset command is detected even during the interrupt transfer processing, and the process can be reliably shifted to the reset processing.

In another preferred embodiment, the separate processing shift means receives a transfer incomplete test result obtained by the transfer completion test means as an interrupt factor different from the interrupt transfer processing. At the same time, according to the test result, the process shifts to an operation waiting process belonging to a different hierarchy from the interrupt transfer process to monitor the data transfer status.

According to such a data transfer control device,
As another cause of the interrupt transfer process, if a repetition test in the interrupt transfer process yields a test result indicating that transfer has not been completed, the process shifts to an operation waiting process belonging to a different layer from the interrupt transfer process and the data is transferred. Since the transfer status is monitored, various types of interrupt processing can be performed in an operation waiting process belonging to a different layer from the interrupt. As a type of the interrupt processing, the repetition test of the transfer completion by the interrupt transfer processing is performed. Another process according to the interrupt factor, for example, a reset process can be executed.

Further, as another preferred embodiment, the separate processing shift means measures the elapsed time of the test repeated by the transfer completion verifying means, and the elapsed time reaches a predetermined time. At this time, assuming that an interrupt factor different from the interrupt transfer process has occurred, the process shifts to an operation waiting process belonging to a different layer from the interrupt transfer process to monitor the data transfer status.

According to such a data transfer control device,
When the elapsed time of the test repeated in the interrupt transfer process reaches a predetermined time, the process shifts to an operation waiting process belonging to a different layer from the interrupt transfer process and the data transfer status is monitored. If the subsequent data transfer is not completed even after the lapse of a predetermined time, the process shifts to an operation waiting process belonging to a different layer from the interrupt, and various types of interrupt processes are enabled. As one type of the interrupt process, the interrupt transfer process is used. While performing the repetition test of the transfer completion, it is possible to execute another process according to the interrupt factor, for example, a reset process.

Further, as another preferred embodiment, the transfer completion verification means, after receiving the transfer control command, verifies the transfer completion of the fixed-length data transferred following the transfer control command. I have.

According to such a data transfer control device,
Since the completion of the transfer of fixed-length data is repeatedly verified following the transfer control command, for example, if fixed-length data of about several bytes is transferred following the transfer control command, the verification of the completion of the transfer is immediately terminated. To transfer to the next process, and if an error occurs in the transfer of fixed-length data, issue another interrupt command, etc., to promptly execute an interrupt process different from the transfer of the fixed-length data. Can be migrated to.

Further, as another preferred embodiment, the transfer control command is a control signal of a command system conforming to the ATAPI standard.

According to such a data transfer control device,
A transfer control command can correspond to a control signal of a command system conforming to the ATAPI standard.
When the transfer timing is different from the transfer timing based on the PI command, it is possible to respond with good mobility.

An optical disk device provided by the second aspect of the present invention is an optical disk device provided with an interface means for transmitting / receiving data for writing / reading to / from a host computer. The means has a data transfer control function corresponding to a transfer format capable of arbitrarily setting a time interval between a predetermined command sent from the host computer and data of a predetermined length following the command, and And a state transition control unit for shifting from a data standby state based on the reception of the command to a standby state according to another command.

According to such an optical disk device, the time interval from the transmission of a predetermined command from the host computer to the start of the transfer of subsequent data of a predetermined length may be set relatively long. In such a case,
The state shifts to another standby state in response to another command. In other words, the operations of the interface unit and the state transition control unit can be realized by the above-described data transfer control device. Examples of the optical disk device connected with the computer as a host include a magneto-optical disk device, a CD-ROM drive, and the like. When applied to various types of optical disc devices that can be connected to a computer, such as a so-called removable storage device and a DVD (Digital Versatile Disc) device, it is possible to avoid a bad situation that causes data destruction on the optical disc and restore normal operation. it can.

[0024] In a preferred embodiment, the state transition control means determines that the reception of another command is valid if no data accompanying the command is received within a predetermined time after the reception of the predetermined command. I do.

According to such an optical disk device, after receiving a predetermined command, if data following the command cannot be received within a predetermined time, reception of another command becomes valid. If data following the command cannot be received due to a problem, another command is issued after a predetermined time has elapsed after receiving the predetermined command, and the process shifts to another process in response to the reception of the other command. can do.

In another preferred embodiment, the operation of the drive mechanism of the optical disk device is stopped during the waiting of data based on the reception of the predetermined command.

According to such an optical disk device, the operation of the drive mechanism is stopped during the standby until the data transfer is started. Therefore, when the data transfer is prolonged, the power consumption accompanying the drive is reduced. Can save money.

Other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the accompanying drawings.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be specifically described below with reference to the drawings.

FIG. 1 is a circuit block diagram showing a circuit configuration of a magneto-optical disk device having a function as a data transfer control device according to the present invention. The magneto-optical disk device shown in FIG. -Optical Disk device is abbreviated as “MO” 10 is connected as an external storage device such as a personal computer serving as host 20. In this type of MO10, for example, 3.
Data is read or written via a 5-inch size removable storage medium.

The MO 10 having a function as a data transfer control device includes a CPU 1, a ROM 2, a RAM 3, and an external I / O.
An F (interface) 4, an internal IF 5, a spindle motor 6, a head 7, a laser irradiation unit 8, and the like are provided. CPU1, ROM2, RAM3,
The external IF 4 and the internal IF 5 are mutually connected by a bus line. The bus lines include an address bus, a data bus, and a control signal line. A host 20 such as a personal computer is connected to the external IF 4. A spindle motor 6, a head 7, and a laser irradiation unit 8 are connected to the internal IF 5.

The CPU 1 controls the entire MO 10. R
The OM 2 stores a control program executed by the CPU 1 and the like. The RAM 3 stores various data according to the operation of the CPU 1. The external IF 4 includes an I / O connector and a gate array circuit for connecting a cable to the host 20, and the so-called ATAPI standard is adopted as the interface standard. The internal IF 5 is configured by a gate array circuit or the like, and allows input / output signals to be exchanged between devices. The spindle motor 6 is an MO1
0 is a drive source for rotating the removable storage medium used for the camera, and operates under the control of the CPU 1. The head 7 reads and writes data on the recording surface of the removable storage medium, and reads and writes data based on magnetic and optical principles under the control of the CPU 1. The laser irradiator 8 irradiates a laser beam of a predetermined wavelength when reading or writing data, and operates according to the control of the CPU 1.

The ATAPI standard is similar to the ATA standard, which is a standard interface standard for IDE hard disks in personal computers and the like, and is generally defined as an interface standard for connecting devices other than hard disks. This A
The operation of the MO 10 according to the TAPI standard command will be specifically described in the following description.

Briefly explaining the main points of the MO 10 having a function as a data transfer control device, for example, when data is transferred from the host 20 to the MO 10, an ATAPI command is sent from the host 20 to the MO 10 prior to the data transfer. publish. In the MO 10 receiving this ATAPI command, the ATAPI command is written to the command register in the external IF 4. Then, when confirming that the ATAPI command has been written in the command register, the CPU 1 of the MO 10 executes an interrupt transfer process. Here, the interrupt transfer processing is based on a control program stored in the ROM 2.
This is a kind of interrupt processing executed by the PU1, and like the normal interrupt processing, the CPU 1 is in a state where other processing cannot be executed during the execution of the interrupt transfer processing. Almost simultaneously with the start of the execution of the interrupt transfer process, n bytes of fixed-length data (hereinafter, referred to as “packet data”) indicating the contents of the ATAPI command and the like are provided following the ATAPI command.
It is transferred from 0. The CPU 1 that has started the execution of the interrupt transfer process then monitors the transfer status of the packet data until the transfer is completed. In particular,
While monitoring the transfer status of the packet data, the CPU 1
Repeatedly tests whether the transfer of, for example, 12-byte packet data from the host 20 has been completed.
When a normal transfer completion result is obtained as the verification result,
After completing the interrupt transfer process, the CPU 1 shifts to an operation waiting process belonging to an idle layer or the like, and is released from the occupation state regarding the interrupt process.

On the other hand, in a personal computer or the like serving as the host 20, the transfer of packet data is started almost simultaneously after the issuance of the ATAPI command. Some are delayed in time. While such a packet data transfer delay occurs, there is a case where reset processing is desired to be performed in response to a trouble occurring on the data bus. When a reset command is issued by key input or the like during the monitoring of the transfer status of the packet data, that is, during the repeated verification of the transfer completion, the CPU
No. 1 shifts to a reset process, which is a type of another interrupt process, in response to the reset command, even though the interrupt transfer process is being executed.

FIG. 2 is an explanatory diagram showing an execution method of the CPU 1 shown in FIG. 1. As shown in FIG.
Is defined on the basis of the hierarchical programming structure stored in the ROM 2. Usually, while executing the interrupt processing based on the interrupt control firmware A defined with higher priority, The CPU 1 is in an occupied state in which an operation waiting process based on the lower-order idle control firmware B or the like cannot be executed. Conversely, when the operation waiting process based on the idle control firmware B is being executed, the CPU 1 performs the operation based on the interrupt control firmware A in response to a reset command such as a key input from the host 20 which is a type of the interrupt command. It is possible to execute a reset process and return from the operating state to the original initial state. The feature of this embodiment is that the CPU 1 can execute a reset process, which is another interrupt process, while the CPU 1 is executing the interrupt transfer process in the interrupt hierarchy to which the interrupt control firmware A belongs.

That is, after receiving the transfer control command, the CPU 1 repeatedly checks whether or not the data transfer with the host has been completed under the monitoring of the data transfer status, and a transfer completion check means. During the repetition verification by the means, another processing shift means for shifting to another processing according to an interrupt factor different from the interrupt transfer processing is realized.

Further, the CPU 1 exchanges data for writing / reading with the host computer, and sets a time interval between a predetermined command sent from the host computer and data of a predetermined length accompanying the command. Realizing an interface means having a data transfer control function corresponding to a transfer format that can arbitrarily set a command, and further, the CPU 1 shifts from a data standby state based on reception of a predetermined command to a standby state according to another command. This implements a state transition control unit that causes the state transition to be performed.

More specifically, the CPU 1 which realizes such a state transition control means, when a predetermined command is received and no data accompanying the command is received within a predetermined time, receives the other command. Reception can be valid.

Next, data transfer processing between the MO 10 and the host 20 shown in FIG. 1 will be described with reference to a flowchart shown in FIG.

FIG. 3 is a flowchart showing an example of an execution procedure when packet data is transferred in response to an ATAPI command. The interrupt transfer process shown in FIG. Is written to the command register of the external IF 4. At this time, the CPU 1 operates while being occupied by the interrupt control firmware A in the interrupt hierarchy shown in FIG.

First, the CPU 1 determines whether or not there is a command written in the command register (S1).
1).

When there is a command in the command register (S1: YES), the CPU 1 shifts to the interrupt hierarchy and executes the interrupt control firmware A (S2).

The CPU 1 thus operating in the interrupt hierarchy
Indicates that the command written to the command register is ATA
It is determined whether the command is a PI command (S3).

If the command is an ATAPI command (S3: Y
ES), the CPU 1 starts the interrupt transfer process,
It is determined whether the transfer of the packet data transferred from the host 20 following the API command is completed (S
4). Here, the packet data is normally sent from the host 20 immediately after issuing the ATAPI command.

When the completion of the transfer of the packet data is obtained as the test result (S4: YES), the CPU 1 determines whether or not the spindle motor 6 is stopped (S4).
5).

If the spindle motor 6 is not in a stopped state (S5: NO), the CPU 1 executes a process for decoding the contents of the received packet data (S6).

Subsequently, based on the contents of the packet data decoded in S6, the CPU 1 verifies whether or not the decoding result includes an interrupt command (S7).

If the verification result in S7 includes an interrupt command (S7: YES), the CPU 1 keeps the state occupied by the interrupt control firmware A in the interrupt hierarchy, and The process shifts to an interrupt process different from the interrupt transfer process (S8), and thereafter, the execution of the program related to the interrupt transfer process ends. In another interrupt process in S8, the CPU 1 can execute a reset process according to the reset command.

In S7, if the interrupt result is not included in the verification result (S7: NO), the CPU 1 shifts to the idle hierarchy and executes the idle control firmware B (S7).
9), various command processes such as an operation waiting process are executed (S10). After that, the CPU 1 ends the execution of the program related to the interrupt transfer processing. In each command processing in S10, the CPU 1
It is possible to execute not only the operation waiting process but also the interrupt process according to the interrupt command, and the state is released from the state occupied only by the interrupt process.

In S5, if the spindle motor 6 is in a stopped state (S5: YES), the CPU 1 rotates the spindle motor 6 (S11), and then proceeds to S6.
Move on to processing.

In S4, if the incomplete transfer of the packet data is obtained as the test result (S4: NO), the CPU 1
Is a state in which the spindle motor 6 is stopped (S1
2) After that, it is detected whether or not a reset factor such as a reset command serving as an interrupt factor has occurred (S13).

Here, in the case of a normal transfer operation in which packet data is transferred from the host 20 immediately after the issuance of the ATAPI command, the transfer is performed in a short time.
The PU1 repeats the operation of S4 in a short time until the transfer of the packet data is completed without detecting the occurrence of the reset factor such as the reset command (S13: NO).

On the other hand, when the start of data transfer is delayed for a considerable time after the issuance of the ATAPI command, the user who determines that the data transfer is abnormal due to the occurrence of a trouble on the data bus or the like issues a reset command or the like by key input. There are cases. Upon receiving the reset command issued in this way, the CPU 1 detects the occurrence of the reset factor based on the reset command while the interrupt transfer process is being executed under the monitoring of the transfer status (S13). : YES), the execution of the interrupt transfer process is stopped based on the detection result, and the process shifts to the reset process (S1).
4). In this reset processing, the CPU 1 is eventually released from the state occupied by the interrupt transfer processing, and restores the original initial state.

In S3, if the command written in the command register is not an ATAPI command, but is, for example, an ATA command (S3: NO), C
PU1 jumps to S7 and executes the subsequent processing.

In S1, when there is no command in the command register (S1: NO), the CPU 1 repeats the determination processing of S1 in the idle layer without shifting to the interrupt layer.

Therefore, the MO having the above configuration and operation is
According to 10, after receiving the ATAPI command from the host 20, it is repeatedly checked whether or not the data transfer from the host 20 has been completed under the monitoring of the transfer status of the packet data. Transfer of the packet data following the ATAPI command from the client may be greatly delayed. In such a situation,
When a reset factor different from the interrupt transfer process using the ATAPI command as an interrupt factor occurs, the process shifts to the reset process according to the reset factor. In other words, when the repetitive operation for verifying the transfer completion under the transfer status monitoring is permanently continued, in order to restore the original operation state from such repetitive operation, for example, a process of issuing a reset command or the like is required. If this is done, the reset command etc. will be transferred to the reset process as another interrupt factor, and the normal key operation can be performed without performing the final measures such as power failure which may cause a failure such as data destruction of the removable storage medium. Recovery processing by input or the like can be performed.

When a reset factor different from the interrupt transfer process is detected, the repetitive operation in the interrupt transfer process is stopped and the process is shifted to another reset process. When restoring to the operation state,
If a reset process such as key input is simply performed, a reset command can be detected even during the interrupt transfer process, and the process can be reliably shifted to the reset process.

Further, when the transfer start of the packet data following the ATAPI command is delayed and the elapsed time until it is determined that the transfer has been completed is prolonged, the CPU 1 sets the S
By repeating the processing of steps S4, S12, and S13, the spindle motor 6 is brought into a stopped state, so that it is possible to save power consumption during the long-time interrupt transfer processing.

Further, the MO 10 and the host 20 shown in FIG.
Another example of the data transfer process between the two will be described with reference to the flowcharts shown in FIGS. Note that the series of processing operations of S1 to S12 shown in the flowchart of FIG. 3 described above are the same in the flowcharts shown in FIGS. 4 and 5 respectively, and thus detailed description thereof will be omitted. 6 regarding the processing operation of the CPU 1
Illustration is omitted in the flowchart.

As a first example, FIG. 4 is a flowchart showing another example of an execution procedure when packet data is transferred according to an ATAPI command. In another example shown in this figure, in brief, the CPU 1 shifts from the state in which the interrupt transfer control firmware A is being executed in the interrupt layer to the lower layer than the interrupt layer in response to the test result of the transfer completion. The state shifts to the idle hierarchy defined at a lower level, and the operation is performed based on the idle control firmware B. The CPU 1 operating based on the idle control firmware B
An interrupt command or the like can be received during state monitoring in the idle layer, and the process can shift to interrupt processing.

More specifically, S24 is a processing operation in the same interrupt hierarchy as that of S4 shown in FIG. 3. In the interrupt hierarchy of S24, the CPU 1 determines whether the completion of the transfer of the packet data is one. Perform only once.

When the incomplete transfer of the packet data is obtained as the test result (S24: NO), the CPU 1
The process shifts to the idle layer whose priority is defined lower than the interrupt layer, and the idle control firmware B is executed (S3).
0), and shifts to a process of monitoring the state of the device (S3).
1).

Subsequently, during the status monitoring process of S31, the CPU 1 checks whether or not an interrupt based on the completion of the transfer of the packet data has occurred as an interrupt factor (S32). This S
The test process of 32 is not executed based on the interrupt control firmware A, but is executed based on the idle control firmware B.

When an interruption of transfer completion occurs (S32:
YES), the CPU 1 proceeds to S25 similar to S6 shown in FIG.
Move to the processing operation.

On the other hand, when the transfer completion interrupt does not occur (S32: NO), the CPU 1 returns to the processing operation after S30 and continues to execute the state monitoring process.

That is, in the case of a normal transfer operation in which packet data is transferred from the host 20 immediately after the issuance of the ATAPI command, the CPU 1 proceeds to the processing operation from S24 to S25, but the transfer of packet data is delayed. The CPU 1 shifts to an idle layer different from the interrupt layer and monitors the state. If an interrupt command such as a reset command is received during this status monitoring, the CP
U1 stops execution of the idle control firmware B, shifts to execution of the interrupt control firmware A, and executes a reset process and the like.

Therefore, according to the MO 10 operating in accordance with the flowchart of FIG. 4, when the test result indicating that the transfer of the packet data is not completed is obtained as another interrupt factor other than the interrupt transfer process by the ATAPI command, Since the process moves to a status monitoring process such as waiting for operation belonging to a different layer from the transfer process and monitors the transfer status of the packet data, various interrupt processes can be performed in the status monitoring process belonging to a different layer from the interrupt. As one type of the interrupt processing, it is possible to perform a repetition test of the transfer completion by the interrupt transfer processing, and to execute a reset processing according to a reset command. That is, since the occupation time of the interrupt processing is shortened and the interrupt occupation rate is reduced, the ATAPI
It is possible to smoothly shift to an interrupt process based on an interrupt command different from the command, and to improve the performance of the entire apparatus by shortening the occupation time of the interrupt process.

In the above-described example of the first execution procedure, the CPU 1 proceeds to S2 without shifting to the interrupt hierarchy.
The processing operation of S30 and subsequent steps may be performed in the idle layer without performing the processing operation of Step 4. A similar effect can be obtained as such an execution procedure.

Next, as a second example, FIG.
11 is a flowchart illustrating another example of an execution procedure when packet data is transferred in response to an I command. In another example shown in FIG.
Performs a packet data transfer completion test repeatedly for a preset time t, and if a transfer completion test result is not obtained even after the time t has elapsed, the priority is defined lower than the interrupt hierarchy. Then, the process shifts to the idle hierarchy, and the same processing operations as those in S30 to S32 shown in FIG.

More specifically, step S44 is a processing operation in the same interrupt hierarchy as step S4 shown in FIG. 3. If the result of the packet data transfer completion test is obtained in step S44 (S44: NO) ), CPU1 is ATA
It is determined whether or not the time t has elapsed since the start of the interrupt transfer process based on the PI command (S50).

If the time t has not elapsed (S50: N
O), the CPU 1 repeatedly executes the transfer completion test until the time t has elapsed. If the time t has elapsed due to the packet data transfer delay during such a repeated test (S50: YES), The CPU 1 shifts to the idle hierarchy defined lower in priority than the interrupt hierarchy and executes the idle control firmware B (S5).
1) The process shifts to processing for monitoring the state of the device (S5).
2).

Subsequently, during the status monitoring process in S52, the CPU 1 checks whether or not an interrupt based on the completion of the transfer of the packet data has occurred as an interrupt factor (S53). Such a series of processing of S51 to S53 is the same processing as S30 to S32 shown in FIG. 4 described above.

When an interruption of transfer completion occurs (S53:
YES), the CPU 1 proceeds to S45 similar to S6 shown in FIG.
Move to the processing operation.

On the other hand, when the transfer completion interrupt does not occur (S53: NO), the CPU 1 returns to the processing operation after S51 and continues to execute the state monitoring processing.

That is, in the case of a normal transfer operation in which packet data is transferred from the host 20 immediately after the issuance of the ATAPI command, the CPU 1 shifts from S44 to S45, but the transfer of packet data is delayed. t
If the transfer is not completed even after the lapse of time, the CPU 1
Is to shift to an idle layer different from the interrupt layer and monitor the state. When an interrupt command such as a reset command is received during the status monitoring, the CPU 1 stops the execution of the idle control firmware B, shifts to the execution of the interrupt control firmware A, and executes a reset process and the like.

Therefore, according to the MO 10 which operates according to the flowchart of FIG. 5, when the elapsed time of the test repeated in the interrupt transfer processing reaches a predetermined time t, the MO 10 is switched to an idle layer different from the interrupt transfer processing. Since the state of the packet data transfer is monitored by shifting to a state monitoring process such as waiting for an operation to belong to, if the transfer of the packet data following the ATAPI command is not completed even after a predetermined time elapses, various types of allocation in the idle layer are performed. Interrupt processing can be performed, and as a type of the interrupt processing, while repetition verification of transfer completion by the interrupt transfer processing is performed, reset processing or the like according to a reset command can be executed. In other words, since the occupation time of the interrupt process is reduced, the interrupt occupancy ratio is reduced, so that it is possible to smoothly shift to the interrupt process based on an interrupt command other than the ATAPI command, and The performance of the entire apparatus can be improved by shortening the occupation time of the interrupt processing.

[0078]

As described above, according to the present invention, after a transfer control command is received from a host, whether or not data transfer with the host has been completed under the monitoring of the data transfer status is repeated. The data transfer following the transfer control command from the host may be significantly delayed during the repeated verification. In such a situation, when an interrupt factor different from the interrupt transfer process using the transfer control command as the interrupt factor occurs, the process shifts to another process according to the other interrupt factor. In other words, if the repetitive operation for verifying the transfer completion under the transfer status monitoring is permanently continued, in order to recover from such repetitive operation to the original operation state, for example, a measure to issue a reset command etc. If this is done, the reset command etc. will be transferred to the reset processing as another interrupt factor, and the normal recovery measures will be performed without the need to take the final measures such as power cut-off that causes a bad situation such as data destruction can do.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a circuit configuration of a magneto-optical disk device having a function as a data transfer control device according to the present invention.

FIG. 2 is an explanatory diagram showing an execution method of a CPU shown in FIG.

FIG. 3 is a flowchart illustrating an example of an execution procedure when packet data is transferred in response to an ATAPI command.

FIG. 4 is a flowchart showing another example of an execution procedure when packet data is transferred in response to an ATAPI command.

FIG. 5 is a flowchart showing another example of an execution procedure when packet data is transferred in response to an ATAPI command.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 ROM 3 RAM 4 External IF 5 Internal IF 6 Spindle motor 7 Head 8 Laser irradiation part 10 Magneto-optical disk unit (MO) 20 Host (Personal computer)

Claims (9)

[Claims] 1. Prior to data transfer with a host, a transfer control command is received from the host, and an interrupt transfer process is executed in accordance with the transfer control command, thereby obtaining a data transfer status. A transfer completion verification means for repeatedly verifying whether or not data transfer with the host has been completed under the monitoring of the data transfer status after receiving the transfer control command. During the repetition test by the transfer completion test means,
A data transfer control device, comprising: a separate process shift unit that shifts to another process according to an interrupt factor different from the interrupt transfer process. 2. The method according to claim 1, wherein the separate process shift means detects a reset factor as another interrupt factor different from the interrupt transfer process, and executes the interrupt transfer process when the reset factor is detected. Abort and proceed to reset processing,
The data transfer control device according to claim 1. 3. The another process shift means receives a transfer incomplete test result obtained by the transfer completion test means as an interrupt factor different from the interrupt transfer process,
2. The data transfer control device according to claim 1, wherein the data transfer control device shifts to an operation waiting process belonging to a different hierarchy from the interrupt transfer process and monitors a data transfer status according to the test result. 4. The another processing shift means measures an elapsed time of the test repeated by the transfer completion verifying means, and when the elapsed time reaches a predetermined time,
Assuming that an interrupt factor different from the above interrupt transfer process occurs,
2. The data transfer control device according to claim 1, wherein the data transfer control device shifts to an operation waiting process belonging to a different hierarchy from the interrupt transfer process and monitors a data transfer status. 5. The transfer completion verification means, after receiving the transfer control command, verifies completion of transfer of fixed-length data transferred subsequent to the transfer control command.
The data transfer control device according to claim 1. 6. The data transfer control device according to claim 1, wherein the transfer control command is a control signal of a command system conforming to the ATAPI standard. 7. Writing / writing to / from a host computer
An optical disc device provided with an interface unit for transmitting and receiving data for reading, wherein the interface unit sets a time interval between a predetermined command transmitted from the host computer and a predetermined length of data following the command. State transition control means having a data transfer control function corresponding to a transfer format that can be arbitrarily set, and transitioning from a data standby state based on reception of the predetermined command to a standby state according to another command; An optical disc device, comprising: 8. The method according to claim 7, wherein the state transition control means validates the reception of another command if no data accompanying the command is received within a predetermined time after the reception of the predetermined command. An optical disk device according to claim 1. 9. The optical disk device according to claim 7, wherein the operation of the drive mechanism of the optical disk device is stopped while waiting for data based on the reception of the predetermined command.