JPH11341356A - Image decoding device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image decoding device which improves a display method of sub-video signal that is superimposed on a main display signal of a DVD (digital video disk) system and suppresses the flickering of the sub-video signal. SOLUTION: This image decoding device consists of a flip-flop circuit FF which latches a display allowable signal Sa with a frame synchronizing signal Sf as a reference signal, an OR gate OR which outputs an OR between the signal Sa inputted in the original timing and a delay signal Sa which is delayed and outputted by the circuit FF, a switching circuit SW which controls the communication and interruption of a sub-video signal Sv, based on a switching control signal Sg outputted from the OR gate OR and a mixer MIX, which synthesizes the signal Sv inputted via the circuit SW with a main video signal Sm and outputs a display video signal Si.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image decoding apparatus, and more particularly, to a digital video disk (Digital Video Disk).
The present invention relates to an image decoding apparatus that superimposes and displays auxiliary video signals (sub-video signals) such as subtitles on an MPEG2 video video signal that is a main video signal in a deo Disc (hereinafter referred to as DVD) system.

[0002]

2. Description of the Related Art In recent years, DVDs have attracted attention as large-capacity storage media capable of storing audio and video information with high image quality and high sound quality.
In particular, various information providing services utilizing the feature of large capacity have been considered. As one of the techniques, there is a technique of combining a main video image with an auxiliary image (sub-video image) such as a caption and displaying it on a screen.

In general, a sub-picture signal in a DVD system is composed of pixel data that has been subjected to a known compression process (Langless compression) in order to handle image data rationally, a display position of the sub-picture signal with respect to a main picture signal, and a display color. And a data unit combining command data strings for controlling display time and the like. The display state and the non-display state of the sub-video signal are set by instructing the display start and end of the pixel data at a predetermined timing based on the display permission signal included in the instruction data sequence, and the main video signal A control method of instantaneously switching between synthesis and non-synthesis to the image is adopted.

FIG. 4 shows a schematic configuration of a conventional image decoding apparatus. As shown in FIG. 4, the image decoding apparatus includes a switch circuit SW that controls transmission and cutoff of the sub-video signal Sv and a switch circuit SW based on the display permission signal Sa included in the command data sequence of the sub-video signal. A video signal synthesizing circuit (mixer) MI that synthesizes the sub video signal Sv ′ transmitted via the main video signal Sm and outputs it as a display video signal Si.
X.

[0005] The operation of such a conventional image decoding apparatus will be described with reference to the timing chart of FIG. As shown in FIG. 5, the display permission signal Sa corresponds to the timing of the clock signal CK for setting the display timing of the image signal on the screen, and the display permission of the sub-video signal Sv (B1, B2) (“1”). Level), display not allowed ("0" level)
Is supplied to the switch circuit SW as a signal level for controlling

The switch circuit SW controls the transmission and cutoff of the sub-video signal Sv to the subsequent stage (mixer MIX) on the basis of the display permission signal Sa to thereby control the display permission period (when the display permission signal Sa is "1"). Level), the sub-video signal Sv '(B1, B2) is output. The mixer MIX outputs the main video signal Sm (A) and the sub video signal S only during the period when the sub video signal Sv ′ is output from the switch circuit SW.
v ′ (B1, B2) and a synthesized signal (A
+ B1, A + B2) as the display video signal Si. Here, the display non-permission period (when the display permission signal Sa is “
At “0” level), the switch circuit SW cuts off the transmission of the sub video signal Sv (B1, B2), so that the signal mixing process by the mixer MIX is not performed, and the main video signal Sm
Only (A) is output as the display video signal Si.

[0007]

In the above-described image decoding apparatus, in the case of subtitle information as sub-picture signals, particularly information that is statically displayed on a screen such as a counter display, as shown in FIG. In general, a control method of setting the signal Sa to a display non-permission state (“0” level) for a predetermined time (one frame period in the figure, but arbitrarily set) in response to the switching of the sub-video signal Sv. Has been adopted.

In such a control method, since the state setting is controlled in synchronization with the display permission signal Sa in synchronization with the clock signal CK, the image displayed on the screen is instantaneously (one frame period). No signal is displayed,
Even if the period during which the sub-video signal is not displayed is an extremely short period of about 1/30 second (one frame period), there is a problem that the human perceives the image flickering when switching the counter display. I have.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an image decoding apparatus which solves the above problems, improves a method of displaying a sub-picture signal superimposed on a main display signal of a DVD system, and suppresses flicker of the sub-picture signal. And

[0010]

In order to achieve the above object, an image decoding apparatus according to the first aspect of the present invention provides a display for controlling display and non-display of a sub-video image synthesized and displayed on a screen. Delay means for delaying the permission signal by a predetermined time based on the frame synchronization signal, and transmission of a sub-video signal for generating the sub-video image based on an output signal from the delay means;
Switch means for controlling cutoff, the sub-video signal transmitted via the switch means, and a video signal synthesis means for synthesizing a main video signal for generating the main video image, and outputting as a display video signal, It is characterized by having.

According to a second aspect of the present invention, in the image decoding apparatus according to the first aspect, the delay means sets a timing of switching the sub-picture image from the display state to the non-display state by the following timing. It is characterized in that it is delayed so as to coincide with the display timing of the sub-picture image. That is, the image decoding apparatus of the present invention includes a delay unit circuit for delaying the fall of the display permission signal from the display permission state to the display non-permission state for an arbitrary frame period, and delays the release timing of the display permission state by a predetermined time. It is characterized by the following.

In this case, instead of simply delaying the change in the state of the display permission signal as a whole, the timing for switching to the display permission state is the same as that for maintaining the original timing of the display permission signal and switching to the display non-permission state. Is delayed, it is possible to prevent occurrence of a state in which the sub-image signal is not instantaneously displayed (non-display period), and to suppress unnatural flicker.

If the time from when the display permission signal changes to the display non-permission state to when the display permission signal returns to the display permission state is sufficiently long, the timing of switching to the display non-permission state is set to several frames as in the present invention. Even if delayed for a period,
There is no visual perception of flicker on the screen display.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An image decoding apparatus according to the present invention will be described below with reference to embodiments. One embodiment of an image decoding device according to the present invention will be described with reference to FIG. The same components as those in FIG. 4 are denoted by the same reference numerals. As shown in FIG. 1, the image decoding apparatus according to the present embodiment includes a flip-flop circuit FF and an OR gate OR constituting a delay unit, and a switch circuit S constituting a switch unit.
W and a mixer MIX constituting a video signal synthesizing means.

The flip-flop circuit FF latches the display enable signal Sa using the frame synchronization signal Sf for setting the display timing of the image signal on the screen as a reference signal, and after a predetermined delay time elapses, The delay signal Sa 'is output to the OR gate OR. The OR gate OR outputs the display permission signal S input at the original timing.
a is ORed with a delay signal Sa ′ output after a predetermined time delay by the flip-flop circuit FF, and output as a switching control signal Sg of the switch circuit SW.

That is, the display permission signal Sa and the delay signal S
at least one of a 'is at "H" level ("1" level)
At this time, an "H" level switching control signal Sg is output. The switch circuit SW outputs the sub-video signal Sv based on the switching control signal Sg output from the OR gate OR.
To the mixer MIX. That is, when the switching control signal Sg is at “H” level, the sub-video signal Sv is transmitted to the mixer MIX, and when it is at “L” level, the transmission of the sub-video signal Sv is cut off.

The mixer MIX performs a signal synthesizing process for synthesizing the main video signal Sm and the sub video signal Sv 'input via the switch circuit SW, and converts the display video signal Si to an image display device (not shown). Output. That is, the main video signal Sm and the sub video signal Sv 'are synthesized only when the switching control signal Sg is at the "H" level, and the main video signal Sm is displayed without performing the signal synthesis process when the switching control signal Sg is at the "L" level. Output as a video signal Si.

Next, a signal processing state of the image decoding apparatus according to the present embodiment will be described with reference to a timing chart (part 1) of FIG. First, the display permission signal Sa included in the command data sequence of the sub-video signal is taken in and held by the flip-flop circuit FF based on the frame synchronization signal Sf defining the start timing of each frame, and the OR gate OR Is applied to one of the inputs. Then, after being held in the flip-flop circuit FF for a predetermined delay time (one frame period in this embodiment), the delay time is applied to the other input of the OR gate OR as a delay signal Sa ′.

Accordingly, an input signal whose rising and falling timings are both shifted by one frame period is applied to the OR gate OR, and at least one of the display permission signal Sa and the delay signal Sa 'is "".
If it is at the H level, the switching control signal Sg at the "H" level is output to the switch circuit SW. That is, when the display permission signal Sa switches to the display non-permission state, one of the inputs to the OR gate OR becomes Although the level is switched to the “0” level, the delay signal Sa ′ from the flip-flop circuit FF is delayed by one frame period and is switched to the “0” level, so that the “H” level switching control signal Sg output to the switch circuit SW. Are set longer by one frame period.

Next, the switch circuit SW is turned ON while the switching control signal Sg at the “H” level is being input.
And enters the sub video signal Sv ′ (B) into the mixer MI.
Transmit to X. Therefore, the mixer MIX outputs the main video signal Sm (A) and the main video signal Sm (A) based on the mixing ratio specified by the instruction data string in the data unit while the switching control signal Sg of “H” level is being input to the switch circuit. A signal synthesizing process with the sub-image signal Sv ′ (B) is performed, and the synthesized signal (A + B) is output as the display image signal Si.

On the other hand, the transmission of the sub-picture signal Sv (B) to the mixer MIX is interrupted while the switch control signal Sg of the “L” level is being input to the switch circuit SW. Main video signal Sm
(A) is output as the display video signal Si. As described above, according to the image decoding apparatus of the present embodiment, only the fall timing of the display permission signal Sa is delayed by the predetermined time by the flip-flop circuit FF and the OR gate OR, and thus the sub-picture signal The display permission state can be set longer, for example, for one frame period, and the synthesizing process of the main video signal Sm and the sub video signal Sv is executed for one frame period.

The above-mentioned display permission signal Sa is controlled at "1" (display permission state) and "0" (display non-permission state) at the timing specified by the instruction data string in the data unit. Next, a signal processing state when the image decoding apparatus of the present embodiment is applied to flicker prevention will be described with reference to a timing chart (No. 2) of FIG. The description of the signal processing state equivalent to that of the timing chart shown in FIG. 2 is omitted.

As shown in FIG. 3, the display permission signal Sa is
When the sub video signal Sv is switched (B1 → B2), 1
It is assumed that the display period has a frame non-permission period, and a delay time for one frame period corresponding to the display non-permission period is set in the flip-flop circuit FF in advance. In this case, when the display permission signal Sa rises and indicates the "1" level to enter the display permission state, the switch circuit S is synchronized with the rise timing of the display permission signal Sa, as in the timing chart of FIG.
W is turned on, and the mixer MIX performs a process of synthesizing the main video signal Sm (A) and the sub video signal Sv ′ (B1).

On the other hand, the display permission signal Sa falls and "
When the display is in the display non-permitted state by indicating the 0 "level, the signal combining process by the mixer MIX is maintained for one frame period set by the flip-flop circuit FF, and the main video signal Sm (A) and the sub-video signal Sv 'are maintained. The combined signal (A + B1) with (B1) is output as the display video signal Si.

When the display permission signal Sa rises again and enters the display permission state, the switch circuit SW continues the ON state, but the sub-picture signal Sv switches synchronously (B1 → B2). Synthesis processing of the main video signal Sm (A) and the sub video signal Sv '(B2) is continuously performed, and the synthesized signal (A + B2) is output as the display video signal Si.

Therefore, in the flip-flop circuit FF, by setting the delay time according to the display non-permission period of the display permission signal Sa to an arbitrary value (for several frame periods), the display time of the sub-video signal Sv can be reduced by a predetermined time. Since the length can be increased, a substantially continuous display of the sub-video signal can be realized without generating a non-display period accompanying the switching of the display of the sub-video signal Sv, and flickering of the screen display can be prevented. it can.

In this embodiment, one frame period is set as the delay time set in the flip-flop circuit FF. However, the present invention is not limited to this. By connecting a plurality of stages, the delay time can be set to a desired plurality of frame periods. In addition, although the circuit configuration using the flip-flop circuit FF as the delay unit has been described, it goes without saying that the same signal processing as described above can be realized by applying a delay circuit using a counter.

Further, in the above-described embodiment, as for the state set by the display permission signal Sa, when the level is "1", the display is permitted, and when the level is "0", the display is not permitted. Although the logical output by OR is used as the switching control signal Sg of the switch circuit SW,
It goes without saying that the same signal processing as described above is realized even if the state by the display permission signal Sa is set such that the output of the AND gate is used for the switching control signal Sg.

[0029]

As described above, according to the image decoding apparatus of the present invention, the delay means circuit for delaying the fall of the display permission signal from the display permission state to the display non-permission state by an arbitrary frame period is provided. The timing for switching to the display permission state can be set so that the original timing of the display permission signal is maintained as it is and only the timing for switching to the display non-permission state is delayed, so that the sub-image signal is not displayed instantaneously. (Non-display period) can be prevented, and unnatural flickering of the screen display can be suppressed.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing an embodiment of an image decoding device according to the present invention.

FIG. 2 is a timing chart (part 1) illustrating a signal processing state of the image decoding apparatus according to the present embodiment.

FIG. 3 is a timing chart (part 2) illustrating a signal processing state of the image decoding apparatus according to the present embodiment.

FIG. 4 is a schematic configuration diagram illustrating an image decoding device according to a conventional technique.

FIG. 5 is a timing chart showing a signal processing state of the image decoding device according to the related art.

[Explanation of symbols]

 FF flip-flop circuit OR OR gate SW switch circuit MIX mixer Sa display enable signal Sf frame synchronization signal Sv sub-video signal Sm main video signal Si display video signal

Claims (2)

[Claims] 1. A delay means for delaying a display permission signal for controlling display and non-display of a sub video image synthesized and displayed on a screen with a main video image for a predetermined time based on a frame synchronization signal; A switch means for controlling transmission and blocking of a sub-picture signal for generating the sub-picture image based on an output signal from the means, and the sub-picture signal transmitted through the switch means;
An image decoding apparatus, comprising: a video signal synthesizing unit that synthesizes a main video signal for generating the main video image and outputs the synthesized video signal as a display video signal. 2. The method according to claim 1, wherein the delay unit sets a timing at which the sub-video image is switched from the display state to the non-display state.
2. The image decoding apparatus according to claim 1, wherein a delay is made so as to coincide with a display timing of the next sub-picture image.