JPH11341308A - Image quality adjustment circuit - Google Patents
Image quality adjustment circuitInfo
- Publication number
- JPH11341308A JPH11341308A JP10147023A JP14702398A JPH11341308A JP H11341308 A JPH11341308 A JP H11341308A JP 10147023 A JP10147023 A JP 10147023A JP 14702398 A JP14702398 A JP 14702398A JP H11341308 A JPH11341308 A JP H11341308A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- crt
- video signal
- blanking pulse
- amplitude
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、CRTを用いた表
示装置の画質調整回路に係り、特に、画質改善を行う手
段を設けた画質調整回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image quality adjusting circuit for a display device using a CRT, and more particularly to an image quality adjusting circuit provided with a means for improving image quality.
【0002】[0002]
【従来の技術】従来の画質調整回路は、図3に示すよう
に、入力の赤、緑、青の原色信号から輝度信号を形成す
るマトリクス回路と、このマトリクス回路から選られる
輝度信号から輪郭補正信号を形成する信号形成回路を設
け、この信号形成から得られる輪郭補正信号を入力の
赤、緑、青の原色信号に合成する回路方式をとり、ブラ
ンキングパルスの振幅(V1)が前段増幅回路105に
印加される基準電圧(V1)と同じとなるよう前段増幅
回路105の内部で処理され、後段増幅回路6が前段増
幅回路105から出力された信号bを反転増幅し、後段
増幅回路6で反転増幅された信号cをCRT8を駆動す
るために必要なDC電位を付加するDC再生回路7を通
し、CRT8に印加して映像信号dが表示される。2. Description of the Related Art As shown in FIG. 3, a conventional image quality adjusting circuit comprises a matrix circuit for forming a luminance signal from input red, green and blue primary color signals, and a contour correction from a luminance signal selected from the matrix circuit. A signal forming circuit for forming a signal is provided, and an outline correction signal obtained from the signal formation is combined with an input primary color signal of red, green, and blue, and the amplitude (V1) of the blanking pulse is adjusted by a preamplifier circuit. The signal is processed inside the pre-amplifier circuit 105 so as to be equal to the reference voltage (V1) applied to the signal 105, and the post-amplifier circuit 6 inverts and amplifies the signal b output from the pre-amplifier circuit 105. The inverted and amplified signal c is applied to the CRT 8 through a DC reproducing circuit 7 for applying a DC potential necessary for driving the CRT 8, and a video signal d is displayed.
【0003】[0003]
【発明が解決しようとする課題】従って、従来の画質調
整回路は、表示する映像信号に応じて信号処理を施すこ
とで鮮鋭度が増すことが知られ、この信号処理を施すこ
とは高周波の映像信号ラインに回路を構成するため、回
路構成が複雑なになることと、映像信号の赤、緑、青の
3色分の回路構成が必要なために高価となる課題があっ
た。Therefore, it is known that the conventional image quality adjustment circuit increases the sharpness by performing signal processing in accordance with the video signal to be displayed. There is a problem that the circuit configuration is complicated because the circuit is configured on the signal line, and that the circuit configuration for three colors of red, green, and blue of the video signal is expensive because the circuit configuration is required.
【0004】そこで本発明の目的は、複雑で高価な回路
構成をとらずに映像増幅回路のDC電位を制御するのみ
ので廉価な画質調整回路を提供することである。SUMMARY OF THE INVENTION An object of the present invention is to provide an inexpensive image quality adjustment circuit which only controls the DC potential of a video amplifier circuit without taking a complicated and expensive circuit configuration.
【0005】[0005]
【課題を解決するための手段】上述の課題を解決するた
めに、本発明の画質調整回路は、同期信号に基づいてホ
ストシステムから送出された映像信号を表示するCRT
と、このCRTで表示される映像信号の同期信号からブ
ランキングパルスを発生するブランキングパルス発生回
路と、このブランキングパルス発生回路から発生された
ブランキングパルスの振幅を制御して上記映像信号を付
加し、かつ増幅する前段増幅回路と、この前段増幅回路
で増幅された映像信号を上記CRTの駆動に必要なレベ
ルへ増幅する後段増幅回路と、この後段増幅回路で増幅
された映像信号を上記CRTの駆動に最適なDC電位に
設定するDC再生回路と、予め可変手段に設定されたパ
ラメータに基き、上記ブランキングパルスの振幅及びD
C電位を制御するよう上記前段増幅回路及びDC再生回
路を制御する制御回路とで構成されたことを特徴とす
る。In order to solve the above-mentioned problems, an image quality adjustment circuit according to the present invention comprises a CRT for displaying a video signal transmitted from a host system based on a synchronization signal.
A blanking pulse generating circuit for generating a blanking pulse from a synchronizing signal of the video signal displayed on the CRT; and controlling the amplitude of the blanking pulse generated by the blanking pulse generating circuit to convert the video signal. A pre-amplifier circuit for adding and amplifying, a post-amplifier circuit for amplifying the video signal amplified by the pre-amplifier circuit to a level required for driving the CRT, and a video signal amplified by the post-amplifier circuit A DC regeneration circuit for setting a DC potential optimal for driving the CRT, and the amplitude of the blanking pulse and D
The control circuit controls the preamplifier circuit and the DC regeneration circuit so as to control the C potential.
【0006】[0006]
【発明の実施の形態】次に、本発明の一実施の形態によ
る画質調整回路を図面を参照して説明する。Next, an image quality adjusting circuit according to an embodiment of the present invention will be described with reference to the drawings.
【0007】図1は、本発明の一実施の形態による画質
調整回路のブロック構成図(A)及び輪郭補正信号波形
図(B)である。FIG. 1 is a block diagram (A) of an image quality adjusting circuit and a waveform diagram (B) of an outline correction signal according to an embodiment of the present invention.
【0008】図2は、本発明の一実施の形態による画質
調整回路の画像信号波形図である。FIG. 2 is an image signal waveform diagram of the image quality adjusting circuit according to one embodiment of the present invention.
【0009】本発明の一実施の形態による画質調整回路
は、図1に示すように、同期信号に基づいてホストシス
テム1から送出された映像信号を表示するCRT8と、
このCRT8で表示される映像信号の同期信号からブラ
ンキングパルスを発生するブランキングパルス発生回路
2と、このブランキングパルス発生回路2から発生され
たブランキングパルスの振幅を制御して映像信号を付加
し、かつ増幅する前段増幅回路5と、この前段増幅回路
5で増幅された映像信号をCRT8の駆動に必要なレベ
ルへ増幅する後段増幅回路6と、この後段増幅回路6で
増幅された映像信号をCRT8の駆動に最適なDC電位
に設定するDC再生回路7と、予め可変手段3に設定さ
れたパラメータに基き、ブランキングパルスの振幅及び
DC電位を制御するよう前段増幅回路5及びDC再生回
路7を制御する制御回路4とで構成される。As shown in FIG. 1, a picture quality adjusting circuit according to an embodiment of the present invention includes a CRT 8 for displaying a video signal transmitted from a host system 1 based on a synchronization signal,
A blanking pulse generating circuit 2 for generating a blanking pulse from a synchronizing signal of a video signal displayed on the CRT 8 and a video signal added by controlling the amplitude of the blanking pulse generated from the blanking pulse generating circuit 2 Amplifying circuit 5 for amplifying and amplifying the video signal, amplifying the video signal amplified by the amplifying circuit 5 to a level necessary for driving the CRT 8, and a video signal amplified by the amplifying circuit 6 Regeneration circuit 7 for setting the DC potential to the optimal DC potential for driving the CRT 8, and a preamplifier circuit 5 and a DC regeneration circuit for controlling the amplitude of the blanking pulse and the DC potential based on the parameters set in advance in the variable means 3. And a control circuit 4 for controlling the control circuit 7.
【0010】次に、本発明の一実施の形態による画質調
整回路の動作を図面を参照して説明する。Next, the operation of the image quality adjustment circuit according to one embodiment of the present invention will be described with reference to the drawings.
【0011】本発明の一実施の形態による画質調整回路
の動作は、図1及び図2に示すよう、まず第1に可変手
段3から制御回路4を通して図3に示す前段増幅回路5
の制御電圧V1の電圧を高くすると、図3に示す波形b
がブランキングパルスの振幅が増大して図2のb1の点
線から実線のようになり、これは後段増幅回路6に入力
される映像信号部分のDC成分が高くなるので、出力さ
れた図2のc1の映像部分は図1(B)の波形2の傾向
を示す、しかしブランキングパルスの振幅を増大したま
までは、図1のdのCRT8のグリット1に対するカソ
ードの映像信号が図2のc1のV2電圧分近づいて輝度
が高くなるため、所定輝度を保つためには、V2分を図
2のd1に示すようにDC再生回路7でDC電圧を持ち
上げるように制御回路4で同時に行う。As shown in FIGS. 1 and 2, the operation of the image quality adjustment circuit according to one embodiment of the present invention is as follows. First, the preamplifier circuit 5 shown in FIG.
When the voltage of the control voltage V1 is increased, the waveform b shown in FIG.
2, the amplitude of the blanking pulse increases and the solid line changes from the dotted line of b1 in FIG. 2 to the solid line. This is because the DC component of the video signal input to the post-amplifying circuit 6 increases, and the output of FIG. The image portion of c1 shows the tendency of the waveform 2 of FIG. 1B, but with the amplitude of the blanking pulse increased, the video signal of the cathode for the grid 1 of the CRT 8 of FIG. Since the luminance increases as the voltage approaches the voltage V2, the control circuit 4 simultaneously increases the voltage V2 by the DC regeneration circuit 7 so as to increase the DC voltage as shown by d1 in FIG.
【0012】一方、可変手段3から制御回路4を通じて
図3に示す前段増幅回路5のV1の電圧を低くすると、
図3の波形bはブランキングパルスの振幅が減少し図2
のb2の点線から実線のようになり、これは後段増幅回
路6に入力される映像信号のDC成分が低くなるので、
出力された図2のc2の映像部分は図(B)の波形2の
傾向を示す、しかしブランキングパルスの振幅を小さく
したままでは、図1のdのCRT8のグリット1に対す
るカソードの映像信号が図2のc2のV3電圧分遠くな
って輝度が低くなるため、所定輝度を保つには、V2分
を図2のd2に示すようにDC再生回路7でDC電圧を
下げるように制御回路で同時に行う。On the other hand, when the voltage V1 of the preamplifier circuit 5 shown in FIG.
Waveform b in FIG. 3 shows that the amplitude of the blanking pulse is reduced and FIG.
From the dotted line of b2 to a solid line. This is because the DC component of the video signal input to the post-amplifying circuit 6 becomes low.
The output image portion of c2 in FIG. 2 shows the tendency of the waveform 2 in FIG. 2B, but if the amplitude of the blanking pulse is kept small, the video signal of the cathode with respect to the grid 1 of the CRT 8 in FIG. Since the luminance decreases as the voltage becomes longer by the voltage V3 of c2 in FIG. 2, in order to maintain the predetermined luminance, the voltage V2 is simultaneously reduced by the control circuit so that the DC voltage is reduced by the DC regeneration circuit 7 as shown by d2 in FIG. Do.
【0013】[0013]
【発明の効果】以上説明したように、本発明の画質調整
回路によれば、映像増幅回路のDC電位の制御で画質調
整を行うことができるため、回路構成が簡単でかつ廉価
に実現できる効果がある。As described above, according to the image quality adjusting circuit of the present invention, since the image quality can be adjusted by controlling the DC potential of the image amplifying circuit, the circuit configuration is simple and inexpensive. There is.
【図1】本発明の一実施の形態による画質調整回路のブ
ロック構成図(A)及び輪郭補正信号波形図(B)であ
る。FIG. 1A is a block diagram of an image quality adjustment circuit according to an embodiment of the present invention, and FIG.
【図2】本発明の一実施の形態による画質調整回路の映
像信号波形図である。FIG. 2 is a video signal waveform diagram of the image quality adjustment circuit according to one embodiment of the present invention.
【図3】従来の画質調整回路のブロック構成図である。FIG. 3 is a block diagram of a conventional image quality adjustment circuit.
1 ホストシステム 2 ブランキングパルス発生回路 3 可変手段 4 制御回路 5 前段増幅回路 6 後段増幅回路 7 DC再生回路 8 CRT REFERENCE SIGNS LIST 1 host system 2 blanking pulse generation circuit 3 variable means 4 control circuit 5 preamplifier circuit 6 postamplifier circuit 7 DC regeneration circuit 8 CRT
Claims (1)
送出された映像信号を表示するCRTと、このCRTで
表示される映像信号の同期信号からブランキングパルス
を発生するブランキングパルス発生回路と、このブラン
キングパルス発生回路から発生されたブランキングパル
スの振幅を制御して上記映像信号を付加し、かつ増幅す
る前段増幅回路と、この前段増幅回路で増幅された映像
信号を上記CRTの駆動に必要なレベルへ増幅する後段
増幅回路と、この後段増幅回路で増幅された映像信号を
上記CRTの駆動に最適なDC電位に設定するDC再生
回路と、予め可変手段に設定されたパラメータに基き、
上記ブランキングパルスの振幅及びDC電位を制御する
よう上記前段増幅回路及びDC再生回路を制御する制御
回路とで構成されたことを特徴とする画質調整回路。1. A CRT for displaying a video signal transmitted from a host system based on a synchronization signal, a blanking pulse generation circuit for generating a blanking pulse from a synchronization signal of the video signal displayed on the CRT, A pre-amplifier circuit for adding and amplifying the video signal by controlling the amplitude of a blanking pulse generated from a blanking pulse generation circuit, and a video signal amplified by the pre-amplifier circuit are required for driving the CRT. Based on a parameter set in advance in a variable means, a DC reproduction circuit for setting the video signal amplified by the latter amplification circuit to a DC potential optimal for driving the CRT,
An image quality adjustment circuit, comprising: a control circuit that controls the preamplifier circuit and the DC reproduction circuit so as to control the amplitude of the blanking pulse and the DC potential.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10147023A JPH11341308A (en) | 1998-05-28 | 1998-05-28 | Image quality adjustment circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10147023A JPH11341308A (en) | 1998-05-28 | 1998-05-28 | Image quality adjustment circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH11341308A true JPH11341308A (en) | 1999-12-10 |
Family
ID=15420806
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10147023A Withdrawn JPH11341308A (en) | 1998-05-28 | 1998-05-28 | Image quality adjustment circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH11341308A (en) |
-
1998
- 1998-05-28 JP JP10147023A patent/JPH11341308A/en not_active Withdrawn
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20050802 |