JPH11341030A - Repeating device and repeating method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute data transmitting process and receiving process in parallel independently of the receiving timing of data. SOLUTION: A receiving means 1 receives a bit stream. A start code detection means 2 detects a start code from the bit stream. A 1st timing signal generation means 3 is initialized when the start code is detected and then generates a 1st timing signal to be activated in one symbol period. A sampling means 4 samples the bit stream synchronously with the 1st timing signal. A 1st storage means stores acquired data. A reading means 7 reads out data to be transmitted from a 2nd storage means 6. A 2nd timing signal generation means 8 generates a 2nd timing signal to be activated in one symbol period. A transmitting means 10 transmits the read data synchronously with the 2nd timing signal. When self-data are not transmitted, a synchronizing means 9 synchronizes the 2nd timing signal with the 1st timing signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a relay apparatus and a recording medium, and more particularly, to a bit stream which is composed of a plurality of symbols and transmitted over a network in units of a frame having a start code added to the head. The present invention relates to a relay device that relays and a recording medium that stores a program that causes a computer to execute such relay processing.

[0002]

2. Description of the Related Art For example, a LAN (Local Area Network)
When connecting to each other, it is necessary to use a relay device.

For example, when relaying data transmitted in units of a frame to which a start code and an end code are added by using such a relay device, reception and relay processing are performed simultaneously with detection of the start code. It is known to start and end the above processing upon detection of the end code of the frame.

[0004]

By the way, in the above-described conventional relay device, the reception processing and the transmission processing are performed at the same timing, and therefore, for example, when another data is received while data is being transmitted. Therefore, when the data reception timing is not synchronized with the data transmission timing, the reception operation cannot be performed.

In particular, in a ring network, data transmitted by a relay device returns after a predetermined time has elapsed, so that transmission processing and reception processing must be performed simultaneously. However, the time until the transmitted data returns is not constant depending on the system configuration and the state of the system, so that the transmission and reception timings do not match, and it is difficult to relay data. Was.

The present invention has been made in view of such a point, and regardless of the input timing of received data,
An object of the present invention is to provide a relay device capable of simultaneously performing a transmission process and a reception process.

[0007]

According to the present invention, in order to solve the above-mentioned problems, a bit stream which is composed of a plurality of symbols and is transmitted over a network in units of a frame having a start code added to the head thereof. Receiving means for receiving the bit stream, start code detecting means for detecting the start code from the bit stream received by the receiving means, and a start code detected by the start code detecting means. Is initialized when it is set, and thereafter becomes active in one symbol period.
First timing signal generating means for generating a timing signal of; and sampling means for sampling the bit stream in synchronization with the first timing signal;
First storage means for storing data obtained by the sampling means, second storage means for storing data to be transmitted, and read means for reading data to be transmitted from the second storage means A second timing signal generating means for generating a second timing signal which is referred to when transmitting data read by the reading means and becomes active in one symbol period; Transmitting means for transmitting the received data in synchronization with the second timing signal; and transmitting the second data when the own data is not transmitted.
Synchronizing means for synchronizing the second timing signal generated by the timing signal generating means with the first timing signal generated by the first timing signal generating means. Provided.

[0008] Here, the receiving means receives the bit stream. The start code detecting means detects a start code from the bit stream received by the receiving means. The first timing signal generating means is initialized when the start code is detected by the start code detecting means, and thereafter generates a first timing signal which becomes active in one symbol period. The sampling means samples the bit stream in synchronization with the first timing signal. The first storage unit stores data obtained by the sampling unit. The second storage means stores data to be transmitted. The reading means reads data to be transmitted from the second storage means. The second timing signal generating means is referred to when transmitting the data read by the reading means, and generates a second timing signal which becomes active in one symbol period. The transmitting means transmits the data read by the reading means in synchronization with the second timing signal. The synchronization means synchronizes the second timing signal generated by the second timing signal generation means with the first timing signal generated by the first timing signal generation means when the own data is not transmitted. Let it.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a principle diagram for explaining the principle of the present invention. As shown in this figure, the relay apparatus of the present invention comprises a receiving unit 1, a start code detecting unit 2, a first timing signal generating unit 3, a sampling unit 4, a first storing unit 5, a second storing unit 6. , Reading means 7, second
Timing signal generating means 8, synchronizing means 9, transmitting means 1
0 and the direct supply means 11.

[0010] The receiving means 1 receives a bit stream transmitted via a network. The start code detecting means 2 detects a start code from the bit stream received by the receiving means 1.

The first timing signal generating means 3 is initialized when the start code is detected by the start code detecting means 2, and thereafter generates a first timing signal which becomes active in one symbol cycle.

The sampling means 4 samples the bit stream in synchronization with the first timing signal.
The first storage unit 5 stores data obtained by the sampling unit.

The second storage means 6 stores data to be transmitted. The reading means 7 reads data to be transmitted from the second storage means 6.

The second timing signal generating means 8 generates a second timing signal which is referred to when transmitting the data read by the reading means 7 and becomes active in one symbol period.

The transmitting means 10 transmits the data read by the reading means 7 in synchronization with the second timing signal. The synchronizing means 9 transmits the second timing signal generated by the second timing signal generating means 8 to the first timing generated by the first timing signal generating means 3 when the own data is not transmitted. Synchronize with signal.

When relaying data, the direct supply means 11 receives the start code detected by the start code detection means 2 and delays the bit stream received by the reception means 1 by the start code. , To the transmitting means 10 for direct transmission.

Next, the operation of the principle diagram of the present invention will be described. Hereinafter, the structure of the data to be processed by the relay device shown in FIG. 1 will be described with reference to FIG. 2, and then the operation will be described with reference to the timing chart shown in FIG.

FIG. 2 is a diagram showing an example of the structure of data (frame) to be processed by the relay device shown in FIG. As shown in this figure, a frame includes a start delimiter (SD) section, a data (DT) section, a frame check sequence (FCS) section, and an end delimiter (E).
D).

The start delimiter section is a start code composed of two symbols each having 5 bits. The frame is classified into two according to the combination of the symbols included in the start delimiter. That is, there are two types of frames: a frame including the symbol “J” and the symbol “K” (FIG. 2A) and a frame including the symbol “J” and the symbol “J” (FIG. 2B).

Next, the operation of the principle diagram shown in FIG. 1 will be described. FIG. 3 is a timing chart showing the operation of the principle diagram shown in FIG. Now, it is assumed that the relay device is transmitting predetermined data stored in the second storage unit 6. In that case, the data stored in the second storage means 6 is read out by the reading means 7 and
Supplied to

The transmitting means 10 receives a second timing signal (FIG. 3) generated by the second timing signal generating means 8.
(D)) is transmitted in synchronization with the timing when (D) becomes active (in this example, the state of “H”). As a result, data is transmitted from the transmitting means 10 in symbol units as shown in FIG. In this example, the data part (DT) is transmitted in the periods P1 to P8, and in the period P9, the frame check sequence part (F
CS), and in periods P10 and P11, an end delimiter unit (ED) is transmitted. Note that FIG.
In FIG. 5, the data structure is partially simplified for simplicity.

During the transmission of data,
As shown in FIG. 3A, if a frame having a shift of シ ン ボ ル symbol is received, the receiving unit 1 supplies the received signal (FIG. 3A) to the start code detecting unit 2.

When the start code detecting means 2 detects a start code (start delimiter in this example) included in the received signal, the first timing signal generating means 3
Initializes the first timing signal. In this example, the start code is received in the periods P3 to P5, and the first timing signal is initialized and synchronized with the received signal in the period P6.

When the start code is detected, the sampling means 4 samples the received signal in synchronization with the first timing signal, and starts processing for supplying the sampled signal to the first storage means 5. As a result, the received data is sequentially stored in a predetermined area of the first storage unit 5.

Even after the reception processing is completed, the first timing signal generation means 3 continues to generate the first timing signal at the same timing as during reception. When the transmission processing of the data stored in the second storage means 6 is completed (FIG. 3B)
Period P11), the synchronization means 9 outputs the second timing signal generated by the second timing signal generation means 8 to the first timing signal.
Synchronize with the timing signal. As a result, FIG.
, The first and second timing signals are synchronized.

As described above, in the relay apparatus of the present invention, the transmission processing and the reception processing can be performed in parallel regardless of the data reception timing. When performing the data relay processing, the data supplied by the receiving means 1 is delayed by two symbols by the direct supplying means 11 and then supplied to the transmitting means 10 for transmission.

According to such processing, the received data can be relayed with a minimum delay. In FIG. 1, the first storage unit 5 and the second storage unit 6 have different configurations, but they may have the same configuration.

Next, an embodiment of the present invention will be described with reference to FIG. FIG. 4 is a diagram illustrating a configuration example of the embodiment of the present invention. In this figure, the relay devices 20-1 and 20-2
0-4 are interconnected by networks 21-1 to 21-4, and the relay device 20-1 → the relay device 20
Data is transmitted in the order of -2 → relay device 20-3 → relay device 20-4.

FIG. 5 is a block diagram showing a detailed configuration example of the relay device 20 shown in FIG. In this figure, CP
A U (Central Processing Unit) 20a performs various arithmetic processes and controls each unit of the apparatus.

The ROM (Read Only Memory) 20b stores C
It stores basic programs and data executed by the PU 20a. RAM (Random Access Memory) 20c
When the CPU 20a executes various arithmetic processing and control processing, it temporarily stores data in the middle of an arithmetic operation and a program being executed.

The image driver 20d generates bitmap data corresponding to the character code or graphic code supplied from the CPU 20a, and outputs a video signal corresponding to the bitmap data to the display device 30.

The display device 30 is, for example, a CRT (Cathod).
(E Ray Tube) monitor, etc., and displays and outputs the image signal supplied from the image drive unit 20d. H
The DD (Hard Disk Drive) 20e is an OS (Operating
System) and application software.

The interface 20f is connected to the transmitting / receiving unit 20.
h, data is exchanged with each other. The bus 20g connects the CPU 20a and other devices, and transmits data between them.

The transmission / reception unit 20h receives data transmitted through the network and transmits data to the network. In addition, this transmission / reception part 20h
A process corresponding to the physical layer that is the lowest layer of the communication protocol is performed.

FIG. 6 is a block diagram showing a detailed configuration example of the transmitting / receiving section 20h shown in FIG. In this figure, a shift register 40 is a 10-bit register, and shifts bit data input to the 0th bit one bit at a time in synchronization with a clock signal (not shown). When the data reaches the ninth bit, the data is discarded at the next clock. The 0th to 9th bits of data stored in the shift register 40 are output as 10-bit parallel data.

The decoder 41 sets the SD signal to "H" when the parallel data output from the shift register 40 is a start code, and otherwise sets the SD signal to "L". That is, when a frame is received and a start code portion of the frame is detected, the state is set to “H”.

The decoder 42 sets the ED signal to an "H" state when the data output from the shift register 40 includes an end code, and otherwise to an "L" state. That is, when a frame is received from the network and the end code part of the frame is detected, the state is set to “H”.

The relay control unit 43 receives the SD signal and the TXS
With reference to an EL signal (described later), an RSYM signal referred to when performing a receiving process and a TSYM signal referred to when performing a transmitting process are generated.

When the SD signal is set to the "H" state, the decoder 44 synchronizes the 0th to 4th bits of data output from the shift register 40 with the corresponding 4-bit data in synchronization with the RSYM signal. , And the same operation is repeated until the ED signal becomes “H”. In addition,
The data generated in this way is supplied to the interface 20f.

The encoder 45 is connected to the interface 20
The 4-bit data to be transmitted supplied via f is encoded into 5-bit data for transmission and supplied to the shift register 46.

The data to be transmitted to the network is coded in order to prevent the transmitted bit stream from continuing to be "1". By doing so, there is no need to transmit a DC component, so that the transmission bandwidth required for the network can be reduced.

The shift register 46 receives the 5-bit data supplied from the encoder 45, and supplies the 5-bit data from the encoder 45 in synchronization with a clock signal (not shown) when the TSYM signal becomes “H”. The 5-bit data is fetched and shifted one bit at a time from the fourth bit to the 0th bit, and the 0th bit data is supplied to the multiplexer 47.

The multiplexer 47 sets the TXSE to the “H” state when the relay apparatus transmits its own data.
When the L signal is in the “H” state, the shift register 4
6 is selected, and when the TXSEL signal is in the "L" state, the ninth bit output from the shift register 40 is selected and transmitted to the network.

The principle diagram shown in FIG. 1 and FIGS.
The following is an example of the correspondence (but an example) of the embodiment shown in FIG. That is, the function of the receiving unit 1 is realized by the shift register 40. The function of the start code detecting means 2 is realized by the decoder 41. The function of the first timing signal generator 3 is realized by the relay controller 43.

The function of the sampling means 4 is as follows.
4 and the interface 20f are realized. The function of the first storage means 5 and the second storage means 6 is
Alternatively, the HDD 20e is realized.

The function of the reading means 7 is realized by the CPU 20a. The function of the second timing signal generating means 8 is as follows.
The relay control unit 43 is realized. The function of the synchronization means 9 is realized by the relay control unit 43. The function of the transmission means 10 is realized by the multiplexer 47. The function of the direct supply means 11 is as follows.
The shift register 40 and the multiplexer 47 are realized.

Next, the operation of the above embodiment will be described with reference to the timing charts shown in FIGS. FIG. 7 is a timing chart when the embodiment shown in FIGS. 5 and 6 performs a relay process.

Now, assuming that the shift register 40 receives a frame as shown in FIG. 7A from the network, this data (bit data) is
It is supplied to the 0th bit of 0, and is shifted bit by bit in synchronization with a clock signal (not shown).

The parallel data output from the shift register 40 is constantly monitored by the decoder 41, and when the received data is a start code (when the symbols J and K (or J) are received), the decoder 41 Reference numeral 41 sets the output SD signal (FIG. 7B) to an "H" state.

Then, in response to the SD signal being set to “H”, the relay control unit 43 receives the RSYM signal (FIG. 7).
(D)) is initialized. As a result, the RSYM signal is calibrated to be in the “H” state at the end of each symbol.

At this time, the TXSEL signal (FIG. 7 (G))
Is in an “L” state (a state in which its own data is not transmitted), the relay control unit 43 synchronizes the TSYM signal (FIG. 7E) with the RSYM signal. As a result, the TSYM signal and the RSYM signal have the same timing.

The decoder 44 decodes the 0th to 4th bits of data output from the shift register 40 into 4 bits of data at the same time when the SD signal becomes "H", and supplies the data to the interface 20f. The interface 20f acquires the data output from the decoder 44 at the timing when the RSYM signal becomes “H”, and supplies the data to, for example, the RAM 20c for storage.

Since the TXSEL signal is "L", the multiplexer 47 selects the ninth bit data output from the shift register 40 and outputs it to the network. The data of the ninth bit of the shift register 40 is the data obtained from the network as 1
Since the bit is delayed by 0 bits, for example, the transmission of the first bit of the symbol “J” received in the period P1 starts from the period P3.

Next, the transmission process will be described. FIG.
Is a timing chart in the case where the present embodiment transmits its own data to the network.

When transmitting data, the interface 20f sets the TXSEL signal (FIG. 8 (G)) to "H".
And the data to be transmitted is read out from the RAM 20c and supplied to the encoder 45, for example.

In the case of FIG. 8, the TXSEL signal is set to the "H" state at the end of the period P1, and the transmission of data to the encoder 45 is started in the period P2 (see FIG. 8 (H)).

The data supplied to the encoder 45 is encoded into 5-bit data for transmission and supplied to the shift register 46. The shift register 46 supplies bit 0 data to the multiplexer 47 in synchronization with the fall of the TSYM signal, and starts shifting bits in synchronization with a clock signal (not shown).

As a result, the data supplied from the encoder 45 is transmitted to the network one bit at a time via the multiplexer 47 in synchronization with an internal clock (not shown), triggered by the fall of the TSYM signal.

When the data transmission is completed, the interface 20f sets the TXSEL signal to the "L" state (see period P12 and thereafter in FIG. 8 (G)). According to the above processing,
Data stored in the RAM 20c or the HDD 20e can be transmitted to the network.

Next, a description will be given of the operation in the case where the reception processing of other data is performed in parallel during the transmission of data. FIG.
FIG. 9 is a timing chart in a case where reception processing of other data is performed in parallel during transmission of data.

It is assumed that data stored in the RAM 20c or the HDD 20e has been transmitted to the network. In such a case, if the data shown in FIG. 9A is received from the network, the decoder 41 changes the SD signal to the “H” state at the timing when all the start codes are stored in the shift register 40. I do. In this example, the SD signal is in the “H” state during the period P4.

The relay control section 43 initializes the RSYM signal in response to the SD signal being set to the “H” state.
In this example, the RSYM signal is initialized in the period P4, and thereafter, the RSYM signal is synchronized with the end of each symbol of the received data.

On the other hand, since the TSYM signal has nothing to do with the initialization of the RSYM signal, the multiplexer 47 continues to transmit data to the network at the same timing as before.

When the end code is received, the decoder 42 sets the ED signal to "H". As a result, the decoder 44 stops the decoding process, and the receiving process ends. In the example of FIG. 9, the end code is input in the periods P9 to P11, and the ED signal is set to “H” at the timing when all the end codes are received (period P11), and the reception process ends.

When the data transmission process from the multiplexer 47 is completed, the TXSEL signal is set to "L". When the TXSEL signal is set to “L”, the relay control unit 43 synchronizes the TSYM signal with the RSYM signal. As a result, as shown in a period P15 in FIG.
The M signal and the RSYM signal are synchronized.

According to the above embodiment, the receiving process and the transmitting process are performed in synchronization with different timing signals, so that the receiving process can be performed in parallel during the transmitting process.

[0067]

As described above, according to the present invention, a bit stream is received from a network, and is initialized when a start code is detected from the bit stream.
Thereafter, a first timing signal that becomes active in one symbol period is generated, and the bit stream is sampled and stored in synchronization with the first timing signal.
When transmitting data, a second timing signal that becomes active in one symbol period is generated, data to be transmitted is read out, and transmitted in synchronization with the second timing signal. When the own data is not transmitted, the second timing signal is synchronized with the first timing signal, so that the data transmission processing and the reception processing are performed regardless of the data reception timing. It can be performed in parallel.

[Brief description of the drawings]

FIG. 1 is a principle diagram showing the principle of the present invention.

FIG. 2 is a diagram illustrating an example of a structure of data (frame) to be processed by the relay device illustrated in FIG. 1;

FIG. 3 is a timing chart showing the operation of the principle diagram shown in FIG. 1;

FIG. 4 is a diagram illustrating a configuration example of an embodiment of the present invention.

FIG. 5 is a block diagram showing a detailed configuration example of the relay device shown in FIG. 4;

FIG. 6 is a block diagram illustrating a detailed configuration example of a transmission / reception unit illustrated in FIG. 5;

FIG. 7 is a timing chart when the embodiment shown in FIGS. 5 and 6 performs a relay process.

FIG. 8 is a timing chart when the embodiment shown in FIGS. 5 and 6 transmits its own data to a network.

FIG. 9 is a timing chart in the case where the embodiments shown in FIGS. 5 and 6 simultaneously receive data while transmitting data.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Receiving means 2 Start code detecting means 3 First timing signal generating means 4 Sampling means 5 First storing means 6 Second storing means 7 Reading means 8 Second timing signal generating means 9 Synchronizing means 10 Transmitting means 11 Direct Supply means

Claims (3)

[Claims] 1. A relay device that relays a bit stream that is composed of a plurality of symbols and that is transmitted over a network in units of a frame having a start code added to the head thereof. Start code detection means for detecting the start code from the bit stream received by the reception means; initialization when the start code is detected by the start code detection means; A first timing signal generating unit for generating a first timing signal, a sampling unit for sampling the bit stream in synchronization with the first timing signal, and storing data obtained by the sampling unit. First memory Stage, second storage means for storing data to be transmitted, reading means for reading data to be transmitted from the second storage means, and data read by the reading means being transmitted. , A second timing signal generating means for generating a second timing signal that becomes active in one symbol cycle, and transmitting the data read by the reading means in synchronization with the second timing signal. Transmitting means for transmitting the second timing signal generated by the second timing signal generating means when the own data is not transmitted, and transmitting the first timing signal generated by the first timing signal generating means to the first timing signal generating means; And a synchronization means for synchronizing with a timing signal. 2. In the case of relaying data, in response to the detection of the start code by the start code detecting means, after delaying a bit stream received by the receiving means by the start code,
2. The relay device according to claim 1, further comprising a direct supply unit that directly supplies and transmits the transmission unit. 3. A relay method for relaying a bit stream transmitted over a network in units of a frame including a plurality of symbols and having a start code added to a head thereof, wherein the step of receiving the bit stream is performed. A start code detecting step of detecting the start code from the bit stream received by the receiving step; and being initialized when a start code is detected by the start code detecting step, and thereafter being activated in one symbol period. A first timing signal generating step of generating a first timing signal, a sampling step of sampling the bit stream in synchronization with the first timing signal, and a first timing signal acquired by the sampling step. A first storage step of storing data; a second storage step of storing data to be transmitted; a reading step of reading data to be transmitted from the second storage step; A second timing signal generating step of generating a second timing signal which is referred to when transmitting the output data and becomes active in one symbol period; and reading the data read by the reading step into the second timing signal. A transmitting step of transmitting in synchronization with a timing signal; and a step of generating the second timing signal generated by the second timing signal generating step when the own data is not transmitted. Synchronizing with the first timing signal at which the step occurs; Relay method characterized by.