JPH11340243A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize speed up of a vertical bipolar transistor. SOLUTION: An NPN transistor Tr of a two-layer polycrystalline silicon structure includes a collector region 4C, having a collector-embedded layer 4C1, an intrinsic collector region 4C2 and a collector lead-out layer; a base region 4B having an intrinsic base region 4B1, an external base region 4B2 formed at an outer periphery thereof and a connection region 4B3 for electric connection between the regions 4B1, 4B2 and 4B3; and an emitter region 4E. An emitter lead-out electrode 8E connected to the emitter region 4E, as well as a base lead-out electrode 8B connected to the external base region 4B2, are made of polycrystalline silicon films. In the transistor, the intrinsic base region 4B1, part of the external base region 4B2, and the connection region 4B3 are formed by implanting impurity ions from an oblique direction.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a technique effective when applied to a semiconductor device having a high-performance bipolar transistor.

[0002]

2. Description of the Related Art A high-performance central processing unit (CPU; Ce)
Logic devices such as ntral Processing Unit)
Bipolar transistor with high switching speed or B with improved power consumption of bipolar transistor
i-CMOS (Bipolar-Complementary Metal Oxide Se
miconductor) A bipolar semiconductor device such as a transistor is used. In such a bipolar transistor, a vertical bipolar transistor excellent in high-speed response is often used. Examples of the vertical bipolar transistor include those described in Japanese Patent Application Laid-Open Nos. 7-231143 and 7-283421. As has been
A double polysilicon film structure using a polysilicon film for the emitter and base extraction electrodes is widely used.

In the vertical bipolar transistor having a double polycrystalline silicon film structure described in the above document, a base region including an intrinsic base region and an external base region is formed above a collector region and is surrounded by the base region. An emitter region is formed. That is, almost the side of the emitter region is surrounded by the external base region, and the intrinsic base region is formed below the emitter region, that is, in a region sandwiched between the emitter region and the collector region. Here, the intrinsic base region, together with the emitter and collector regions, is p
An np or npn transistor is configured to function as a transistor base, and the external base region functions as an electrical connection region connected to the intrinsic base region.

In the above-mentioned vertical bipolar transistor, a polycrystalline silicon film containing an impurity of the same conductivity type as the impurity doped into the external base region at a high concentration is used as the base extraction electrode, and the emitter region is used as the emitter extraction electrode. A polycrystalline silicon film containing an impurity of the same conductivity type as the impurity doped at a high concentration is used.
As described above, by using the polycrystalline silicon film doped with impurities for the base extraction electrode and the emitter extraction electrode, the external base region and the emitter region can be formed in a self-aligned manner, and miniaturization is facilitated.

[0005] For example, a technical report of the Institute of Electronics, Information and Communication Engineers published in January 1995, ED94-130 / MW94.
-117 / ICD94-192, Hashimoto et al. "Ultra High Speed LSI
0.3μm-Si bipolar process technology ”, p13
To p18, SOI (Silicon On
Insulator) A technique using a substrate and a U-groove element isolation structure, a technique in which an amorphous silicon film doped with phosphorus is used to form an emitter to form a shallow junction of the emitter, and a low energy ion species (acceleration energy 10 keV
Implantation of BF ₂ ) and RTA (Rapid Thermal Anne)
aling), and a technique of reducing the thickness of the epitaxial growth layer forming the collector region to 0.6 μm in order to shorten the carrier transit time in the collector region.
Attempts have been made to increase the speed of transistors using these techniques.

On the other hand, in the intrinsic base region, an impurity region for forming an intrinsic base region is previously formed by ion implantation or the like in a region where an intrinsic base is to be formed, that is, an opening for forming an emitter, and is extended and diffused. It is formed by this. The extension diffusion is performed at the same time when the external base region and the emitter region are formed by autodoping from the base extraction electrode and the emitter extraction electrode.

As a method of implanting ions into a region where an intrinsic base is formed, for example, Japanese Patent Application Laid-Open No. Hei 7-142519
JP-A-5-175204, JP-A-8-1
As described in JP-A-39100, etc., an ion implantation method of impurity ions obliquely (for example, 45 degrees) with respect to a substrate is known.

[0008]

However, with the spread of multimedia and Internet services in recent years, a technology for transmitting more information efficiently and inexpensively becomes necessary. There is an increasing demand for higher speed in bipolar transistors as well. In addition, the next-generation communication device is required to be provided at a lower cost in addition to being high-speed (high-performance). Therefore, the next-generation communication device is developed and manufactured in a short time using existing process technology. It is necessary.

That is, in an optical transmission system which is one of large-scale communication systems, the transmission speed required for the next generation optical transmission system is 40 Gb / s, and the cutoff frequency fT Is about 10
It becomes 0 GHz. Such high-speed performance cannot be achieved unless the current device characteristics are further improved.

Further, not only IC chip sets used in optical transmission systems but also optical interconnects for connecting them are required to have higher performance. The optical interconnect is required to replace a conventional connection between a communication device and a computer using a coaxial cable with an optical fiber array cable and realize high-speed, high-density wiring with a light weight. In order to achieve this, in addition to high speed, low power consumption, high uniformity, and excellent noise characteristics are required. For this reason, devices such as bipolar transistors used in optical interconnects are required to have high speed, small variations between devices, and stable and uniform characteristics.

An object of the present invention is to increase the speed of a vertical bipolar transistor.

Another object of the present invention is to reduce the base width of a vertical bipolar transistor to a shallow junction.

Another object of the present invention is to reduce the base resistance of a vertical bipolar transistor.

It is still another object of the present invention to increase the speed of a vertical bipolar transistor, reduce variations between elements, and realize stable and uniform characteristics.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0016]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) The method of manufacturing a semiconductor device according to the present invention
(A) A first conductivity type impurity is introduced into a main surface of a substrate made of a semiconductor or a substrate having a semiconductor layer on the surface thereof to form a first conductive type impurity.
Forming a semiconductor region and forming a second semiconductor region on the first semiconductor region; (b) a second isolation region near the surface of the second semiconductor region and a second region reaching a lower portion of the first semiconductor region;
Forming an isolation region; and (c) introducing a first conductivity type impurity into a portion of the second semiconductor region surrounded by the first isolation region to reach the first semiconductor region. (D) depositing a first polycrystalline silicon film into which an impurity of the second conductivity type is introduced, and forming a second semiconductor region surrounded by the first isolation region in and around the other region. Etching the first polycrystalline silicon film so as to cover the first isolation region, (e) forming a first insulating film covering the first polycrystalline silicon film, and (f) forming a first insulating film on the second semiconductor region. Forming an opening in the insulating film and the first polycrystalline silicon film; (g) ion-implanting a second conductivity type impurity into the second semiconductor region at the bottom of the opening from a direction oblique to the substrate;
A first base region functioning as a base of the transistor,
Forming a part of a second base region formed under the first polycrystalline silicon film and a fourth semiconductor region including a third base region electrically connecting the first base region and the second base region; (H) forming a sidewall spacer on the inner wall of the opening, and depositing a second polysilicon film containing a first conductivity type impurity on the fourth semiconductor region, the sidewall spacer, and the first insulating film at the bottom of the opening; Process,
(I) a step of etching the second polycrystalline silicon film while leaving an opening, and (j) a step of forming a second base region by diffusion from the first polycrystalline silicon film accompanying heat treatment of the substrate.

According to such a method of manufacturing a semiconductor device, the impurity is ion-implanted obliquely into the region where the base is to be formed, so that the junction width of the base can be reduced. That is, Japanese Patent Application Laid-Open No. 7-142519
JP-A-5-175204, JP-A-8-1
In the technique described in JP-A-39100, etc., ion implantation into the base region is performed from an oblique direction. However, a connection region (ring base region) connecting the intrinsic base region and the external base region or an external base region is obliquely formed. The intrinsic base region is formed by ion implantation from a vertical direction. On the other hand, in the present invention, in addition to a part of the external base region (second base region) and the connection region (third base region), an intrinsic base region (first base region)
Is also formed by ion implantation from an oblique direction. Thus, since the intrinsic base region is formed by ion implantation from an oblique direction, the ion implantation depth can be made shallower than ion implantation from a vertical direction. As a result, a shallow junction can be formed by forming the shallow intrinsic base region, and the performance of the semiconductor device can be improved.

On the other hand, a method of forming a shallow junction by lowering the energy of the implanted ions can be considered. However, if the implantation energy is reduced, the energy variation of the implanted ions increases, and the uniformity of the intrinsic base is improved with good reproducibility. It becomes difficult to form a region. On the other hand, in the present invention, since the ion implantation is performed in an oblique direction, the implantation energy is not reduced unnecessarily, and a shallow junction can be formed while appropriately suppressing the variation in the implantation energy. This makes it possible to form the intrinsic base region uniformly with good reproducibility, suppress variations between elements of the semiconductor device, and obtain stable performance.

According to the present invention, the intrinsic base region (first base region), a part of the external base region (second base region), and the connection region (third base region) are obtained by ion implantation in an oblique direction. Are formed at the same time, and the region into which ions are implanted to the deepest is the connection region (third base region) from the relationship between the diameter of the opening and the opening depth. Since the third base region is formed deep as described above, the cross-sectional area of the third base region as a conductor region is increased, and an intrinsic base region (first base region) and a part of the external base region (first base region) are formed. 2 base region) can be reduced. Thereby, the base resistance of the semiconductor device can be reduced, and the performance of the semiconductor device can be improved.

Conventionally, an intrinsic base region is formed in a self-aligned manner by ion implantation in a vertical direction, and an external base region and a connection region are formed from a base extraction electrode made of a polycrystalline silicon film doped with impurities. Although formed by diffusion of impurities, in the present invention, since ion implantation is performed in an oblique direction, the external base region and connection region that cannot be formed when the intrinsic base region is formed in a self-aligned manner are also formed by ion implantation. it can.
In particular, the connection region formed by impurity diffusion from the base extraction electrode conventionally has a problem that the resistance value increases because the distance from the base extraction electrode, which is a diffusion source, becomes longer and does not reach a sufficient impurity concentration. However, in the present invention, since the connection region (third base region) is formed by ion implantation in an oblique direction, the resistance value can be sufficiently reduced. Therefore, the performance of the semiconductor device can be improved by reducing the base resistance of the semiconductor device.

By reducing the base resistance as described above, the performance of the semiconductor device, in particular, the cutoff frequency f, which indicates high speed operation,
T and the maximum cut-off frequency fmax which is a guideline for high performance
How is improved by using an equation will be described. That is, the cutoff frequency fT and the maximum cutoff frequency fmax
_{Is, fT = Dn B / 2π ·} W 2, fmax = fT / 8π · r bb · C TC, in represented. Here, W is the base width, Dn _B base diffusion constant, the r _bb base resistance, C _TC is the collector junction capacitance. As can be seen from the above equation, the cutoff frequency fT is proportional to the square of the width of the intrinsic base region, and it is important to form a shallow junction in order to increase the speed. Further, it can be seen that increase of the maximum cutoff frequency fmax is reduced base resistance r _bb with increasing cutoff frequency fT is important.
Therefore, the present invention in which the intrinsic base region (first base region), a part of the external base region (second base region), and the connection region (third base region) are formed by oblique ion implantation, It turns out that it is extremely effective for improvement.

Further, according to the present invention, an opening is formed in a base extraction electrode (first polycrystalline silicon film), and ion implantation for forming a base is performed in a self-aligned manner using the opening as a mask. No alignment margin is required for formation, the element size of the semiconductor device can be reduced, and the semiconductor device can be highly integrated.

Further, the oblique ion implantation technique can be performed by injecting ions while tilting the substrate, and can be realized only by adding necessary minimum improvements to conventional equipment. Thus, a high-performance semiconductor device can be manufactured at low cost using conventional devices and materials. Also,
Although the present invention requires the optimization of the impurity concentration in the base region, it is possible to use a device structure and a mask of the prior art, thereby shortening the development period and providing an inexpensive high-performance semiconductor. Equipment can be manufactured.

(2) The method of manufacturing a semiconductor device according to the present invention comprises the steps of: (a) introducing a first conductivity type impurity into a main surface of a semiconductor substrate or a substrate having a semiconductor layer on its surface; Forming a semiconductor region and forming a second semiconductor region on the first semiconductor region; (b) forming a first isolation region near the surface of the second semiconductor region and a second isolation region reaching below the first semiconductor region; Forming, (c) introducing a first conductivity type impurity into a part of the second semiconductor region surrounded by the first isolation region to form a third semiconductor region reaching the first semiconductor region; (D) depositing a first polycrystalline silicon film into which impurities are not positively introduced and a second polycrystalline silicon film into which impurities of a second conductivity type are introduced, and a second semiconductor surrounded by the first isolation region The first of the other areas of the area and its surroundings Etching the second polycrystalline silicon film and the first polycrystalline silicon film so as to cover the region, first to cover the (e) first and second polycrystalline silicon film
Forming an insulating film; (f) a first step on the second semiconductor region;
Forming an opening in the insulating film, the second polycrystalline silicon film, and the first polycrystalline silicon film; and (g) introducing an impurity of the second conductivity type into the second semiconductor region at the bottom of the opening from a direction oblique to the substrate. Ion implantation is performed, a first base region functioning as a base of the transistor, a second base region formed below the first polycrystalline silicon film, and a third base region electrically connecting the first base region and the second base region. Forming a fourth semiconductor region consisting of a base region, (h) forming a sidewall spacer on the inner wall of the opening, and forming a sidewall spacer on the fourth semiconductor region, the sidewall spacer and the first insulating film at the bottom of the opening;
The method includes a step of depositing a third polycrystalline silicon film containing a first conductivity type impurity, and a step of (i) etching the third polycrystalline silicon film while leaving an opening.

According to such a method of manufacturing a semiconductor device, in addition to the above-mentioned effect (1), the junction capacitance between the base and the collector can be reduced, and the performance of the semiconductor device can be improved. That is, in the present invention, a stacked film of the first polycrystalline silicon film into which impurities are not positively introduced and the second polycrystalline silicon film into which impurities of the second conductivity type are introduced is used as the base extraction electrode. This suppresses excessive diffusion of impurities into the external base region due to the heat treatment when forming the emitter region. In other words, since the non-doped first polycrystalline silicon film (lower layer) is formed between the impurity-doped second polycrystalline silicon film (upper layer) and the substrate, impurities from the second polycrystalline silicon film are removed. Diffusion stops by the first polycrystalline silicon film and does not reach the main surface of the substrate or only a very small amount. Therefore, the introduction of impurities into the external base region can be suppressed to a necessary minimum, and the junction capacitance between the base and the collector can be reduced. As described above, in the present invention, the external base region does not need to be formed by diffusion of impurities from the base extraction electrode because the second base region functioning as the external base region is formed by oblique ion implantation. Based.

In the step (g), ion implantation from an oblique direction is performed at θ ≧ tan ⁻¹ (d / L), where θ is the angle of incidence of ions on the substrate surface and d is the depth of the opening. , L is the opening radius.). By satisfying such a condition, the intrinsic base region (first
The base region), a part of the external base region (second base region), and the connection region (third base region) can be reliably formed.

In the step (g), in addition to the ion implantation in an oblique direction, the ion implantation in a direction perpendicular to the substrate may be performed repeatedly to form the fourth semiconductor region.

The emitter region (fifth semiconductor region) may be formed by depositing the second polysilicon film or the third polysilicon film (emitter extraction electrode) deposited in the above-mentioned step (h) and etched in the step (i). ) Can be performed by thermal diffusion of impurities. Alternatively, the emitter region (fifth
The semiconductor region is formed by ion-implanting impurities of the first conductivity type into the fourth semiconductor region (base region) at the bottom of the opening from the direction oblique to the substrate after the formation of the sidewall spacer in the step (h). Can be formed. In the case where the emitter region is formed by ion implantation from an oblique direction as described above, the density of impurities introduced into the emitter region can be precisely controlled, and the formation depth can be reduced to improve the performance of the semiconductor device. .

(3) In the semiconductor device of the present invention, a substrate made of a semiconductor or a substrate having a semiconductor layer on its surface, and a first conductivity type impurity formed on the main surface of the substrate and functioning as an emitter of a transistor are introduced. The first semiconductor region, a first base region covering the first semiconductor region and functioning as a base of the transistor, a second base region formed in a part below the base extraction electrode, and the first base region and the second base. A second semiconductor region including a third base region electrically connected to the region and having a second conductivity type impurity introduced therein, and a first conductivity type formed below the second semiconductor region and functioning as a collector of the transistor A third semiconductor region into which a third impurity has been introduced.
The depth of the bottom surface of the base region is shallower than the depth of the bottom surface of the third base region.

The main surface of the substrate below the base extraction electrode has an external base region electrically connected to the second base region and formed by diffusion of a second conductivity type impurity from the base extraction electrode. Things.

Alternatively, a base extraction electrode is formed on the main surface of the substrate and does not contain much impurities of the second conductivity type, and a first polysilicon film formed on the first polysilicon film is formed of the second conductivity type. In the case where the substrate is formed of a laminated film with the second polycrystalline silicon film containing a large amount of impurities, an impurity semiconductor region is formed on the main surface of the substrate below the base extraction electrode by diffusion of impurities from the base extraction electrode. Not what it is.

Such a semiconductor device has the above-mentioned (1)
Alternatively, the semiconductor device is manufactured by the method of manufacturing a semiconductor device according to (2), wherein the depth of the bottom surface of the first base region (intrinsic base region) is smaller than the depth of the bottom surface of the third base region (connection region). Therefore, the base width of the intrinsic base region can be shortened to increase the speed, and the cross-sectional area of the connection region can be increased to reduce the base resistance, thereby improving the performance of the semiconductor device.

[0034]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a sectional view showing an example of a semiconductor device according to an embodiment of the present invention. FIG. 2 is an enlarged cross-sectional view of a portion II in FIG.

The semiconductor substrate 1 of the semiconductor device according to the first embodiment has a substrate 1a made of, for example, p-type silicon (Si) single crystal, and an SOI (Silicon On Insulato) on its upper surface.
r) An SOI substrate having an insulating layer 1b and a single-crystal silicon layer 1c. The single crystal silicon layer 1c is made of SOI
A single crystal silicon film is formed on the bond silicon layer on the insulating layer 1b by epitaxial growth. Here, S
Although an OI substrate is exemplified, it goes without saying that a single crystal silicon substrate may be used.

A field insulating film 2 made of, for example, a silicon oxide film is formed on the main surface of semiconductor substrate 1, and an element isolation in which an insulating film is buried in a U groove is formed below a part of field insulating film 2. Region 3 is formed. The insulating film embedded in the U groove is, for example, a silicon oxide film. The bottom of the element isolation region 3 is formed to reach the SOI insulating layer 1b, and the single crystal silicon layer 1c surrounded by the SOI insulating layer 1b and the element isolation region 3 is electrically insulated from the substrate 1a. As a result, the stray capacitance of the element can be reduced and the speed can be increased.

Each region of the semiconductor substrate 1 surrounded by the element isolation region 3 includes, for example, a vertical npn bipolar transistor (hereinafter simply referred to as an npn transistor) Tr, a simple stack type capacitance element C, and a polycrystalline silicon film. A resistance element R is formed. Here, an npn transistor Tr is illustrated, but a vertical pnp bipolar transistor may be formed.

The npn transistor Tr has a collector region 4C, a base region 4B and an emitter region 4E.

The collector region 4C includes a collector buried layer 4C1 and an intrinsic collector region 4C formed thereabove.
2 and a collector lead-out layer 4C3 formed on the collector buried layer 4C1.

The collector buried layer 4C1 is formed on the single crystal silicon layer 1c by, for example, antimony (S
b) is introduced and formed. Intrinsic collector area 4C2
And collector lead-out layer 4C3 is formed on single-crystal silicon layer 1c by, for example, n-type impurity phosphorus or arsenic (As).
Are introduced and formed. However, the intrinsic collector region 4
The impurity concentration of C2 is, for example, about 1 × 10 ¹⁶ / cm ³ . The impurity concentration of the collector lead layer 4C3 is
For example, it is about 1 × 10 ¹⁹ / cm ³ .

The collector extraction layer 4C3 is electrically connected to the collector electrode 8C through a connection hole opened in the insulating film 6 on the single crystal silicon layer 1c. The collector electrode 8C can be, for example, a stacked film of a tungsten film formed by a sputtering method, a tungsten film formed by a CVD method, an aluminum film, and a tungsten film formed by a sputtering method. The aluminum film is a main conductive layer and may be an Al-Si-Cu alloy. The insulating film 6 is made of, for example, PSG (Phospo
-Silicate Glass) film or BPSG (Boron-doped Ph)
ospo-Silicate Glass) film or SOG (Spin On Gl)
ass) consisting of membrane.

A pedestal collector region 4C4 in which a higher concentration of n-type impurity As or phosphorus is introduced than the intrinsic collector region 4C2 is formed in the intrinsic collector region 4C2 immediately below the base region 4B. Accordingly, the Kirk effect can be suppressed by suppressing the apparent extension of the base region 4B during the operation of the npn transistor Tr, and the collector cutoff frequency characteristics can be improved.

The base region 4B is an intrinsic base region 4B1
And an external base region 4B2 formed below the base extraction electrode 8B, and a connection region 4B3 connecting the intrinsic base region 4B1 and the external base region 4B2.

The intrinsic base region 4B1 forms an active region of the npn transistor Tr together with an intrinsic collector region 4C2 and an emitter region 4E described later. The external base region 4B2 electrically connects the base extraction electrode 8B and the intrinsic base region 4B1, and most of the region is formed by diffusion of impurities from the base extraction electrode 8B as described later. You. The connection region 4B3 includes an intrinsic base region 4B1 and an external base region 4B.
2 is an area for electrical connection with

The intrinsic base region 4B1 and the external base region 4
As will be described later, a part of B2 and the connection region 4B3 are formed by introducing impurity ions such as boron of a p-type impurity by ion implantation from an oblique direction. Therefore, the intrinsic base region 4B1 can be formed shallow, and the base width can be reduced to increase the cutoff frequency fT and the maximum cutoff frequency fmax of the npn transistor Tr.

Further, not only the intrinsic base region 4B1 but also the external base region 4B2 can be implanted by oblique ion implantation.
And the connection region 4B3 are also formed, so that the impurity concentration introduced into the connection region 4B3 can be increased, and the connection region 4B3 can be formed deeper than the intrinsic base region 4B1.
That is, the bottom of the connection region 4B3 is
It is formed deeper than the bottom of B1 by a distance M as shown in FIG. Thereby, the cross-sectional area of the connection region 4B3 can be increased to reduce the resistance value of the connection region 4B3, and the base resistance can be reduced to increase the cutoff frequency fT and the maximum cutoff frequency fmax of the npn transistor Tr.

Further, part of the external base region 4B2 is also formed by ion implantation from an oblique direction. As a result, the external base region 4B2 overlaps with regions formed by oblique ion implantation (the intrinsic base region 4B1, a part of the external base region 4B2 and the connection region 4B3), and the two regions are electrically connected. Is performed reliably. As a result, the base resistance is reduced and the cutoff frequency fT and the maximum cutoff frequency fmax of the npn transistor Tr are reduced.
Can be increased.

The external base region 4B2 is electrically connected to the base lead electrode 8B. A high concentration, for example, 5 × 10 ¹⁹ to 1 × 10 ²¹ is applied to the base extraction electrode 8B.
Boron (B) is introduced at a rate of about boron / cm ³ . The high-concentration impurities contained in the base extraction electrode 8B are introduced into the external base region 4B2 by thermal diffusion, and the external base region 4B2 has an impurity concentration of at least 1 × 10 ¹⁹ / cm.
³ or more. Thereby, the resistance of the external base region 4B2 is reduced, and the cutoff frequency f of the npn transistor Tr is reduced.
T and the maximum cutoff frequency fmax can be increased. The thickness of the base extraction electrode 8B is, for example, 200
nm.

An insulating film 9a is deposited on the upper layer of the base lead electrode 8B, and a side wall spacer 9b is formed on the side surface of the base lead electrode 8B via the insulating film 9c. The insulating film 9a, the insulating film 9c, and the side wall spacer 9b are made of, for example, a silicon oxide film. The silicon oxide film can be deposited by, for example, a CVD method.

The base lead electrode 8B is connected to the first layer wiring 1 through a connection hole formed in the insulating film 6 and the insulating film 9a.
0a. The first layer wiring 10a is
It has the same configuration as the collector electrode 8C described above.

The emitter region 4E is an intrinsic base region 4B
1 is formed by introducing, for example, an n-type impurity such as phosphorus or As. The impurity concentration is, for example, 1 ×
It is about 10 ²⁰ to 10 ²¹ / cm ³ . Emitter region 4
E is electrically connected to the insulating film 9a, the sidewall spacer 9b, and the emitter lead-out electrode 8E formed on the emitter region 4E. Emitter extraction electrode 8E is made of, for example, an n-type polycrystalline silicon film. The emitter extraction electrode 8E is electrically connected to the first layer wiring 10b through a connection hole opened in the insulating film 6. The first layer wiring 10b has the same configuration as the first layer wiring 10a.

The simple stack type capacitance element C includes an upper electrode 11, a capacitance insulating film 12, and an impurity semiconductor region 13 serving as a lower electrode. The impurity semiconductor region 13
The semiconductor device includes a semiconductor region 13a formed facing the upper electrode 11 with the capacitor insulating film 12 interposed therebetween, a semiconductor region 13b formed as a semiconductor layer embedded in the single crystal silicon layer 1c, and a semiconductor region 13c. Semiconductor regions 13a to 13c
Are electrically connected to each other to form a conductive region in the single-crystal silicon layer 1c. The upper electrode 11 and the semiconductor region 13c are connected to the wiring 14 via connection holes opened in the insulating films 6, 9a, respectively. That is, the capacitor C is formed between the wirings 14.

The upper electrode 11 is made of a polycrystalline silicon film into which impurities are introduced, and is formed in the same layer as the base lead electrode 8B. Capacitive insulating film 12 is, for example, a silicon oxide film formed by a thermal oxidation method, and has a thickness of, for example, 50 nm. The semiconductor regions 13a and 13c are semiconductor regions into which the same impurity as that of the collector lead layer 4C3 has been introduced, and their bottoms are in contact with the semiconductor region 13b. The semiconductor region 13b is configured similarly to the collector buried layer 4C1. The wiring 14 is configured similarly to the collector electrode 8C, the first layer wiring 10a, and the first layer wiring 10b.

The resistance element R is formed by using the polycrystalline silicon film 15 formed on the field insulating film 2 as a resistance material. Wirings 16 are formed at both ends of the polycrystalline silicon film 15 so as to be in contact with each other, and a resistor is formed between the wirings 16.
Impurities are introduced into the polycrystalline silicon film 15 and have the same configuration as the base extraction electrode 8B and the upper electrode 11. The wiring 16 is connected to the polycrystalline silicon film 15 through a connection hole opened in the insulating films 6 and 9a, and has the same configuration as the collector electrode 8C, the first layer wiring 10a, the first layer wiring 10b, and the wiring 14. .

An interlayer insulating film 17 is formed on the collector electrode 8C, the first layer wiring 10a, the first layer wiring 10b, the wiring 14 and the wiring 16, and a lower wiring is formed through a connection hole opened in the interlayer insulating film 17. Is formed on the interlayer insulating film 17. The interlayer insulating film 17 is, for example, a silicon oxide film formed by a CVD method.
For example, a stacked film of a tungsten film formed by a sputtering method, a tungsten film formed by a CVD method, an aluminum film, and a tungsten film formed by a sputtering method can be used. The aluminum film is
It is a main conductive layer and may be an Al-Si-Cu alloy.

An insulating film 19 is formed on the second layer wiring 18, and a bump 21 is formed in a connection hole opened in the insulating film 19 via a bump base metal 20. Insulating film 19
Is a silicon oxide film formed by, for example, a CVD method. The bump base metal 20 is a laminated metal film of nickel, gold, or the like, and the bump 21 is, for example, a solder bump.

Although the case where the number of metal wiring layers is two is illustrated here, it is needless to say that three or more wiring layers may be provided. Needless to say, a bonding pad for wire bonding may be formed instead of the bump 21 without forming the bump 21. Further, the bump 21 is not limited to the solder but may be a gold bump, and the bump shape is not limited to a ball and may be a stud shape.

Next, a method of manufacturing the semiconductor device according to the first embodiment will be described in the order of steps with reference to the drawings. 3 to 12
FIG. 5 is a cross-sectional view or a partially enlarged cross-sectional view illustrating an example of a manufacturing process of the semiconductor device of the first embodiment in the order of steps;

First, an SOI insulating layer 1b and a bond silicon layer 1c are formed on a substrate 1a made of p-type silicon single crystal.
After preparing an SOI substrate having 1 and using a photoresist film as a mask to form a sacrificial oxide film 22 in a region where an npn transistor Tr and a capacitor C are to be formed, impurities such as antimony (Sb) are introduced by ion implantation. Thus, an impurity implantation layer 23 is formed (FIG. 3A). The conditions for the ion implantation are, for example, an acceleration voltage of 100 keV and an implantation density of 2 × 10 ¹⁵ atoms / cm ² .

Next, the sacrificial oxide film 22 is removed, and an epitaxial growth layer 1c2 is formed on the bond silicon layer 1c1 (FIG. 3B). The thickness of the epitaxial growth layer 1c2 is, for example, 0.6 μm. The epitaxial growth layer 1c2 and the bond silicon layer 1c1 form the single crystal silicon layer 1c of the semiconductor substrate 1. The epitaxial growth layer 1c2 will later become an intrinsic collector region 4C2, a base region 4B and an emitter region 4E.

At the time of this epitaxial growth, the epitaxial growth layer 1c2 on the impurity implantation layer 23 has
Antimony which is an impurity is auto-doped, and its specific resistance becomes about 3 Ω · cm. Further, the impurity injection layer 23
It is spread and diffused by heating during epitaxial growth, and is later formed into the collector buried layer 4C1 and the semiconductor region 1
A semiconductor region 24 to be 3b is formed.

Next, for example, a sacrificial oxide film having a thickness of 13.5 nm and a silicon nitride film having a thickness of 140 nm are deposited, and are etched and patterned using a photoresist film as a mask. The field insulating film 2 is formed on the single crystal silicon layer 1c which is the epitaxial growth layer 1c2. That is, LOCOS (Local Oxidation of Silico)
A field insulating film 2 made of a silicon oxide film is formed by using the n) method (FIG. 4A).

Next, a pre-oxide film (not shown) is formed on the entire surface of the semiconductor substrate 1, a non-doped polycrystalline silicon film 25 into which impurities are not introduced is deposited to a thickness of, for example, 100 nm, and a silicon oxide film 26 is deposited, for example. 2
After being deposited to a thickness of 00 nm, anisotropic etching is performed using the photoresist film as a mask to form a U-shaped groove 27 (FIG. 4B). The bottom of the U groove 27 is formed so as to reach the SOI insulating layer 1b. Due to the formation of the U-groove 27, the semiconductor region 24 is divided. In the region where the npn transistor Tr is formed, the semiconductor region 24 becomes the collector buried layer 4C1.
b. The width of the U groove 27 is, for example, 0.4 μm.

Next, the semiconductor substrate 1 including the inside of the U-groove 27
For example, a silicon oxide film is deposited on the entire surface of the substrate, and the silicon oxide film is etched back to form an element isolation region 3 in which a silicon oxide film is buried inside the U groove 27 (FIG. 5A).
At the time of etch back, the polycrystalline silicon film 25 can be used as a stopper film. Note that the deposition and the etch back of the silicon oxide film can be performed a plurality of times.
Further, a void may be formed inside the element isolation region 3 as shown in the figure. In such a case, the insulation performance can be improved by oxidizing the inside of the U-groove 27 by a thermal oxidation method or the like before depositing the silicon oxide film.

Next, the polysilicon film 25 is removed and 5
A 0-100 nm silicon oxide film 28 is deposited. Thereafter, for example, phosphorus (P) is ion-implanted using the photoresist film as a mask to form the collector extraction layer 4C3 and the semiconductor regions 13a and 13c. Further, the silicon oxide film 28 in the region where the capacitance element C is formed is removed, and the capacitance insulating film 12 is formed on the semiconductor region 13a by, for example, a thermal oxidation method.
Is formed (FIG. 5B).

Next, the silicon oxide film 28 in the region where the npn transistor Tr is to be formed is removed, and a polycrystalline silicon film doped with, for example, boron is deposited on the entire surface of the semiconductor substrate 1. The thickness of this polycrystalline silicon film is, for example, 2
00 nm. Then, using the photoresist film as a mask, the polycrystalline silicon film is patterned and npn
The base lead electrode 8B is formed in the region where the transistor Tr is formed, the upper electrode 11 is formed in the region where the capacitive element C is formed, and the polycrystalline silicon film 15 is formed in the region where the resistive element R is formed. Further, the silicon oxide film 29 is
Deposited with a thickness of 0 nm, the silicon oxide film 29 on the base extraction electrode 8B is removed (FIG. 6).

Next, an insulating film 9a is formed on the base lead electrode 8B, and an opening 30 is formed in a region where the base and the emitter of the npn transistor Tr are formed (FIG. 7). The insulating film 9a can be, for example, a silicon oxide film having a thickness of 200 nm, and is formed by thermal CVD or TEOS.
Can be formed by a CVD method using

Next, an insulating film 9c is formed inside the opening 30, and the insulating film 9c is formed in a direction substantially perpendicular to the surface of the semiconductor substrate 1.
For example, phosphorus is accelerated at a voltage of 200 keV and an injection density of 5 × 1
Ion implantation is performed under the condition of 0 ¹² atoms / cm ² . Thus, a pedestal collector region 4C4 is formed (FIG. 8).

Next, impurities such as BF from an oblique direction
By performing the ion implantation of ₂ , the intrinsic base region 4B
1. A connection region 4B3 is formed (FIG. 9). Note that a part of the connection region 4B3 is also a part of the external base region 4B2, and is integrated with an external base region 4B2 formed later by diffusion of an impurity from the base extraction electrode 8B. The conditions for the ion implantation are, for example, an implantation energy of 10 keV and an implantation density of 6 × 10 ¹³ atoms / cm.
Can be ² . Ion implantation from an oblique direction
Holding the semiconductor substrate 1 at an angle to the ion incident direction,
This can be done by rotating.

The angle θ of the ion implantation is given by θ ≧ tan
^-1 (d / L). However,
θ is the angle of incidence of ions on the substrate surface, d is the depth of the opening 30, and L is the radius of the opening 30. The angle θ can be exemplified by 45 degrees.

As described above, by implanting impurity ions obliquely to form the intrinsic base region 4B1, a shallow junction of the base width can be achieved. That is, if impurity ions are implanted in the vertical direction, the shallow intrinsic base region 4B as in the present embodiment is formed.
In order to form 1, the ion implantation energy must be reduced. However, as described above, the ion energy is considerably small at 10 keV. If the ion energy is further reduced, the variation of the ion energy becomes relatively large, and the intrinsic base region 4B1 cannot be formed stably with good reproducibility. Of each element characteristic becomes large. However, in the present embodiment, since the ion implantation is performed from the oblique direction as described above, the intrinsic base region 4B1 can be formed shallowly without reducing the ion energy. For this reason, it is possible to improve the cut-off frequency fT and the maximum cut-off frequency fmax of the semiconductor device, suppress variations in element characteristics, improve the uniformity and reproducibility of the performance of each element, and improve the performance of the semiconductor device.

Further, by ion implantation from an oblique direction,
Since not only the intrinsic base region 4B1 but also the connection region 4B3 are formed, the connection region 4B3 is formed not by diffusion from the external base region 4B2 or the like, but directly by ion implantation. That is, it is possible to sufficiently increase the density of impurities introduced into the connection region 4B3 and reduce the resistance. Thus, the base resistance of the element can be reduced, the maximum cutoff frequency fmax can be improved, and the performance of the semiconductor device can be improved. Further, from the relationship between the radius L of the opening and the opening depth d, as shown in FIG.
B3 is formed deeply. That is, the intrinsic base region 4B
While the ion implantation into 1 is partially shielded at the upper part of the opening 30, the ion implanted into the connection region 4B3 has nothing to shield it, so that the ion is implanted deeply. Since the connection region 4B3 is formed deep as described above,
The cross-sectional area, that is, the cross-sectional area of the conductive portion increases, and the resistance can be reduced.

Since the ion implantation is performed obliquely, not only the intrinsic base region 4B1 but also the connection region 4B3 can be formed simultaneously with the opening 30 in a self-aligned manner.
As a result, fine processing of the semiconductor device can be facilitated and the degree of integration can be improved. Further, a part of the connection region 4B3 is formed so as to be located below the base extraction electrode 8B, and the connection region 4B3 located below the base extraction electrode 8B is formed.
3 is also a part of the external base region 4B2. As described above, the oblique ion implantation allows the external base region 4B2
Is formed to secure the electrical connection between the external base region 4B2 and the intrinsic base region 4B1, thereby reducing the base resistance and improving the performance of the semiconductor device. In addition,
The part of the connection region 4B3 is formed so as to be located below the base extraction electrode 8B because oblique ion implantation is performed before a sidewall spacer 9b described later is formed. The lower part of the base extraction electrode 8B, that is, a part of the external base region 4B2 can be formed.

The oblique ion implantation technique as in the present embodiment can be performed by injecting ions while tilting the semiconductor substrate 1, and is realized only by adding a necessary minimum improvement to the conventional equipment. It is possible. Thus, a high-performance semiconductor device can be manufactured at low cost using conventional devices and materials. Further, in this embodiment, the conventional device structure, mask, and the like can be used as they are, and a high-performance semiconductor device can be manufactured at a low cost with a reduced development period.

Next, base annealing is performed to form an external base region 4B2. Further, a silicon oxide film having a thickness of, for example, 140 nm is deposited on the entire surface of the semiconductor substrate 1, and this silicon oxide film is etched by anisotropic etching to form a base lead electrode 8B via an insulating film 9c.
And a side wall spacer 9b on the side surface of the insulating film 9a.
Is formed (FIGS. 10 and 11A). Note that a silicon nitride film may be deposited instead of the silicon oxide film.

Next, a low-resistance polycrystalline silicon film containing an n-type impurity such as phosphorus is deposited on the entire surface of the single-crystal silicon layer 1c by CVD or the like, and then an emitter electrode is formed on the low-resistance polycrystalline silicon film. Patterning the photoresist film for formation by photolithography technology,
Subsequently, using the photoresist film as an etching mask, the low-resistivity polycrystalline silicon film is patterned to form an emitter extraction electrode 8E. further,
For example, a PSG film is deposited, and the PSG film is reflowed to form an insulating film 6 (FIG. 11B). At the time of this reflow or independently, a heat treatment is performed to diffuse the impurity from the emitter extraction electrode 8E so that the emitter region 4E is diffused.
To form The conditions of the heat treatment are, for example, 900 ° C., 10
Minutes.

Next, the base extraction electrode 8B, the emitter extraction electrode 8E, the upper electrode 11, the semiconductor region 13c,
Connection holes are opened in the insulating films 6 and 9a on the polycrystalline silicon film 15, for example, a 50 nm thick tungsten film is sputtered, a 150 nm thick tungsten film is sputtered, and a 600 nm thick aluminum film is sputtered. By law
Further, a tungsten film having a thickness of 100 nm is sequentially deposited by a sputtering method, and the laminated metal film is patterned to form a collector electrode 8C, first layer wirings 10a and 10b, wirings 14 and 1,
6 (FIG. 12).

Finally, the collector electrode 8C and the first layer wiring 1
After the interlayer insulating film 17 is formed on the wirings 0a and 10b and the wirings 14 and 16 by, for example, a CVD method, and a connection hole is opened in the interlayer insulating film 17, the second layer wiring 18
To form Further, an insulating film 19 is formed by, for example, a CVD method, and after a connection hole is opened, a metal laminated film to be a bump-underlying metal 20 is deposited by, for example, a sputtering method, and this is patterned to form a bump-underlying metal 20. Thereafter, bumps 21 are formed on the bump base metal 20 by using a known method such as patterning, and the semiconductor device shown in FIG. 1 is completed.

According to the semiconductor device of Embodiment 1 and the method of manufacturing the same, oblique ion implantation is used to implant intrinsic base region 4B1, part of external base region 4B2 and connection region 4B.
B3 can be formed, the base width is reduced, the performance of the semiconductor device is improved, the variation in the element characteristics of the semiconductor device is reduced, and the manufacturing cost is reduced. The manufacturing technology can be provided.

(Embodiment 2) FIG. 13 is a cross-sectional view showing an example of a semiconductor device according to another embodiment of the present invention, in which a portion corresponding to II portion in FIG. It is the expanded sectional view which expanded and shown.

The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in the configuration of the base lead electrode 8B and the external base region 4B2, and the other configurations are the same as those of the semiconductor device of the first embodiment. It is. Therefore, the description is omitted.

In the semiconductor device according to the second embodiment, the base lead electrode 8B comprises a first electrode layer 8B1 and a second electrode layer 8B2.
It is composed of The second electrode layer 8B2 corresponds to the first embodiment.
Is a polycrystalline silicon film in which impurities are introduced at a high concentration.
Although the electrode layer 8B1 contains impurities, the second electrode layer 8
The impurity concentration is lower than that of B2.

The reason why the concentration of the impurity contained in the first electrode layer 8B1 is lower than the impurity concentration of the second electrode layer 8B2 is due to the manufacturing process. That is, the method of manufacturing the semiconductor device of the second embodiment is the same as that of the first embodiment shown in FIG.
In the process shown in (1), a non-doped polycrystalline silicon film is deposited before depositing a boron-doped polycrystalline silicon film to be the base extraction electrode 8B. That is, the boron-doped polycrystalline silicon film becomes the second electrode layer 8B2, and the non-doped polycrystalline silicon film is
It becomes the first electrode layer 8B1.

At the beginning of the formation of the polycrystalline silicon film, boron is not introduced into the first electrode layer 8B1, but boron from the second electrode layer 8B2 diffuses into the first electrode layer 8B1 by a subsequent heat treatment or the like. Has a certain boron concentration. Therefore, the diffusion of boron from the second electrode layer 8B2 is stopped by the first electrode layer 8B1, and the heat treatment is performed so that the boron does not reach the semiconductor substrate 1.
The thickness of B1 can be adjusted. As a result, the external base region 4B2 of the semiconductor device according to the second embodiment can be constituted by impurity regions formed by oblique ion implantation as shown in FIG.

As described above, even if there is no impurity diffusion from the base extraction electrode 8B, in the semiconductor device of the present embodiment, since the external base region 4B2 is formed by oblique ion implantation, no problem occurs in the base contact. No adverse effects such as an increase in base resistance occur. On the other hand, since the external base region 4B2 is formed with a minimum necessary volume, the junction region between the base and the collector is reduced, the capacitance between the base and the collector is reduced, and the high-speed response characteristics of the semiconductor device can be improved.

The heat treatment conditions or the first electrode layer 8B
It is a matter of course that the impurity may be diffused into the semiconductor substrate 1 by adjusting the thickness of the semiconductor substrate 1.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the scope of the invention. Needless to say, it can be changed.

For example, in the above-described embodiment, an example has been shown in which the intrinsic base region 4B1 is formed by only ion implantation from an oblique direction. However, the intrinsic base region 4B1 is formed by using ion implantation from a vertical direction. You may.

In the above embodiment, the case of an npn transistor has been described as an example. However, the present invention can be similarly applied to a pnp transistor by applying the conductivity type in reverse.

In the above embodiment, the example of the isolation region by the field insulating film 2 has been described. However, the isolation region may be formed by a shallow trench element isolation structure.

[0092]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) The speed of the vertical bipolar transistor can be increased.

(2) It is possible to reduce the junction width of the base of the vertical bipolar transistor.

(3) The base resistance of the vertical bipolar transistor can be reduced.

(4) The speed of the vertical bipolar transistor can be increased, the variation between elements can be reduced, and stable and uniform characteristics can be realized.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating an example of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is an enlarged sectional view showing a portion II in FIG.

FIGS. 3A and 3B are cross-sectional views illustrating an example of a manufacturing process of the semiconductor device according to the first embodiment in the order of steps;

FIGS. 4A and 4B are cross-sectional views illustrating an example of a manufacturing process of the semiconductor device according to the first embodiment in the order of steps;

FIGS. 5A and 5B are cross-sectional views illustrating an example of a manufacturing process of the semiconductor device of the first embodiment in the order of steps;

FIG. 6 is a sectional view illustrating an example of the manufacturing process of the semiconductor device of the first embodiment in the order of steps;

FIG. 7 is a partially enlarged cross-sectional view showing an example of the manufacturing process of the semiconductor device of the first embodiment in the order of steps;

FIG. 8 is a partially enlarged cross-sectional view showing an example of the manufacturing process of the semiconductor device of the first embodiment in the order of steps;

FIG. 9 is a partially enlarged cross-sectional view showing an example of the manufacturing process of the semiconductor device of the first embodiment in the order of steps;

FIG. 10 is a partially enlarged cross-sectional view showing an example of the manufacturing process of the semiconductor device of the first embodiment in the order of steps;

FIGS. 11A and 11B are cross-sectional views illustrating an example of a manufacturing process of the semiconductor device according to the first embodiment in the order of steps;

FIG. 12 is a partially enlarged cross-sectional view showing an example of the manufacturing process of the semiconductor device of the first embodiment in the order of steps;

FIG. 13 is a partially enlarged sectional view showing an example of a semiconductor device according to another embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 1a substrate 1b SOI insulating layer 1c single crystal silicon layer 1c1 bond silicon layer 1c2 epitaxial growth layer 2 field insulating film 3 element isolation region 4B base region 4B1 intrinsic base region 4B2 external base region 4B3 connection region 4C collector region 4C1 collector buried layer Reference Signs List 4C2 Intrinsic collector region 4C3 Collector extraction layer 4C4 Pedestal collector region 4E Emitter region 6 Insulating film 8B Base extraction electrode 8B1 First electrode layer 8B2 Second electrode layer 8C Collector electrode 8E Emitter extraction electrode 9a Insulating film 9b Sidewall spacer 9c Insulating film 10a , 10b First layer wiring 11 Upper electrode 12 Capacitive insulating film 13 Impurity semiconductor region 13a to 13c Semiconductor region 14 Wiring 15 Polycrystalline silicon film 16 Wiring 17 Interlayer insulating film 18th Layer wiring 19 Insulating film 20 Bump base metal 21 Bump 22 Sacrificial oxide film 23 Impurity injection layer 24 Semiconductor region 25 Polycrystalline silicon film 26 Silicon oxide film 27 U groove 28, 29 Silicon oxide film 30 Opening C Capacitance element R Resistance element Tr npn Transistor M Distance L Opening radius d Opening depth θ Incident angle fT Cutoff frequency fmax Maximum cutoff frequency rbb Base resistance

Claims (9)

[Claims] 1. A first semiconductor region is formed by introducing an impurity of a first conductivity type into a main surface of a substrate made of a semiconductor or a substrate having a semiconductor layer on a surface thereof, and a first semiconductor region is formed on the first semiconductor region. Forming a second semiconductor region; (b) forming a first isolation region near the surface of the second semiconductor region and a second isolation region reaching below the first semiconductor region; (c) forming the first isolation region. (D) forming a third semiconductor region reaching the first semiconductor region by introducing the impurity of the first conductivity type into a part of the second semiconductor region surrounded by the isolation region; Depositing a first polycrystalline silicon film into which a two-conductivity-type impurity is introduced, and forming the second polysilicon film surrounded by the first isolation region;
The first region in and around the other region of the semiconductor region;
Etching the first polycrystalline silicon film so as to cover the isolation region; (e) forming a first insulating film covering the first polycrystalline silicon film; and (f) forming the first insulating film on the second semiconductor region. Forming an opening in the first insulating film and the first polycrystalline silicon film; and (g) ion-implanting a second conductivity type impurity into the second semiconductor region at the bottom of the opening from a direction oblique to the substrate. A first base region functioning as a base of the transistor, a part of a second base region formed below the first polysilicon film, and an electrical connection between the first base region and the second base region; Forming a fourth semiconductor region consisting of a third base region to be formed; (h) forming a sidewall spacer on the inner wall of the opening; Depositing a second polycrystalline silicon film containing impurities of a first conductivity type on an insulating film; (i) etching the second polycrystalline silicon film while leaving the opening; (j) the substrate Forming the second base region by diffusion from the first polycrystalline silicon film in accordance with the heat treatment. 2. A first semiconductor region is formed by introducing an impurity of a first conductivity type into a main surface of a substrate made of a semiconductor or a substrate having a semiconductor layer on the surface thereof, and a first semiconductor region is formed on the first semiconductor region. Forming a second semiconductor region; (b) forming a first isolation region near the surface of the second semiconductor region and a second isolation region reaching below the first semiconductor region; (c) forming the first isolation region. A step of introducing the impurity of the first conductivity type into a part of the second semiconductor region surrounded by the isolation region to form a third semiconductor region reaching the first semiconductor region; Depositing a first polycrystalline silicon film into which no impurity is positively introduced and a second polycrystalline silicon film into which impurities of the second conductivity type are introduced, and forming the second polycrystalline silicon film in the second semiconductor region surrounded by the first isolation region. The first isolation in and around other areas Etching the second polycrystalline silicon film and the first polycrystalline silicon film so as to cover a region; (e) a first covering the first and second polycrystalline silicon films.
Forming an insulating film; (f) forming an opening in the first insulating film, the second polysilicon film, and the first polysilicon film on the second semiconductor region; and (g) a bottom of the opening. A second conductivity type impurity is ion-implanted into the second semiconductor region from an oblique direction with respect to the substrate to form a first base region functioning as a base of a transistor, formed under the first polycrystalline silicon film; Forming a fourth semiconductor region comprising a second base region and a third base region electrically connecting the first base region and the second base region, (h) forming a sidewall spacer on the inner wall of the opening. Forming and depositing a third polycrystalline silicon film containing impurities of a first conductivity type on the fourth semiconductor region, the sidewall spacer and the first insulating film at the bottom of the opening; (i) forming the opening Etching the third polycrystalline silicon film while leaving the third polycrystalline silicon film. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the ion implantation from an oblique direction in the step (g) is performed by: θ ≧ tan ⁻¹ (d / L); θ is the angle of incidence of ions on the substrate surface, d
Is the depth of the opening, and L is the opening radius. A method of manufacturing a semiconductor device, which satisfies the following conditions. 4. The method for manufacturing a semiconductor device according to claim 1, wherein in the step (g), in addition to ion implantation from an oblique direction, a direction perpendicular to the substrate. Forming the fourth semiconductor region by performing ion implantation from the semiconductor device repeatedly. 5. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is deposited in the step (h) and etched in the step (i) in accordance with the heat treatment of the substrate. Forming a fifth semiconductor region functioning as an emitter of the transistor by diffusing impurities from the second polysilicon film or the third polysilicon film into the fourth semiconductor region. Semiconductor device manufacturing method. 6. The method for manufacturing a semiconductor device according to claim 1, wherein the fourth semiconductor region is formed at a bottom of the opening after forming the sidewall spacer in the step (h). Then, a first conductivity type impurity is ion-implanted into the substrate from an oblique direction, and a fifth impurity functioning as an emitter of the transistor is implanted.
A method for manufacturing a semiconductor device, comprising a step of forming a semiconductor region. 7. A semiconductor substrate or a substrate having a semiconductor layer on a surface thereof, a first semiconductor region formed on a main surface of the substrate and doped with a first conductivity type impurity functioning as an emitter of a transistor. A first base region covering the first semiconductor region and functioning as a base of the transistor; and a second base region formed under a base extraction electrode.
A second semiconductor region including a base region, a third base region electrically connecting the first base region and the second base region, into which impurities of the second conductivity type are introduced, and a lower portion of the second semiconductor region. And a third semiconductor region doped with a first conductivity type impurity functioning as a collector of a transistor, wherein the depth of the bottom surface of the first base region is the bottom surface of the third base region. A semiconductor device characterized by being shallower than a depth of the semiconductor device. 8. The semiconductor device according to claim 7, wherein the second base region is electrically connected to the main surface of the substrate below the base extraction electrode, and is electrically connected to the second base region. A semiconductor device having an external base region formed by diffusion of a type impurity. 9. The semiconductor device according to claim 7, wherein said base extraction electrode is formed on a main surface of said substrate, and said first polycrystalline silicon film does not contain much second conductivity type impurities. A second polycrystalline silicon film formed on the first polycrystalline silicon film, the second polycrystalline silicon film containing a large amount of impurities of a second conductivity type; A semiconductor device, wherein an impurity semiconductor region is not formed by diffusion of the impurity from a base lead electrode.