GB2419230A

GB2419230A - Method of reducing the base resistance of bipolar transistors

Info

Publication number: GB2419230A
Application number: GB0422754A
Authority: GB
Inventors: Jun Fu
Original assignee: X Fab Semiconductor Foundries GmbH
Current assignee: X Fab Semiconductor Foundries GmbH
Priority date: 2004-10-14
Filing date: 2004-10-14
Publication date: 2006-04-19
Also published as: GB0422754D0

Abstract

A method of reducing the base resistance of a bipolar transistor comprising providing an emitter window over a base; carrying out a tilt implant through the emitter window, and thereafter forming at least part of the emitter in this emitter window. The angle of incidence of the tilt implant is chosen so the sidewalls of the emitter window shield the bottom of the emitter window from the tilt implant, thereby allowing the dopant to be implanted in particular regions of the base and protecting the intrinsic base region of the bipolar transistor. The tilt implant serves to introduce a dopant to enlarge the extrinsic base region under the emitter window, thereby reducing the length of link base region. This reduces the overall base resistance and allows for an increased switching frequency of the bipolar transistor.

Description

241 9230 Improvements in Bipolar Transistors The present invention relates

to improved bipolar transistors and methods of producing such transistors.

A known process sequence for manufacturing a bipolar transistor (in this case a non-self aligned SiGe base HBT) is illustrated in Figures IA to IF. Backend process steps (which will be known to those skilled in the art) for completing the manufacture of the transistor are not illustrated. Nevertheless, the device shown in Figure IF will be referred to as transistor 100. The unfinished device shown in Figures IA to IE also carries reference numeral 100, for the sake of simplicity.

A description of a process similar to the one shown in Figures IA to IF can be found in "High performance 0.25,um SiGe and SiGe:C HBTs using non selective epitaxy" by H. Baudry et al., IEEE BCTM 3.1, 0-7803-7019-8/Ol, 2001, pages 52-55.

Referring to Figure IA, the device 100 is formed with a (heavily doped N+) Si Subcollector 1, on which is formed a (lightly doped N type) Sicollector 2, on which is grown a Si/SiGe/Si base epitaxial layer or Si/SiGe/Si stack 3 (in the following usually referred to as "stack" or "epi layer"). The stack 3 is epitaxially grown with a SiGe layer sandwiched between a Si cap layer 6 and a Si buffer layer 4. Usually the SiGe layer 5 or both the SiGe layer 5 and the Si cap layer 6 are in situ doped with boron during epitaxial growth. A thin oxide layer 7 is thermally grown or deposited and patterned by photolithography on top of a central region of the Si cap layer 6 of stack 3. The patterned thin oxide layer 7 and the outer regions of Si cap layer 6 are covered by a (heavily doped) P+ poly Si layer as extrinsic base layer 8. Finally, a top oxide layer 9 covers the extrinsic base layer 8.

Referring now to Figure 1B, a portion of top oxide layer 9 and extrinsic base layer 8 are removed over a central region of the thin oxide layer 7, using a patterning technique, so as to form emitter window 10. The formation of the emitter window is stopped on the thin oxide layer 7. The emitter window may have an approximately rectangular cross section. The area of the emitter window where the thin oxide layer 7 is now exposed will be referred to herein as bottom portion 11. The approximately vertical sides ofthe emitter window 10 will be referred to herein as sidewall portion 12.

Referring now to Figure IC, sidewall reoxidation of those portions 13 of the extrinsic base layer 8 which are located adjacent to emitter window 10 is carried out.

Thus, the entire surface I I and 12 of emitter window 10 is oxidised.

Referring now to Figure IF (there is no Figure ID), nitride sidewall spacers 14 are formed inside the emitter window 10 through nitride layer deposition followed by etch-back.

Referring now to Figure IF, a HE (hydrofluoric acid) dip is performed so as to remove a central portion of thin oxide layer 7 which is not covered by nitride sidewall spacers 14. This is followed by deposition of a (heavily doped) N+ emitter poly layer 15, followed by a patterning step and a subsequent emitter drive-in anneal. The emitter material 15 fills the emitter window 10 and extends on top of emitter window 10 and laterally over a portion of top oxide layer 9. Then the conventional Bipolar technology backend process will complete the manufacture of the transistor 100.

Shown in Figure IF are regions 16 and 17, which are the outer regions of Si cap layer 6, which are located below those portions of extrinsic base layer 8 where the thin oxide layer 7 is not present. Also shown in Figure IF are regions 18 and 19, which are portions of SiGe layer 5 which are situated below regions 16 and 17. The resistance of regions 16, 17, 18 and 19 is relatively low. This is so because P type dopants diffuse from heavily doped extrinsic base poly layer 8 into the underlying epi layer forming the heavily doped P+ regions denoted as 16, 18, and 17, 19 as shown in Fig. IF. It is to be noted however that the figure is only a schematic drawing and, in fact, the diffusion front of outdiffusion from extrinsic base poly layer 8 may come to a stop within the SiGe layer 5 (the case shown in Fig. IF), or extend across the SiGe layer 5 or even Si buffer layer 4 depending on the doping concentration of the epi layer and the extrinsic base poly layer 8 and the thermal budget included in the emitter drive-in anneal and other subsequent thermal cycles for completing the manufacture process.

On the other hand, as a result of the emitter drive-in anneal, that portion of the cap layer 6 which is in contact with emitter poly 15 (i.e. below the opening which has been formed in the thin oxide layer 7) is converted into heavily doped N+ intrinsic emitter region 22 owing to outdiffusion of N type dopants from heavily doped emitter poly 1 5.

With the extra amount of P type dopants added to diffusive extension regions 16, ] 8, 17 and 19, and with outdiffusion of N type dopants to intrinsic emitter region 22, the resistivity of regions 16, 17, 18, 19 and 22 is lower than that of the other P type portions of SiGe layer 5 and Si cap layer 6.

The remaining portions 20 and 21 of Si cap layer 6 (i.e. under the remaining portions of thin oxide layer 7), together with the P type portions of SiGe layer 5 directly below them, are generally referred to as link base regions. The resistance of these (relatively low-doped) regions is significantly higher than that of the heavily doped extrinsic base regions, which comprise the extrinsic base poly layers 8 and the underlying diffusive extension regions 16, 17, 18 and 19 into the original epi layer.

The present inventor has devised a novel method of reducing the resistance of the link base regions by making these regions shorter (in horizontal direction). This is desirable since the total base resistance essentially consists of three components: the resistance of heavily doped P+ (normally doped over 1 E20 cm3) extrinsic base Rex,, the resistance of relatively low doped (around E18-E19 cm3) link base Rib and the resistance of intrinsic base Runts A strongly simplified model of the three resistance components and the regions in which they are to be found is indicated in Figure 3.

Region (a) is the intrinsic region (with the intrinsic base region being located below intrinsic emitter region 22), region (b) the link base region and region (c) the heavily doped P+ base region.

The lower part of Figure 3 shows an approximate electric equivalent diagram of the total base resistance RB. In the electric diagram, the terminal 23 corresponds to the centre of the intrinsic base, and terminal 24 corresponds to a connection made to the extrinsic base regions 8.

It should be noted that Figure 3 (and also Figure 4) is a strongly simplified diagram, whose main purpose is to facilitate the understanding of the disclosed technique. It is not to be understood as an accurate description of the base resistance. As is known, the base resistances in a Bipolar transistor are more complex because base currents flow in a twodimensional manner, so it is not entirely accurate to represent the base resistance simply as a value RB.

Nevertheless, the representation RFS is used herein to denote the base resistance, for the sake of simplicity. In any event, by reducing the resistance Rib of link base regions 20 and 21 the total base resistance RB is reduced as well. Such a reduction is highly desirable since the maximum switching frequency of the transistor can be increased by lowering the base resistance. In embodiments of the present invention the base resistances can be reduced by conversion of portions of the high resistive linkbase regions (below the extrinsic base poly layers) into low resistive extrinsic base regions.

Embodiments of the present invention make use of a tilt implant, which has the effect of extending the heavily doped P+ base region and of reducing the width of the relatively high resistance link base region.

Accordingly, in a first aspect the present invention provides a method of forming an emitter of a bipolar transistor over a base, comprising: providing an emitter window over said base; carrying out a tilt implant through said emitter window; and forming at least a portion of said emitter in said emitter window.

The tilt implant may for example be a boron tilt implant, which serves to implant boron in particular regions of the base of the transistor, so as to reduce the total base resistance.

After the tilt implant through the emitter window has been carried out the emitter may be completed so that at least a portion of the emitter is formed in the emitter window.

Hence, in a closely related second aspect the present invention provides a method of forming an emitter of a bipolar transistor over a base, comprising: providing an emitter window over said base; carrying out a tilt implant; and thereafter forming at least a portion of said emitter in said emitter window.

According to a closely related third aspect the present invention provides a method of forming a bipolar transistor, comprising forming at least a portion of an emitter in an emitter window over a base, comprising carrying out a tilt implant prior to forming said portion of the emitter in said emitter window.

During the tilt implant the bottom portion of the emitter window is preferably substantially shielded from the implant. Conveniently, the sidewall portions of the emitter window can be used to substantially shield the bottom portion from the tilt implant.

Accordingly, in a fourth aspect the present invention provides a method of reducing the base resistance of a base for a bipolar transistor, comprising carrying out a tilt implant through a window structure having a sidewall portion and a bottom portion, wherein the sidewall portion is used to substantially shield the bottom portion from the tilt implant.

In a fifth aspect the present invention provides a bipolar transistor, comprising an emitter, at least part of which is formed in an emitter window, the emitter window being arranged over the base of the transistor, wherein a tilt implant has been carried out through said emitter window prior to formation of said emitter portion.

Apparatus aspects corresponding to all method aspects disclosed herein are also provided, and vice versa. Preferred features are set out in the dependent claims.

US 6,528,375 discloses a technique which employs a tilt implant so as to reduce the total base resistance. The tilt implant is not performed through any emitter window (no such emitter window being provided). Instead, the tilt implant is carried out after formation of the emitter.

Some preferred embodiments of the present invention will now be described by way of example only and with reference to the accompanying drawings, in which: Figure I A is a first process step in the manufacture of a known transistor.

Figure I B is a second process step in the manufacture of the known transistor.

Figure 1 C is a third process step in the manufacture of the known transistor.

Figure I E is a fourth process step in the manufacture of the known transistor.

Figure I F is a fifth process step in the manufacture of the known transistor.

Figure 2A is a first process step in the manufacture of a transistor according to the present invention.

Figure 2B is a second process step in the manufacture of the transistor according to the present invention.

Figure 2C is a third process step in the manufacture of the transistor according to the present invention.

Figure 2D is a fourth process step in the manufacture of the transistor according to the present invention.

Figure 2E is a fifth process step in the manufacture of the transistor according to the present invention.

Figure 2F is a sixth process step in the manufacture of the transistor according to the present invention.

Figure 3 schematically shows regions of the completed transistor manufactured according to Figure 1.

Figure 4 schematically shows regions of the completed transistor manufactured according to Figure 2.

Figure 5 is a simplified top view of two emitter windows to illustrate a second embodiment ofthe present invention.

The technique of the present invention will be described using a non-self aligned SiGe base NPN HBT (heterojunction bipolar transistor) and using a boron implant as the tilt implant. It will be understood that this is purely by way of example only. Some variations which are considered to fall within the scope of the present invention are indicated towards the end of the description. Other variations will be clear to one skilled in the art.

The manufacturing steps (illustrated in Figures 2A to 2C) of the transistor 200 according to the described embodiment of the present invention are identical to the first three manufacturing steps (illustrated in Figures 1 A to I C) of the known transistor, and reference should be made to the description of Figures IA to IC for an understanding of the first three manufacturing steps shown in Figures 2A to 2C.

On completion of the process steps shown in Figures 2A to 2C a boron tilt implant is performed as illustrated in Figure 2D. Preferably, at least two such tilt implants as indicated by arrows 30 and 40 are carried out from opposite sides (or along fixed symmetrical directions), so as to implant the two regions 31 and 41 located within the Si/SiGe/Si base epi layer 3 under the outer regions of thin oxide layer 7. The implant is preferably carried out so that the implanted regions lie just outside the emitter window 10, avoiding the central region of the epi layer 3 which is located under the emitter window 10. To this end the angle of incidence (which in Figure 2D is the angle formed between e.g. implant 30 and the surface normal of the bottom portion 11 of the emitter window) is preferably chosen such that the left sidewall portion of the emitter window shields the bottom portion 11 of the emitter window from tilt implant 30. By _ 1 _ _ UJiJ.

making the same choice for the angle of incidence between implant 40 and the surface normal of the bottom portion 11 the right sidewall portion of the emitter window will shield the bottom portion 11 from the tilt implant 40. On the other hand, the angle of incidence should be chosen as small as possible so that as much of the sidewalls 12 as possible is exposed to the tilt implants, especially the lower regions. In the case of a rectangular cross section of the emitter window 10 the angle of incidence a is preferably chosen to be a = arctan (w/h), wherein w is the width of the bottom portion I I of the emitter window and h is the (internal) height of the sidewall portion 12 of the emitter window, i.e. a distance from the intersection of the bottom portion 11 and sidewall portion 12 to the top of sidewall portion 12. It will be appreciated that the angle of incidence may need to be adjusted in the case of a non- rectangular cross section of the emitter window.

It will further be understood that indications of position or orientation (such as top, bottom, left, right, vertical, horizontal) are not to be understood in a limiting sense, these indications corresponding to the position and orientation of features shown in the drawings so as to facilitate understanding of the drawings. It will be appreciated that in use or during manufacture the position or orientation of features shown in the drawings does not have to be the same as that shown in the drawings.

After completion of the tilt implants the process steps shown in Figures 2E and 2F essentially correspond to the process steps shown in Figures IE and IF, and reference should be made to the description of Figures IE and IF. Hence, nitride sidewall spacers 14 are formed, followed by a HE dip, followed by N+ emitter poly layer deposition and patterning, followed by emitter drive-in anneal. The transistor 200 shown in Figure 2F can then be completed with the conventional Bipolar technology backend process. As can be understood from a comparison of Figure 2F with Figure I F. the relatively low resistance regions 36, 37, 38 and 39 in the Si cap layer 6 and the epi layer 5 are significantly larger than regions 16, 17, 18 and 19 shown in Figure IF. A significant part of portions 36, 37, 38 and 39 extends under the thin oxide layer 7, towards the intrinsic base region. In turn, the relatively high resistance regions 50 and 51 and the P type portions of the SiGe layer 5 directly below regions 50 and 51 (in Figure 2F confined to regions located below nitride spacers 14) are significantly smaller than regions 20 and 21 and the P type portions of the SiGe layer 5 directly below regions 20 and 21 shown in Figure I F. Central region 52 in Figure 2F has approximately the same dimensions as region 22 in Figure IF.

The relatively small size of link base regions 50 and 51 results in a lower total base resistance RB, as illustrated by the (strongly simplified) equivalent electric diagram in the lower part of Figure 4. The regions (a), (b) and (c) correspond to those shown in Figure 3, although of course regions (b) are now smaller.

The two tilt implants 30 and 40 indicated in Figure 2D would in most circumstances be sufficient to reduce the base resistance in transistors in which the emitter windows are all oriented in the same way. It will be appreciated that in many cases the emitter windows can be regarded as a trench, extending, in the examples shown in Figures 1 to 4, in a direction perpendicular to the paper plane. In such a case all sidewalls will shield the corresponding bottom portions of each emitter window from the tilt implants. However, in some cases the emitter window "trenches" may extend in more than one direction. In this case several pairs of tilt implants from opposite sides should be performed, one pair of opposite implants for each direction along which the emitter window trenches extend. This is illustrated in Figure 5, which shows a top view of two emitter window trenches 60 and 70. In the example shown in Figure 5 the orientation of trenches 60 and 70 form a 90 angle, but it will be appreciated that in principle any angle is possible.

The process sequence essentially follows that of Figures 2A to 2F but two pairs of boron implants are carried out per trench direction. Thus Figure 5 shows four tilt implants 61, 62, 71 and 72. Tilt implants 61 and 62 from opposite sides form one pair of tilt implants for reducing the base resistance associated with emitter window trench 60, and tilt implants 71 and 72 form a pair oftilt implants from opposite sides for reducing the base resistance associated with emitter window trench 70. Only the horizontal component of tilt implant 61, 62, 71 and 72 is shown in Figure 5. It will be understood that each tilt implant also has a vertical component, i.e. towards the respective trench 60 and 70 (i.e. perpendicular to the paper plane). Since the tilt implant would in many cases cover a region much larger than one trench, in the case of the example shown in Figure 5 the tilt implants 61 and 62 would also implant the bottom portion of trench 70, and the tilt implants 71 and 72 would also implant the bottom portion of trench 60. In order to avoid this, those trenches which extend parallel to the horizontal component of a particular tilt implant are masked before that tilt implant. Once the respective pair of tilt implants is completed the masking is removed, and the masking, implant and removal steps are repeated for the other direction of trenches. I.e. in the example of Figure 5, in order to achieve implants in only the desired regions, the following sequence of process steps would be carried out: 1. Mask trench 70.

2. Perform tilt implants 61 and 62.

3. Remove masking from trench 70.

4. Mask trench 60.

5. Perform tilt implants 71 and 72.

6. Remove masking from trench 60.

The invention has been explained with reference to a SiGe base NPN HBT. The invention can be applied to other types of transistors, including Si (homojunction) bipolar junction transistors (BJT). Similarly, the invention is not limited to the use of Si or SiGe.

In the described embodiments the tilt implants were boron ion implants. Other ions could be used for the tilt implant.

The embodiment illustrated in Figure 2 has an epitaxial base 3. The invention is not limited to the use of an epitaxial layer. For example, an ion-implanted base could be used instead.

The N+ emitter poly material may be arsenic or phosphorus, but other materials could be used as well.

The term "shielding" has been used in the present specification, including the claims. It will be understood that a small degree of exposure of the bottom of the emitter window to the tilt implant may be acceptable, as long as the performance of the transistor is not significantly affected. In particular, the intrinsic emitter/base doping profiles should normally not be (significantly) disturbed, nor should any (significant) damage be introduced to intrinsic regions as this may cause leakage or affect the reliability ofthe transistor.

The two tilt implants from opposite sides are preferably carried out successively, but could also be performed simultaneously.

Although the invention has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in the invention, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.

Claims

CLAIMS: 1. A method of forming an emitter of a bipolar transistor over a

base, comprising: providing an emitter window over said base; carrying out a tilt implant through said emitter window; and forming at least a portion of said emitter in said emitter window.
2. A method of forming an emitter of a bipolar transistor over a base, comprising: providing an emitter window over said base; carrying out a tilt implant; and thereafter forming at least a portion of said emitter in said emitter window.
3. A method according to claim 1, wherein carrying out said tilt implant comprises carrying out said tilt implant through said emitter window.
4. A method according to any of claims I to 3, wherein on forming of the emitter, the emitter window is substantially filled.
5. A method according to any of claims I to 4, wherein the angle of incidence of the tilt implant is chosen in dependence upon the dimensions of the emitter window.
6. A method according to claim 5, wherein the emitter window comprises a bottom portion and a sidewall portion.
7. A method according to claim 6, wherein the angle of incidence is chosen such that the sidewall portion of the emitter window substantially shields the bottom portion of the emitter window from the tilt implant.
8. A method according to claim 6 or 7, wherein the angle of incidence (= a) is chosen to be a 2 arctan (w/h), wherein 0 < a < 90 and wherein w is the width of the bottom portion of the emitter window and h is the height of the sidewall portion as measured from the surface of the bottom portion.
9. A method according to any of claims 6 to 8, comprising carrying out at least two such tilt implants from opposite sides with respect to the surface normal of the bottom portion of the emitter window.
10. A method according to claim 9, further comprising carrying out two further such tilt implants from opposite sides with respect to each other.
11. A method according to claim 10, wherein the angle between the projections of the directions of a said tilt implant and a said further tilt implant is between 60 and 120 , preferably between 75 and 105 , more preferably between 80 and 100 and yet more preferably between 85 and 95 .
12. A method according to claim 10 or I 1, comprising forming at least two emitters of at least two bipolar transistors over at least two bases, an emitter window being provided over each base, the method comprising: masking at least a first one of said emitter windows by means of a first masking structure; carrying out said tilt implants; removing said first masking structure; masking at least a second one of said emitter windows by means of a second masking structure; carrying out said further tilt implants; removing said second masking structure; and forming emitter portions in each emitter window.
13. A method according to any of claims I to 12, wherein said tilt implant is a boron tilt implant.
14. A method according to any of claims 1 to 13, wherein the or each base is formed on a collector.
15. A method according to any of claims I to 14, wherein an oxide layer is used to stop emitter window patterning.
16. A method according to any of claims I to 15, further comprising inserting sidewall spacers into the or each emitter window, preferably nitride sidewall spacers.
17. A method according to any of claims I to 16, wherein the tilt implant is performed so as to cause a link base region of said base to become smaller and/or shorter, thereby reducing the base resistance.
18. A method of forming a bipolar transistor, comprising forming at least a portion of an emitter in an emitter window over a base, comprising carrying out a tilt implant prior to forming said portion of the emitter in said emitter window.
19. A method of reducing the base resistance of a base for a bipolar transistor, comprising carrying out a tilt implant through a window structure having a sidewall portion and a bottom portion, wherein the sidewall portion is used to substantially shield the bottom portion from the tilt implant.
20. A bipolar transistor, comprising an emitter, at least part of which is formed in an emitter window, the emitter window being arranged over the base of the transistor, wherein a tilt implant has been carried out through said emitter window prior to formation of said emitter portion.
21. A method or a transistor, substantially as herein described with reference to, or as illustrated in, Figs. 2A to 2F, 4 or 5 of the accompanying drawings.