JPH11339478A - Static random access memory and saving method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an SRAM in which a failed memory cell can be saved as a good memory cell by providing means for increasing current of a memory cell when a decision is made that high temperature or low temperature data is not retained well because of insufficient current supply from a power supply. SOLUTION: A high resistance load type static random access memory comprises a series circuit of a resistor 5' and a switching element SW3 connected in parallel with a high resistance load R5, and a series circuit of a resistor 6' and a switching element SW4 connected in parallel with a high resistance load R6. An L level (GND) is fed to the control input of the switching elements SW3, SW4 by cutting the fuse element FU 2 of a control circuit CC2 by means of laser, or the like, and the switching element SW3, SW4 are turned on constantly thus connecting the resistor 5' (R6') in parallel with the high resistance load R5 (R6). Consequently, current supply from a power supply Vcc increases to eliminate insufficient retaining of high temperature or low temperature data thus saving the memory cell.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a high resistance load type static random access memory.

[0002]

2. Description of the Related Art In a conventional high resistance load type static random access memory (SRAM), a test is performed at both a high temperature and a low temperature in order to check whether or not a failure occurs within an operation guarantee temperature range. Was. For SRAM,
Testing of data retention at high and low temperatures is important. The mechanism of defective data retention at high and low temperatures in the SRAM will be described below.

FIG. 3 shows a circuit configuration diagram of a memory cell of a high resistance load type SRAM. In the figure, R1 and R2 are high resistance loads, and TR1 and TR2 are N-channel MOS transistors for driving memory cells. Also, TR3
And TR4 are a memory cell and a data line pair DL1 and DL
2 based on the signal level of the word line WL.
This is an N-channel MOS transistor for a transfer gate to be cut off. The memory cell is supplied with a current IR from a power supply Vcc. In the memory cell, M
There are an off-state leakage current Ioff of the OS transistor and a junction leakage current IL.

FIG. 4 shows general temperature characteristics of IR, Ioff, and IL. If Ioff or IL is larger than IR, the memory cell cannot hold data. Therefore, if the temperature TH satisfying IR <Ioff is lower than the upper limit TOPH of the operation guarantee temperature range, high-temperature data retention failure occurs, and if the temperature TL satisfying IR <IL is higher than the lower limit TOPL of the operation guarantee temperature range, low temperature data retention occurs. It becomes bad. Therefore, in order to guarantee the data holding function of the SRAM, conventionally, tests on both the high temperature side and the low temperature side have been required.

[0005]

In the prior art, as a result of the test, a memory cell determined to be a low-temperature data retention defect or a high-temperature data retention defect due to a shortage of a supply current from a power supply is particularly provided with a defect remedy means. Was not taken, resulting in a decrease in yield.

The present invention has been made in view of the above-mentioned conventional problems, and means for increasing a current for a memory cell determined to have a low-temperature or high-temperature data retention failure due to insufficient supply current from a power supply. To provide a static random access memory that can rescue a defective product as a non-defective product.

[0007]

According to the first aspect of the present invention, there is provided a static random access memory according to the present invention, wherein a resistor and a switching element are connected in parallel to a high resistance load. And a series circuit is provided.

According to a second aspect of the present invention, there is provided the static random access memory according to the first aspect, wherein an external terminal for controlling a state of the switching element during a test is provided.
In actual use, a control circuit including a fuse element for controlling the state of the switching element is provided.

Further, the defect remedy method for a static random access memory according to the present invention according to claim 3 is provided in claim 1.
Or a defect remedy method for a static random access memory according to item 2, wherein, in actual use, the switching element is turned on to increase a current supplied from a power supply and relieve a data retention defect. It is a feature.

According to the static random access memory of the present invention, a predetermined signal is inputted from an external terminal to a memory cell determined to be defective in data retention in the low and high temperature tests, and the switching means is turned on. As a state, a resistor is connected in parallel with the high resistance load, and the test is performed again with the supply current from the power supply increased, and as a result, if the data retention defect has been eliminated, fuse with laser etc. By cutting off the element, the switching element is always turned on, and a resistor is connected in parallel with the high-resistance load, thereby increasing the current supplied from the power supply to the memory cell and performing relief.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows an SRA according to an embodiment of the present invention.
FIG. 3 is a circuit configuration diagram of M memory cells.

In the figure, R5 and R6 are high resistance loads, and TR1 and TR2 are N channel MOS transistors for driving memory cells. Also, TR3 and TR4
Is an N-channel MOS transistor for a transfer gate that connects and disconnects the memory cell and the data line pair DL1 and DL2 based on the signal level of the word line WL.

A feature of the present invention is that a resistor R5 'and a switching element SW connected in parallel to a high resistance load R5 are provided.
3 and a series circuit of a resistor R6 'and a switching element SW4 connected in parallel to a high resistance load R6. The switching elements SW3 and SW4 are switching elements that are turned on when the control input is at the L level and turned off when the control input is at the H level, and can be configured by, for example, P-channel MOS transistors. In addition, T2, during the test,
An external terminal for supplying an L-level signal to control inputs of the switching elements SW3 and SW4.
A control circuit that includes a fuse element FU2 and two resistors PU2 and PD2, and provides an H-level or L-level signal to control inputs of the switching elements SW3 and SW4 during actual use.

When no signal is input to the external terminal T2, an H level signal is applied to the control inputs of the switching elements SW3 and SW4 by the pull-up resistor PU2 and the fuse element FU2 of the control circuit CC2. And the switching elements SW3 and SW4 are in the off state. When an L-level signal is supplied from the external terminal T2, the switching elements SW3 and SW4 are turned on, and the resistors R5 ′ and R5 are connected in parallel with the high-resistance loads R5 and R6.
6 'is connected. Therefore, the load resistance value of the memory cell becomes (R5.R5 ') / (R5 + R5') and (R6.R6 ') / (R6 + R6'), and the current value supplied from the power supply Vcc increases. I do. FIG. 4 shows the relationship between the current IR supplied from the power supply, the off-state leakage current Ioff, the junction leakage current IL, and the temperature when no signal is input to the external terminal T2. As a result, a low-temperature data retention failure occurs at a temperature TL, and a high-temperature data retention failure occurs at a temperature TH. Next, an L-level signal is input to the external terminal T2, the switching elements SW3 and SW4 are turned on, and IR ″ and Ioff when the current supplied from the power supply Vcc becomes IR ″. FIG. 2 shows a relationship between IL, and IL, and temperature. When the external terminal T2 is at the L level,
The memory cell that has failed at the temperature of TL
The memory cell which has failed at L ″ (<TL) and has failed at the temperature of TH has a temperature TH ″ (> TH)
Is bad. The lower limit temperature of the operation guarantee temperature range is TOP
L, if the upper limit temperature is TOPH, TL ″ <TOP
The resistances R5 ′ and R5 are set so that L, TH ″> TOPH.
By determining the resistance value of 6 ′, a memory cell having a low-temperature and high-temperature data retention failure can be made a good product.

As a result of the low-temperature and high-temperature tests, the memory cell determined to have a low-temperature or high-temperature data retention defect is further characterized by:
A test is performed by applying an L level signal to the external terminal T2.
For the memory cell determined to be remedied for the data retention defect, the fuse element FU2 of the control circuit CC2 is cut by a laser or the like, so that the switching element SW3,
To the control input of SW4 via the resistors PU2 and PD2,
An L level (GND) signal is applied to turn on the switching elements SW3 and SW4 at all times, thereby reducing the load resistance value and increasing the supply current from the power supply Vcc. As a result, the memory cell having the data retention failure is remedied as a good product.

If the external terminal and the control circuit are provided for each bit line or word line, the number of fuses to be cut is reduced, and the success rate of the relief is improved.

[0018]

As described above in detail, according to the present invention, a memory cell which has been defective in data retention due to insufficient supply current from a power supply is remedied as a good product by increasing the supply current. Because it was configured to be able to
The yield can be improved, and the practical effect is extremely large.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of a memory cell in an SRAM according to an embodiment of the present invention, in which a resistor is connected in parallel to a high-resistance load.

FIG. 2 shows a supply current IR ″ from a memory cell power supply, a junction leak current IL, and a transistor off-state leak current Ioff when a resistor is connected in parallel to a high-resistance load.
FIG. 4 is a diagram showing a relationship between the temperature and the temperature.

FIG. 3 is a circuit configuration diagram of a memory cell in a conventional high resistance load type SRAM.

FIG. 4 shows a supply current IR from a memory cell power supply, a junction leak current IL,
FIG. 5 is a diagram illustrating a relationship between a leakage current Ioff of a transistor and an off-state and a temperature.

[Explanation of symbols]

R5, R6 High resistance load R5 ', R6' Resistance SW3, SW4 Switching element T2 External terminal CC2 Control circuit FU2 Fuse element

Claims (3)

[Claims] 1. A static random access memory of a high resistance load type, comprising a series circuit of a resistor and a switching element connected in parallel to a high resistance load. 2. The static random access memory according to claim 1, wherein an external terminal for controlling a state of the switching element during a test,
A static random access memory comprising a control circuit including a fuse element for controlling a state of the switching element. 3. The method for relieving a defect of a static random access memory according to claim 1, wherein a current supplied from a power supply is increased by turning on said switching element in actual use. A method for relieving a defect in a static random access memory, comprising relieving a data retention defect.