JPS62143300A - Redundant constitution selection circuit - Google Patents

Abstract

PURPOSE:To reduce power consumption by providing a program link in series with one of P and N channel MOSFETs constituting a CMOS inverter circuit and using a signal formed based on a redundancy selection signal to apply complementary switch operation. CONSTITUTION:A CMOS inverter circuit 2 is adopted for the 1st stage circuit inputting a control signal phi, a program link 3 is provided between the output terminal and a drain of a N-channel MOSFETQ2, the program link 3 is programmed depending on the address to be relieved to set the relieved address. Then a redundancy row decoder circuit 11 is subjected to selection control in response to the program state, the input level of the control signal phi and the supplied address signal, and no through-current flows to the CMOS inverter circuit regardless of the input level of the control signal phi and the program state of the program link 3. Thus, the power consumption in the redundancy address setting circuit is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a redundant configuration selection circuit, and relates to a technique that is effective when applied to, for example, a redundant address setting circuit for selecting spare bits of a semiconductor memory device.

[Background technology]

In order to improve the yield of semiconductor memory devices, a redundant configuration including spare bits to replace defective bits is sometimes adopted.

In such a redundant configuration, a redundant address setting circuit selects a spare bit to replace a defective bit. The redundant address setting circuit has a program link such as an electric fuse corresponding to each bit of the address signal and a resistance element such as a pull-down resistor connected in series with the program link, and the redundant address setting circuit has a program link such as an electric fuse corresponding to each bit of the address signal and a resistance element such as a pull-down resistor connected in series with the program link. By cutting off the program link in advance, the address to be rescued can be set. When an input address signal is supplied to the address buffer, the input address signal is compared with the level at the connection point between the program link and the pull-down resistor, and when the results match in terms of the focus correspondence of the address signal, the reserved bit is is selected.

However, in this configuration in which the program link and pull-down resistor are connected in series between the power supply terminal and the ground terminal, current always flows through the program link when it is not disconnected, increasing power consumption.

, the present inventor has proposed a PSRAM (Static Random Access Memory) which receives almost the same external signals as an SRAM (Static Random Access Memory) and has the basic structure of a DRAM (Dynamic Random Access Memory) which does not employ an address multiplexing method. In pseudo-static random access memory (SRAM), we investigated a configuration in which data stored in memory cells is retained by battery backup, similar to SRAM. In this case, PSRAM requires a refresh operation just like DRAM due to its nature, so taking into consideration the current supply capacity of the battery, it is necessary to reduce power consumption in battery backup operation mode. If the above-mentioned redundant address setting circuit is included, power is wasted in this circuit, and sufficient battery backup time cannot be guaranteed.

Examples of documents describing redundant configurations of semiconductor storage devices include "rLsI Handbook, published by 1-Om Co., Ltd.", November 30, 1980, P2S5 to P2S5.

[Purpose of the invention]

An object of the present invention is to provide a redundant configuration selection circuit that can achieve low power consumption.

The foregoing and other objects and novel features of the present invention will become apparent from the present specification and accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a P-channel type MO5FET and an N-channel type MOSFET are provided, which are coupled to form a CMOS inverter circuit, and the two MOSFETs are
A program link is provided in series with each of T, for example, an N-channel MOSFET, and the above two MOSFETs are
Power consumption is reduced regardless of whether the program link is conductive or non-conductive by performing a complementary switching operation using a signal formed based on a redundancy selection signal indicating whether redundancy selection has been programmed.

〔Example〕

FIG. 1 is a circuit diagram showing an embodiment in which the present invention is applied to a redundant address setting path of a PSRAM.

The redundant address setting circuit 1 shown in the figure is, although not particularly limited, a circuit for selecting a spare word line to replace a defective bit in PSRAM, and a defective bit is detected as a test result such as a semiconductor wafer test. When the defective bit is detected, the address indicating the defective bit, that is, the row address to be repaired, is set in the program link in each.

The redundant address setting circuit 1 receives row address signals Ax, -Axn supplied to the row decoder circuit 12 of the PSRAM.
The number of unit setting circuits Ec,=Ecn equal to the number of bits is provided, and each unit setting circuit has the same configuration.

The unit setting circuit Ec shown as a representative in the figure is provided with a CMOS inverter circuit 2 consisting of a P-channel type MOSFET QI and an N-channel type MOSFET Q2 as its first input stage. A program link 3 is provided between the output terminal of this CMOS inverter circuit 2 and the drain of MO8FETQ2. This program link 3 may be electrically conductive and physically cuttable in the initial state, such as a vapor-deposited aluminum layer or polycrystalline silicon layer, or non-conductive in the initial state, such as a polycrystalline silicon layer. It is possible to appropriately adopt a conductive material that is conductive and whose conductivity is determined by laser annealing. In each program link 3, when the use of a redundant configuration is instructed due to the presence of a defective pin, each unit setting circuit Eco-Ecn is programmed to be conductive or non-conductive in accordance with the address to be repaired. It is something that will be done.

A P-channel type MO5FET Q3 is connected to the output terminal and power supply terminal of the CMOS inverter circuit 2 to maintain the output of the inverter 2 at a high level when the program link 3 is cut off.

The gates 1 to 1 of this power switch MOSFET Q3 correspond to the output level of the CMOS inverter circuit 2.
The inverted level is supplied by the inverter circuit 4. The output terminal of the CMOS inverter circuit 2 is connected to the CMOS inverter circuit 2.
Exclusive NOR (E
xclusive NOR) is coupled to one input terminal of the gate circuit 5. The other input terminal of this exclusive NOR gate circuit 5 is the row address signal Ax.
, is coupled to the input line that is supplied.

A control signal φ is commonly input to the CMOS inverter circuit 2 provided at the first input stage of each unit setting circuit Eco-Ecn. A latch circuit 6 that stores information regarding whether or not to use a redundant configuration in a circuit that forms this control signal φ, and outputs a redundancy selection signal φre of a level corresponding to the information.
including. Although this latch circuit 6 is not particularly limited, it can have a circuit configuration similar to that of the unit setting circuit Eco, in which the gate circuit 5 is omitted. For example, an inverted signal of the output of the gate circuit 8 is supplied to an inverter corresponding to the inverter 2 in the latch circuit. If a redundant configuration is not used, a program link (not shown) in the latch circuit 6 is programmed. In other words, the program link within the latch circuit 6 is cut off. Therefore, in this case, redundancy selection signal φre is always kept at high level.

The output terminal of the latch circuit 6 is coupled to one input terminal of a Nant gate circuit 7, and the other input terminal of the Nant gate circuit 7 is coupled to the output terminals of the circuits 1 to 8. This OR gate circuit 8 has control signals φsr and c.
e is supplied. The control signal ce is an internal signal generated by a controller (not shown) based on an external chip selection signal CE supplied to the PSRAM, and is set to a high level (chip selection level) in a chip selection state.

The control signal φsr is an internal signal generated by a controller (not shown), and is set to a high level in a self-refresh operation mode using battery backup. The self-refresh operation is performed substantially independently of external signals, and in this operation mode, the address signal that specifies the address of the memory cell to be refreshed is 1.
A refresh counter (not shown) sequentially outputs the data at predetermined time intervals.

Although a detailed explanation of the PSRAM itself is not shown since it is not directly related to the present invention, its outline is as follows.

In other words, PSRAM includes a memory array, a data line precharge circuit, a sense amplifier, and the circuit shown in FIG.
It consists of a column switch circuit, a data input/output circuit, a column decoder circuit, a row address buffer, a column address buffer, an address multiplex circuit, an address signal change detection circuit, a controller, and a refresh controller.

The memory array has a plurality of dynamic memory cells arranged in a matrix, and its word lines and redundant word lines are driven by the outputs of the row decoder circuit and redundant row decoder circuit shown in FIG. The data line of the memory array is coupled on one side to an input/output terminal of a sense amplifier and a precharge circuit, and on the other hand to an input/output circuit via a column switch circuit controlled by a column address decoder.

The refresh controller includes refresh address generation circuitry, such as a refresh address counter.

The address multiplex circuit, whose operation is controlled by, for example, a refresh controller, selects one of the output of the row address buffer and the output of the refresh address generation circuit, and selects one selected row address 18.
The signal is supplied to the row decoder circuit (12 in FIG. 1).

The address signal change detection circuit detects a change in the address signal supplied to the row address decoder and the column address decoder, and outputs a detection pulse to the controller.

The controller receives an externally supplied chip selection signal,
It outputs various timing signals for controlling the operation of internal circuitry in response to the write enable signal, the refresh control signal and the vapor detection pulse. That is, when the chip selection signal is set to the selection level and when the detection pulse is output from the address signal change detection circuit, the controller 1 first sets the word line and the redundant word line to the non-selection level in response. The word line selection timing signal supplied to the row decoder and redundant row decoder is set to a non-selection level such as a low level, and the timing signal for controlling the operation of the sense amplifier is set to a level such as a low level. .

At the same time as the word line and the redundant word line are set to the non-select level and the sense amplifier is set to the non-select level, a precharge timing signal is generated for a predetermined period of time, and this causes the pre-charge. The circuit is activated. That is, each data line of the memory array is set to a precharge level.

While the operation of the precharge circuit is stopped, the word line selection timing signal is again set to a selection level such as a high level, and in response, a word line or a redundant word line begins to be selected. After selecting word line or redundant word line,
The sense amplifier is reactivated. After the sense amplifier operates, a data line selection timing signal is supplied to the column address decoder, and the column address decoder outputs a data line selection signal. An appropriate data line of the memory array is selected in response to the data line selection signal and coupled to the input/output circuit. Note that if the refresh controller outputs a control signal indicating a refresh operation, control signals for column-related circuits such as a column address decoder are not required.

A CMOS inverter circuit 2 provided at the first input stage of each unit setting circuit Ec, ``-Ecn outputs a control signal at a level inverted by the MOS inverter circuit 9 with respect to the output level of the Nant gate circuit 7. When the redundancy selection signal φre is set to a high level (redundancy selection level), that is, when the redundant configuration is utilized, the control signal φsr is set to a high level (self-refresh operation level) or When the control signal ce is set to a high level (chip selection level), the control signal φ is set to a high level (unit setting circuit operation level).In other words, the control signal φ is set to enable the redundant configuration. The control signal φ is set to a high level when a predetermined memory cell is to be addressed in the state. Otherwise, the control signal φ is set to a low level.

The output level of the CMOS inverter circuit 2 when the control signal φ is set to high level is as follows. That is, if program link 3 is made non-conductive, C
The output of the MOS inverter circuit 2 is kept at a high level because an appropriate capacitor C existing at its output node is charged in advance via the MOSFET QI, and the MOSFET Q3 is turned on. On the other hand, if the program link 3 is in a conductive state, the output of the CMOS inverter circuit 2 is set to a low level in response to the control signal φ being set to a high level.

Note that when the control signal φ is at a low level, the output of the CMOS inverter circuit 2 is fixed at a high level regardless of whether the program link 3 is conductive or non-conductive.

When receiving the high-level control signal φ, the inverter circuit 4 in each unit setting circuit Eco=Ecn supplies signals of different levels to the exclusive NOR circuit 5 depending on whether the program link 3 is conductive or non-conductive. . On the redundant address setting circuit of this embodiment, each program link 3
When the row address signals Ax, . It is programmed in advance so that it can be input to the exclusive NOR gate circuit 5. That is, the address to be rescued is set by this. When the address to be rescued is supplied, the control signal φ is When set to high level, the outputs of all exclusive NOR circuits 5 are set to high level in synchronization with this.

The output terminals of all exclusive NOR circuits 5 and the output terminal of the latch circuit 6 are coupled to the input terminal of an AND gate circuit 10. The output terminal of this AND gate circuit 10 is connected to a control terminal of a redundant row decoder circuit 11 and further connected to a control terminal of a normal row decoder circuit 12 via a CMOS inverter circuit 13. The control terminals of both row decoder circuits 11 and 12 are for controlling each row decoder circuit to be in an operable state or in an inoperable state, and select the operating state by receiving a high level signal.

In the case of PSRAM, it should be understood that the output timing of the signals output from the row decoder circuit 12 and redundant row decoder circuit 11 is defined by the word line selection timing signal.

The reason why the control signal φre is inputted to the AND gate circuit 10 is to prevent the normal row decoder circuit 12 from being rendered inoperable when the control signal φ is at a low level. That is, when the control signal φ is at a low level, the output of the CMOS inverter circuit 2 is set at a high level regardless of the program state of the program link 3. are various control signals φre, φs
r.

A low level signal is supplied regardless of Ce.

Therefore, when all the row address signals supplied to the exclusive NOR circuits of each unit setting circuit E Co-E an are at low level, all the exclusive NOR circuits 5 receive high level signals even when the redundant configuration is not used. The signal will be output.

In this case, control signal φre is used to prevent row decoder circuit 12 from being erroneously rendered inoperable.

In the redundant address setting circuit 1 configured as described above, when a defective bit occurs in the PSRAM, the address to be relieved is determined by programming conduction or non-conduction of the program link 3 of each unit setting circuit Eco=Ecn. is set. At this time, the latch circuit 6 is also programmed, and the redundancy selection signal φre is always kept at a high level. In a state where the redundant configuration is enabled, when the control signal φS is set to high level (self-refresh operation level) or the control signal Ce is set to high level (chip selection level), the control signal φ is set to high level (unit setting circuit operation level).As a result, one input terminal of the exclusive NOR gate circuit 5 of each unit setting circuit Ec, ~Ear (in accordance with the program state of the program link 3) is set to high level (unit setting circuit operation level). At this time, each exclusive no game 1 to circuit 5 compares the row address signal supplied from the other input terminal with the above input signal, and all of them match based on the bit correspondence of the row address signal. In this case, the AND gate circuit 1o outputs a high level signal.This high level output signal enables the redundant row decoder circuit 11 to operate.
The normal row decoder circuit 12 is rendered inoperable. The redundant row decoder circuit 11 that is activated selects a predetermined spare word line based on the address signal input at this time.

When the use of the redundant configuration is not selected, the redundancy selection signal φre is always kept at a low level, so the output of the AND gate circuit 1o is fixed at a low level, and as a result, the normal row decoder circuit 12 can operate. be put into a state.

In this way, the redundant address setting circuit 1 of this embodiment has a CMOS inverter circuit 2 in the first stage circuit which inputs the control signal φ.
A program link 3 is provided between its output terminal and the drain of the N-channel type M○5FET Q2 constituting the CMOS inverter circuit 2, and this program link 3 is programmed according to the address to be rescued. This sets the address to be rescued. Then, as described above, selection control of the redundant row decoder circuit 11 is performed according to the program state, the input level of the control signal φ, and the supplied address signal. Regardless, since no through current flows through the CMOS inverter circuit, power consumption in the redundant address setting circuit can be reduced. In particular, power consumption during the standby mode of the chip usually occurs only in a few parts, such as the substrate voltage generation circuit, the first stage circuit of the control system, and the redundant address setting circuit.

According to this embodiment, the overall power consumption in standby mode is significantly reduced. Therefore, when applied to a PSRAM in which self-refresh operation is performed by battery backup as in this embodiment, the reduction in power consumption in the redundant address setting circuit can be allocated to power for refresh operation, so that relatively low current Sufficient self-refresh operation can be guaranteed by battery backup with low supply capacity.

〔Effect of the invention〕

As is clear from the above explanation, the invention disclosed in this application provides the following effects.

(1,) Since a program link is provided between the output terminal of the CMOS inverter circuit and the MOSFET on one power supply terminal side, which is programmed by electrical conduction or non-conduction, 11 current can be applied regardless of whether the program link is conductive or non-conductive. Therefore, it is possible to achieve low dissipation lψ power.

(2) From the above effects, when the present invention is applied to a PSRAM having a self-refresh operation mode, sufficient self-refresh operation can be guaranteed by battery backup with relatively low current supply capacity.

Although the invention made by the present inventor has been specifically explained above with reference to examples, the present invention is not limited to the above-mentioned examples, and various modifications can be made without departing from the gist thereof.

Although the program link in the above embodiment was provided between the output terminal of the CM○S inverter circuit 2 and the drain of the N-channel MO5FET Q2 constituting the CMOS inverter circuit 2, the program link is not limited to this. It is also possible to provide it between the terminal and the drain of the P-channel type MO8FETQI that constitutes the CMOS inverter circuit 2. In this case, the power switch MO8FET must be of N-channel type and must be provided between it and the ground terminal, and the low level of the control signal φ is set to the operating level of the unit setting circuit.

[Application field]

The above explanation has mainly been about the case where the invention made by the present inventor is applied to the redundant address setting circuit of PSRAM, which is the technical field behind the invention, but it is not limited to this, and is applicable to other devices such as DRAM. It can be widely used in semiconductor memory devices and various semiconductor integrated circuits.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment in which the present invention is applied to a redundant address setting circuit of a PSRAM. 1... Redundant address setting circuit, 2... CMOS inverter circuit, 3... Program link, Q3... Power switch MOS FET, Ec, -Ecn・
= Unit setting circuit. Agent: Patent Attorney Katsuo Ogawa
'+7;r'',--'

Claims (1)

[Claims] 1. Based on a selection instruction signal provided between one terminal of the power source and the output terminal and between the output terminal and the other terminal of the power source and indicating whether or not redundancy selection has been made. and a program link connected in series with the second MOSFET between the output terminal and the other terminal of the power source. Redundant configuration selection circuit. 2. The redundant configuration selection circuit according to claim 1, wherein the signal formed based on the selection instruction signal is a signal obtained by ANDing the selection instruction signal and the chip selection signal. . 3. The first and second MOSFETs are complementary MOSFETs.
3. A redundant configuration selection circuit according to claim 1 or 2, characterized in that the redundant configuration selection circuit comprises an ET.