JP3505387B2 - Static random access memory, test method thereof, and defect repair method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a high resistance load type static random access memory.

[0002]

2. Description of the Related Art In a conventional high resistance load type static random access memory (SRAM), a test is performed at both high temperature and low temperature in order to check whether or not a defect occurs within an operation guarantee temperature range. It was In the case of SRAM,
Testing data retention at high and low temperatures is important. The mechanism of data retention failure at high temperature and low temperature in SRAM will be described below.

FIG. 5 shows a circuit configuration diagram of a memory cell of a high resistance load type SRAM. In the figure, R1 and R2 are high resistance loads, and TR1 and TR2 are N channel MOS transistors for driving memory cells. Also, TR3
And TR4 are memory cell and data line pairs DL1 and DL
2 and 2 based on the signal level of the word line WL.
It is an N-channel MOS transistor for a transfer gate that cuts off. The current IR is supplied to the memory cell from the power supply Vcc. In addition, in the memory cell, M
There is a leak current Ioff when the OS transistor is off and a junction leak current IL.

FIG. 6 shows temperature characteristics of general IR, Ioff, and IL. If Ioff and IL are larger than IR, data cannot be held in the memory cell. Therefore, if the temperature TH that satisfies IR <Ioff is lower than the upper limit TOPH of the operation guarantee temperature range, high temperature data retention becomes defective, and if the temperature TH that satisfies IR <IL is higher than the lower limit TOPL of the operation guarantee temperature range, low temperature data retention is performed. It becomes defective. Therefore, in order to guarantee the data retention function of the SRAM, conventionally, tests on both the high temperature side and the low temperature side have been required.

As a conventional technique, a method of testing a data retention failure due to a junction leak at room temperature is disclosed in Japanese Patent Laid-Open No. 1-22.
It is disclosed in Japanese Patent No. 31342. This is disclosed in JP-A-1-
In the test method of 231342, a well or a source of a transistor in which a source / drain region is connected to each data holding node of a plurality of memory cells forming a memory cell array of each semiconductor memory device on the wafer is used.
A test electrode for connecting the drain-drain substrate to the well of another transistor or the source-drain substrate separately is provided, and the test electrode is provided between the well or the source-drain substrate and the data holding node. By applying a predetermined potential such that the potential difference between the memory cells becomes larger than that during normal operation and increasing the junction leakage current, predetermined data is written to each memory cell, and the data retention state of each memory cell is tested. It is a thing.

[0006]

SUMMARY OF THE INVENTION In the above conventional technique,
Since the test needs to be performed twice, high temperature and low temperature, the number of test steps increases, and an expensive device such as a low temperature prober is also required, resulting in an increase in the cost of the test. Further, in the conventional technique disclosed in JP-A-1-231342, a defect due to a junction leak current (generally a low temperature defect) can be tested at room temperature, but a defect due to an off-state leak current of a MOS transistor does not occur. I can't test. Further, there is also a problem that the yield cannot be improved because the defective data retention cannot be relieved as a good product.

The present invention has been made in view of the above-mentioned conventional problems, and it is possible to test the data retention failure due to the junction leakage current of the SRAM and the leakage current at the time of OFF at room temperature, and it is possible to detect the data retention failure. SRAM that can be remedied as a non-defective product, and further, if the supply current from the power supply is larger than necessary, the current value can be reduced to reduce the power consumption.
Is provided.

[0008]

A static random access memory according to a first aspect of the present invention is a static resistance random access memory of a high resistance load type, wherein a first resistor connected in series to a high resistance load is used. , A first switching element connected in parallel to the first resistor, and during a test
To control the state of the first switching element
External terminal and the above-mentioned first switching element during actual use
A control circuit including a fuse element for controlling the state of the child
It is characterized in that comprising providing a road.

A static random access memory according to a second aspect of the present invention is a high resistance load type static memory.
Direct access to high resistance load in random access memory
A first resistor connected to the column and a parallel connection to the first resistor
A first switching element, connected in parallel to the high-resistance load, a series circuit of a second resistor and a second switching element, during the test, the first and second switching
External terminals to control the status of
To control the states of the first and second switching elements
In order to achieve this, a control circuit including a fuse element is provided .

[0010] Also, a method of testing a static random access memory of the present invention according to claim 3, claim 1 or
The static random access memory testing method according to the second aspect is characterized in that the first switching element is turned off and a test at a low temperature or a high temperature is performed at room temperature.

According to a fourth aspect of the present invention, there is provided a static random access memory defect relieving method according to the present invention.
Alternatively , it is a method for relieving a defect of a static random access memory according to the second aspect , in which the current supplied from the power supply is reduced by turning off the first switching element during actual use to relieve the excessive current defect. It is characterized by performing.

Further, a method of repairing a defect of a static random access memory according to a fifth aspect of the present invention is the method of the second aspect.
A method of relieving a defect of a static random access memory according to the above, wherein the second switching element is turned on during actual use to increase a current supplied from a power source to relieve a data retention defect. It is characterized by.

According to the static random access memory of the present invention, an external terminal is provided, and a predetermined signal is input from the external terminal to connect a resistor (first resistor) in series to a high resistance load, The current supplied from the power supply to the memory cell is reduced, and a memory cell that has a data retention failure at high temperature or low temperature is detected by a test at room temperature. In addition, by a test, by inputting a predetermined voltage from an external terminal to a memory cell that has failed to retain data, a resistor (second resistor) is connected in parallel to the high resistance load and is supplied from the power supply. The current is increased, and a test is performed to see if the current is relieved as a good product. The memory cell determined to be relieved as a non-defective product has a current supplied from the power supply to the memory cell by connecting a resistor (second resistor) in parallel with the high resistance load by cutting the fuse element with a laser or the like. To increase the relief. Similarly, for a memory cell that has an excessive supply current, a fuse (first resistance) is connected in series with a high resistance load by cutting the fuse element with a laser or the like, and the power is supplied from the power supply to the memory cell. The current consumption can be reduced by decreasing the current consumption.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an SRA which is an embodiment of the present invention.
It is a circuit block diagram of the memory cell of M.

In the figure, R3 and R4 are high resistance loads, and TR1 and TR2 are N channel MOS transistors for driving memory cells. Also, TR3 and TR4
Is an N-channel MOS transistor for a transfer gate that connects and disconnects the memory cell and the data line pair DL1 and DL2 based on the signal level of the word line WL. The features of the present invention are that the high resistance loads R3 and R4 are connected in series with resistors R3 'and R4', and the switching elements SW1 and SW2 are connected in parallel with the resistors R3 'and R4', respectively. Is provided. The switching elements SW1 and SW2 are switching elements that are turned on when the control input is at the L level and turned off when the control input is at the H level.
It can be configured by a P-channel MOS transistor. Furthermore, T1 is a switching element SW during the test.
1 and SW2 are external terminals for supplying an H level signal to the control inputs, and CC1 is a fuse element FU1.
And a control circuit including two resistors PU1 and PD1 for giving an H level or L level signal to the control inputs of the switching elements SW1 and SW2 in actual use.

When no signal is input to the external terminal T1, an L level signal is given to the control inputs of the switching elements SW1 and SW2 by the pull-down resistor PD1 and the fuse element FU1 of the control circuit CC1. Therefore, the switching elements SW1 and SW2 are in the ON state. When an H level signal is applied from the external terminal T1, the switching elements SW1 and SW2 are turned off, and the resistors R3 ′ and R3 are connected in series with the high resistance loads R3 and R4.
4'is connected. Therefore, the load resistance value of this memory cell becomes (R3 + R3 ′) and (R4 + R4 ′), and increases, so that the current value supplied from the power supply Vcc decreases. FIG. 6 shows the relationship between the temperature IR and the current IR supplied from the power source, the leak current Ioff when the transistor is off, and the junction leak current IL when no signal is input to the external terminal T1. That is, the low temperature data retention failure occurs at the temperature TL, and the high temperature data retention failure occurs at the temperature TH. Next, when an H level signal is input to the external terminal T1, the switching elements SW1 and SW2 are turned off, and the current supplied from the power supply Vcc becomes IR ′, IR ′, Ioff, and The relationship between IL and temperature is shown in FIG. When the external terminal T1 is at the L level, the memory cells that are not defective unless the temperature is lowered to TL become defective at the temperature TL ′, and the memory cells that are not defective unless the temperature is raised to TH are
It becomes defective at the temperature TH '. Here, TL '> TL, and TH'<TH. In FIG. 2, TH '> T
L '> TR, but room temperature TR becomes TR <T
When the resistance values of the resistors R3 'and R4' are set so that L'or TR> TH ', the data retention failure at low temperature and high temperature can be made defective by the test at room temperature. Figure 2
In the example, since TR <TL ', the low temperature data retention failure can be selected by the test at room temperature.

When a single resistor R3 '(R4') cannot handle both low temperature and high temperature, a resistor for low temperature defect detection and a resistor for high temperature defect detection are provided in parallel and selected. It may be configured to be used.

Further, in the test, for the memory cell in which the supply current from the power supply Vcc is detected to be larger than necessary, the fuse element F of the control circuit CC1 is used.
By cutting U1 with a laser or the like, the resistors PU1 and PD are connected to the control inputs of the switching elements SW1 and SW2.
A signal of H level (Vcc) is applied via 1 to constantly turn off the switching element, thereby increasing the load resistance value, reducing the current supplied from the power source, and reducing the power consumption. Can be planned.

This is the end of the description of the first embodiment of the present invention.

Next, a second embodiment of the present invention will be described.

In the second embodiment, in addition to the structure of the first embodiment, the current supplied from the power supply is further increased to repair the data retention failure.

FIG. 3 shows the SRA of the second embodiment of the present invention.
It is a circuit block diagram of the memory cell of M.

In the figure, R7 and R8 are high resistance loads, and TR1 and TR2 are N-channel MOS transistors for driving memory cells. Also, TR3 and TR4
Is an N-channel MOS transistor for a transfer gate that connects and disconnects the memory cell and the data line pair DL1 and DL2 based on the signal level of the word line WL. Also in this embodiment, similarly to the first embodiment, the resistors R7 ′ and R8 ′ connected in series to the high resistance loads R7 and R8, and the resistors R7 ′ and R8 ′,
Switching elements SW5 and SW6 connected in parallel are provided respectively. The switching elements SW5 and SW6 are switching elements that are turned on when the control input is at the L level and turned off when the control input is at the H level, and can be configured by, for example, P-channel MOS transistors. Furthermore, T3 is
CC3 is an external terminal for applying an H level signal to the control inputs of the switching elements SW5 and SW6, and CC3 is
The control circuit includes a fuse element FU3 and two resistors PU3 and PD3, and supplies an H-level or L-level signal to the control inputs of the switching elements SW5 and SW6 in actual use.

The feature of this embodiment is that the high resistance load R
7, a series circuit of a resistor R7 ″ and a switching element SW7 connected in parallel, and a series circuit of a resistor R8 ″ and a switching element SW8 connected in parallel to a high resistance load R8 are provided. In point. Switching element S
W7 and SW8 are switching elements that are turned on when their control inputs are at L level and turned off when their control inputs are at H level, and can be composed of, for example, P-channel MOS transistors. Further, T4 is an external terminal for giving an L level signal to the control inputs of the switching elements SW7 and SW8 during the test, and C4
C4 includes a fuse element FU4 and two resistors PU4 and PD4.
It is a control circuit for giving a signal of H level or L level to the control inputs of W7 and SW8.

When no signal is input to the external terminal T4, an H level signal is given to the control inputs of the switching elements SW7 and SW8 by the pull-up resistor PU4 and the fuse element FU4 of the control circuit CC4. Therefore, the switching elements SW7 and SW8 are in the off state. When an L level signal is applied from the external terminal T4, the switching elements SW7 and SW8 are turned on, and the resistors R7 ″ and R8 are connected in parallel with the high resistance loads R7 and R8.
8 ″ is connected. Therefore, the load resistance value of this memory cell is (R7 · R7 ″) / (R7 + R7 ″)
And (R8 · R8 ″) / (R8 + R8 ″) (assuming that the switching elements SW5 and SW6 are in the ON state) and decrease, the current value supplied from the power supply Vcc increases. FIG. 6 shows the relationship between the temperature IR and the current IR supplied from the power source, the leak current Ioff when the transistor is off, and the junction leak current IL when no signal is input to the external terminal T4. That is, the low temperature data retention failure occurs at the temperature TL, and the high temperature data retention failure occurs at the temperature TH. Next, an L level signal is input to the external terminal T4, and the switching elements SW7 and SW8 are input.
Is turned on, and the current supplied from the power source Vcc is I
FIG. 4 shows the relationship between IR ″, Ioff, and IL and the temperature in the case of R ″. When the external terminal T4 is at the L level, the memory cell that is defective at the temperature of TL becomes defective at the temperature TL ″ (<TL).
A memory cell that has been defective at a temperature of H has a temperature of T
H ″ (> TH) results in a defect. If the lower limit temperature of the guaranteed operating temperature range is TOPL and the upper limit temperature is TOPH, T
L ″ <TOPL, TH ″> TOPH,
By setting the resistance values of resistors R7 '' and R8 '',
It is possible to make a memory cell, which has a poor retention of low-temperature and high-temperature data, a good product.

By applying an H level signal to the external terminal T3,
As a result of the test conducted at room temperature, the memory cell determined to have a low temperature or high temperature data retention defect is further subjected to the external terminal T
3 is supplied with an H level signal and the external terminal T4 is supplied with an L level signal to perform a test.
By disconnecting the fuse element FU4 of No. 4 with a laser or the like, an L level (GND) signal is applied to the control inputs of the switching elements SW7 and SW8 via the resistors PU4 and PD4 to always turn on the switching element. As a result, the load resistance value is reduced and the supply current from the power supply Vcc is increased. As a result, the memory cell having the defective data retention is relieved as a good product.

If the external terminal and the control circuit are provided for each bit line or word line, the number of fuses to be cut is reduced and the success rate of repair is improved.

[0029]

As described above in detail, according to the present invention, it is possible to test the data retention failure due to the junction leak current of the SRAM and the leak current at the time of OFF at room temperature, so that the number of test steps is reduced. Moreover, since an expensive device such as a low temperature prober is not required, the cost for the test can be reduced. In addition, it is possible to remedy a defective data retention as a good product, and to reduce the power consumption of the one in which the current supplied from the power supply is larger than necessary to reduce the power consumption. Therefore, the yield can be improved,
It is possible to achieve cost reduction.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a memory cell in an SRAM according to a first embodiment of the present invention, which has a configuration in which a resistor is connected in series to a high resistance load.

FIG. 2 shows a supply current IR ′ from a power supply of a memory cell, a junction leakage current IL, and a transistor off-leakage current Ioff when a resistance is connected in series to a high resistance load.
It is a figure which shows the relationship between and.

FIG. 3 is a circuit configuration diagram of a memory cell in the SRAM of the second embodiment of the present invention, which has a configuration in which resistors are connected in series and in parallel to a high resistance load.

FIG. 4 shows a supply current IR ″ from a power supply of a memory cell, a junction leakage current IL, and a transistor off-leakage current Ioff when a resistance is connected in parallel to a high resistance load.
It is a figure which shows the relationship between and.

FIG. 5 is a circuit configuration diagram of a memory cell in a conventional high resistance load type SRAM.

FIG. 6 is a diagram showing a conventional high resistance load type SRAM in which a supply current IR from a power source of a memory cell, a junction leakage current IL,
FIG. 9 is a diagram showing a relationship between a leakage current Ioff when the transistor is off and a temperature.

[Explanation of symbols]

R3, R4, R7, R8
High resistance load R3 ', R4', R7 ', R8', R7 ", R8"
Resistors SW1, SW2, SW5, SW6, SW7, SW8
Switching elements T1, T3, T4
External terminals CC1, CC3, CC4
Control circuits FU1, FU3, FU4
Fuse element

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G11C 11/41-11/412 G11C 29/00

Claims (5)

(57) [Claims] 1. A high resistance load type static random access memory, comprising: a first resistance connected in series to a high resistance load; and a first switching element connected in parallel to the first resistance . During the test, control the state of the first switching element
External terminal for controlling and the state of the first switching element at the time of actual use
And a control circuit including a fuse element for performing the static random access memory. 2. A high resistance load type static random arm.
In a access memory, a first resistance connected in series to a high resistance load and a first switching element connected in parallel to the first resistance
And a series circuit of a second resistance and a second switching element connected in parallel to a high resistance load, and states of the first and second switching elements at the time of a test.
External terminal for controlling the state of the first and second switching elements in actual use.
And a control circuit including a fuse element for controlling the state of the static random access memory. 3. A method of testing a static random access memory according to claim 1 or 2, as an off-state the first switching element, the test at a low temperature or high temperature, and configured to perform at room temperature A method for testing a static random access memory, which is characterized in that 4. A defect repairing method of static random access memory according to claim 1 or 2, in actual use, by the OFF state of the first switching element, reducing the supply current from the power supply A method of repairing a defect in a static random access memory, which is characterized in that an excessive current defect is repaired. 5. The method of repairing a defect of a static random access memory according to claim 2 , wherein the second switching element is turned on during actual use to increase the current supplied from the power supply. A method of relieving a defect in a static random access memory, which is characterized in that a data retention defect is relieved.