JPH11331135A - Demodulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To speedily and highly accurately demodulate a received signal. SOLUTION: This demodulator is constituted so as to detect (13) a code change point from a sampling signal by sampling (10 and 11) the received signal with the high-speed clock signal of a cycle higher than its bit rate, to recognize (14) the bit rate of the received signal based on this code change point and to extract (15 and 16) the received signal, based on this bit rate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulator used for demodulating a signal received by a mobile terminal or a base station.

[0002]

2. Description of the Related Art Conventionally, a demodulator of this kind has been used to improve the I
A method of demodulating a received signal by sampling a signal and a Q signal based on a clock signal of a bit (symbol) rate of the received signal is adopted.

FIG. 4 shows such a conventional demodulator. In the first and second sampling circuits 1 and 2, the I signal and the Q signal of the received signal are respectively applied to one input terminal thereof. Is entered. The first and second sampling circuits 1, 2
The output terminal of the timing adjustment unit 3 is connected to the other input terminal, and the comparator 4 is connected to each output terminal.

An oscillator 5 is connected to the comparator 4, and a clock signal corresponding to a bit (symbol) rate of a received signal is input from the oscillator 5. Thereby, the comparator 4
When the sampling signals of the I signal and the Q signal are input from the first and second sampling circuits 1 and 2, the sampling signals are respectively compared with the clock signal to detect each phase error.

[0005] A loop filter 6 is connected to the output terminal of the comparator 4 and outputs detected phase error information to the loop filter 6. The timing adjustment unit 3 is connected to the loop filter 6, calculates a timing control value based on the input phase error information, and outputs it to the timing adjustment unit 3.

The timing adjuster 3 adjusts the period of the clock signal based on the input timing control value and outputs the adjusted clock signal to the first and second sampling circuits 1 and 2, respectively. As a result, the first and second sampling circuits 1 and 2 sample and demodulate the input I and Q signals based on the clock signal from the timing adjustment unit 3.

However, the demodulator does not stabilize unless a considerable reception signal is input until the output of the loop filter 6 converges and stabilizes, so that it takes a long time to realize highly accurate demodulation. Has the problem of spending.

According to this, particularly when applied to a communication system in which the bit rate of a received signal is changed and transmitted, a considerable amount of time is required for the tuning time, which may adversely affect the communication system. .

[0009]

As described above, the conventional demodulator has a problem that the tuning time is long and a relatively long time is required to realize high-precision demodulation. The present invention has been made in view of the above circumstances, and has as its object to provide a demodulator having a simple configuration and capable of realizing high-accuracy demodulation of a received signal quickly.

[0010]

SUMMARY OF THE INVENTION The present invention is based on a clock oscillating means for oscillating a high-speed clock signal having a cycle faster than the bit rate of a received signal, and a high-speed clock signal oscillated by the clock oscillating means. Sampling means for sampling the received signal; sign change point detecting means for detecting a sign change point of the sampling signal sampled by the sampling means based on a high-speed clock oscillated from the clock oscillating means; Bit rate recognition means for recognizing the bit rate of the received signal based on the sign change point detected by the means; and a sampling signal sampled by the sampling means based on the bit rate of the received signal recognized by the bit rate recognition means. A reception signal extracting means for extracting a reception signal. It was constructed the vessel.

According to the above configuration, the received signal is sampled by the high-speed clock signal having a cycle faster than the bit rate, a sign change point is detected from the sampled signal, and the bit rate of the received signal is determined based on the sign change point. Recognizing and extracting the received signal based on this bit rate. Therefore, the bit rate and the phase can be quickly detected without the need for the tuning time, and the quick demodulation operation can be realized.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a demodulator according to an embodiment of the present invention. One of input terminals of first and second sampling circuits 10 and 11 receives an I signal and a Q signal of a received signal. You. The output terminal of the oscillator 12 is connected to the other input terminals of the first and second sampling circuits 10 and 11.

An output terminal of the oscillator 12 is connected to one input terminal of the sign change point detecting unit 13. The oscillator 12 generates a high-speed clock signal having a cycle faster than the cycle of the bit (symbol) rate of the received signal, for example, a cycle twice as long (see FIG. 2), and the first and second sampling circuits 10 and 11 described above. , To the sign change point detection unit 13.

The sign change point detecting section 13 has the other input terminal connected to the first and second sampling circuits 10 and 10.
11 are connected to an output terminal, and a bit rate recognition unit 14 is connected to the output terminal. The sign change point detection unit 13 performs the first and the second based on the high-speed clock signal from the oscillator 12.
Of the sampling signals from the sampling circuits 10 and 11 are detected and output to the beat rate recognition unit.

An output terminal of the bit rate recognition unit 14 is connected to one input terminal of each of the first and second reception signal extraction units 15 and 16, and extracts the reception signal based on the input code change point information. Recognizing bit rate changes by finding points,
A bit rate clock corresponding to the bit rate change is generated and output to the first and second received signal extraction units 15 and 16.

First and second received signal extracting sections 15 and 16
The other input terminal is connected to the output terminals of the first and second sampling circuits 10 and 11, and extracts a reception signal from the sampling signal based on the input bit rate clock.

In the above configuration, the first and second sampling circuits 10 and 11 receive a received signal, an I signal and a Q signal as shown in FIG. At the same time, the high-speed clock signal from the oscillator 12 shown in FIG. 2B is input to the first and second sampling circuits 10 and 11, and the I signal and the Q signal are sampled based on the high-speed clock signal. Then, the sampling signal is converted to a sign change point detecting unit 13 and first and second received signal extracting units 15 and 16.
Respectively.

Here, the sign change point detector 13 detects a sign change point (see FIG. 2C) of the sampling signal based on the high-speed clock signal from the oscillator 12, and converts the sign change point signal into a bit. Output to the rate recognition unit 14. The bit rate recognizing unit 14 determines, for example, an intermediate point between the code change points as a reception signal extraction point based on the code change point signal input as shown in FIG. Recognizing the bit rate change, generating a bit rate clock corresponding to the bit rate change, and
And the second received signal extracting sections 15 and 16.

Here, the first and second received signal extraction units 15 and 16 extract and demodulate the I signal and the Q signal from the sampling signal based on the input bit rate clock.

As described above, the demodulator converts the received signal into
Sampling is performed with a high-speed clock signal having a cycle faster than the bit rate, a sign change point is detected from the sampled signal, the bit rate of the received signal is recognized based on the sign change point, and reception is performed based on the bit rate. It was configured to extract signals.

According to this, the bit rate and the phase of the received signal can be quickly detected with almost no tuning time required, so that a stable demodulation operation can be quickly realized.

In the above embodiment, a case has been described in which the cycle of the high-speed clock signal oscillated by the oscillator 12 is set to be twice the cycle of the bit rate of the received signal. However, the present invention is not limited to this. Instead, the period may be set to be at least twice the period of the bit rate of the received signal. According to this, the sign change point detection can be performed with higher accuracy, and more effective effects are expected. Therefore, it is needless to say that the present invention is not limited to the above-described embodiment, but can be variously modified without departing from the gist of the present invention.

[0023]

As described in detail above, according to the present invention, it is possible to provide a demodulator having a simple configuration and capable of realizing a highly accurate demodulation of a received signal quickly. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a demodulator according to one embodiment of the present invention.

FIG. 2 is a waveform diagram shown for explaining the operation of FIG. 1;

FIG. 3 is a diagram illustrating a relationship between a bit rate of a received signal, a code change point, and a received signal extraction point.

FIG. 4 is a block diagram showing a configuration of a conventional demodulator.

[Explanation of symbols]

 10 1st sampling circuit. 11 Second sampling circuit. 12 ... oscillator. 13 ... sign change point detection unit. 14: Bit rate recognition unit. 15 1st received signal extraction part. 16 second reception signal extraction unit

Claims (2)

[Claims] 1. A clock oscillating means for oscillating a high-speed clock signal having a cycle faster than a bit rate of a received signal, and a sampling means for sampling the received signal based on the high-speed clock signal oscillated by the clock oscillating means. A sign change point detecting means for detecting a sign change point of the sampling signal sampled by the sampling means based on a high-speed clock oscillated from the clock oscillating means; and a sign change point detected by the sign change point detecting means. Bit rate recognizing means for recognizing the bit rate of the received signal based on the received signal, and receiving signal extracting for extracting the received signal from the sampling signal sampled by the sampling means based on the bit rate of the received signal recognized by the bit rate recognizing means. And a demodulator comprising: 2. The demodulator according to claim 1, wherein said clock generating means oscillates a high-speed clock having a cycle twice or more a cycle of a bit rate of said received signal.