JPH11331005A - Waveform shaping circuit - Google Patents

Waveform shaping circuit

Info

Publication number
JPH11331005A
JPH11331005A JP10134091A JP13409198A JPH11331005A JP H11331005 A JPH11331005 A JP H11331005A JP 10134091 A JP10134091 A JP 10134091A JP 13409198 A JP13409198 A JP 13409198A JP H11331005 A JPH11331005 A JP H11331005A
Authority
JP
Japan
Prior art keywords
rssi signal
output terminal
circuit
potential
input terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10134091A
Other languages
Japanese (ja)
Inventor
Akira Yoshimoto
昭 吉元
Koji Ono
浩二 大野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japan Radio Co Ltd
Original Assignee
Japan Radio Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Japan Radio Co Ltd filed Critical Japan Radio Co Ltd
Priority to JP10134091A priority Critical patent/JPH11331005A/en
Publication of JPH11331005A publication Critical patent/JPH11331005A/en
Pending legal-status Critical Current

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  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Circuits Of Receivers In General (AREA)

Abstract

PROBLEM TO BE SOLVED: To avoid delays in rising and falling. SOLUTION: A current flows to a diode D by a potential difference produced between an input and an output of a time constant circuit 20 in the case of rising, a capacitor C is charged and an electric potential at an output terminal OUT rapidly rises. In the case of falling, an output of an amplifier AMP rises by the potential difference produced between the input and the output of the time constant circuit 20, a transistor TR is turned on to rapidly decrease the potential at the output terminal OUT.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、バースト信号を受
信する装置例えばPHS(Personal Handy-phoneSystem)
子局においてキャリアセンス回路の一部として使用され
る回路、特にRSSI(Receiving Signal Strength Ind
icator)信号を波形整形する回路に関する。
The present invention relates to a device for receiving a burst signal, for example, a PHS (Personal Handy-phone System).
Circuits used as part of the carrier sense circuit in slave stations, especially RSSI (Receiving Signal Strength Ind
icator) relates to a circuit for shaping a signal.

【0002】[0002]

【従来の技術及びその問題点】PHSにおいては625
μsの時間長を有するバースト信号にて通信が行われて
おり、PHS子局はこのバースト信号の到来を素早くか
つ正確に検出してこれに応答する必要がある。図2に示
すように、抵抗R及びコンデンサCから構成される時定
数回路20を受信機10の後段に設け、RSSI信号入
力端INを介し受信機10から時定数回路20にRSS
I信号を入力し、入力したRSSI信号を時定数回路2
0により積分し、RSSI信号出力端OUTから後段に
供給するようにすれば、QPSK変調や雑音等の影響で
RSSI信号に現れていた振幅変動を抑えることがで
き、後段の回路にて正確にバースト信号の到来を安定に
検出できる。
2. Description of the Related Art In the PHS, 625 is used.
Communication is performed using a burst signal having a time length of μs, and the PHS slave station needs to quickly and accurately detect the arrival of the burst signal and respond to it. As shown in FIG. 2, a time constant circuit 20 including a resistor R and a capacitor C is provided at a subsequent stage of the receiver 10, and the RSSI signal is input from the receiver 10 to the time constant circuit 20 via the RSSI signal input terminal IN.
I signal is input, and the input RSSI signal is converted to a time constant circuit 2
If the signal is integrated by 0 and supplied to the subsequent stage from the RSSI signal output terminal OUT, amplitude fluctuations appearing in the RSSI signal due to the influence of QPSK modulation, noise, and the like can be suppressed. Signal arrival can be detected stably.

【0003】図2に示した従来回路には、RSSI信号
入力端INにおいて現れていた例えば約±7dBの振幅
変動を約±1dBまで低減できる、という利点がある反
面、時定数回路20を用いているため、RSSI信号の
立上り時及び立下り時に遅れが発生する、という問題が
ある。この遅れは、図3(a)及び(b)に示すように
約100μs程になる。
The conventional circuit shown in FIG. 2 has an advantage that the amplitude fluctuation of, for example, about ± 7 dB that appears at the RSSI signal input terminal IN can be reduced to about ± 1 dB, but the time constant circuit 20 is used. Therefore, there is a problem that a delay occurs when the RSSI signal rises and falls. This delay is about 100 μs as shown in FIGS. 3A and 3B.

【0004】[0004]

【発明の概要】本発明の目的は、従来回路における平滑
作用は引き続き維持しつつ、従来回路の問題点であった
立上り時及び立下り時の遅れを解消し、従来に比べ正確
にバースト信号の到来を検出してこれに素早く応答でき
るようにすることにある。
SUMMARY OF THE INVENTION It is an object of the present invention to eliminate the problem of the conventional circuit at the time of rising and falling while maintaining the smoothing function of the conventional circuit, and to more accurately output the burst signal as compared with the conventional circuit. The aim is to detect the arrival and respond quickly to it.

【0005】このような目的を達成すべく、本発明にお
いては、バースト信号の受信レベルを示すRSSI信号
をそのRSSI信号入力端から入力して波形整形し、波
形整形後のRSSI信号を出力する波形整形回路に、
(1)RSSI信号入力端とRSSI信号出力端との間
に接続され、所定の時定数を以てRSSI信号を積分す
る時定数回路と、(2)RSSI信号入力端の電位がR
SSI信号出力端の電位より所定値以上高いことを検出
し、これに応じ、時定数回路をバイパスしてRSSI信
号入力端をRSSI信号出力端に接続するバイパス回路
と、(3)RSSI信号出力端の電位がRSSI信号入
力端の電位より所定値以上高いことを検出し、これに応
じ、RSSI信号出力端の電位を強制的に低下させる出
力低下回路と、を設けることとした。
In order to achieve the above object, according to the present invention, an RSSI signal indicating a reception level of a burst signal is input from an RSSI signal input terminal thereof, the waveform is shaped, and an RSSI signal after the waveform shaping is output. In the shaping circuit,
(1) a time constant circuit that is connected between the RSSI signal input terminal and the RSSI signal output terminal and integrates the RSSI signal with a predetermined time constant; and (2) the potential of the RSSI signal input terminal is R
A bypass circuit for detecting that the potential is higher than the potential of the SSI signal output terminal by a predetermined value or more, and bypassing the time constant circuit to connect the RSSI signal input terminal to the RSSI signal output terminal; Is detected to be higher than the potential of the RSSI signal input terminal by a predetermined value or more, and an output reduction circuit for forcibly reducing the potential of the RSSI signal output terminal is provided.

【0006】このように、立上り時にはバイパス回路に
よりRSSI信号出力端の電位を強制的に立ち上げ、立
下り時には出力低下回路によりRSSI信号出力端の電
位を強制的に立ち下げるようにしたため、本発明によれ
ば、従来の回路に比べて立ち上がり時及び立下り時にお
ける遅れが少ない波形整形回路を得ることができる。更
に、立上りから立下りまでの間は時定数回路により積分
による平滑を行っているため、従来回路と同程度以上の
平滑度を実現できる。更に、RSSI信号入力端及び出
力端の電位即ち時定数回路前後の電位を検出しているた
め、特開平9−261188号に記載の回路と異なり、
バーストタイミングの検出乃至推定を行う必要がなく、
回路構成が簡素になる。
As described above, the potential of the RSSI signal output terminal is forcibly raised by the bypass circuit at the time of rising, and the potential of the RSSI signal output terminal is forcibly lowered by the output reduction circuit at the time of falling. According to this, a waveform shaping circuit having less delay at rising and falling times as compared with the conventional circuit can be obtained. Furthermore, since the smoothing by integration is performed by the time constant circuit from the rising to the falling, a smoothness equal to or higher than that of the conventional circuit can be realized. Further, since the potential of the RSSI signal input terminal and the output terminal, that is, the potential before and after the time constant circuit is detected, unlike the circuit described in JP-A-9-261188,
There is no need to detect or estimate the burst timing,
The circuit configuration is simplified.

【0007】更に、バイパス回路及び出力低下回路に係
る機能はダイオードやトランジスタにより実現できるた
め、回路構成はこの面でも簡素になる。即ち、そのアノ
ードがRSSI信号入力端に接続され、かつそのカソー
ドがRSSI信号出力端に接続されたダイオードによっ
て、バイパス回路を実現できる。また、RSSI信号出
力端及び接地にコレクタ及びエミッタが接続されている
トランジスタのベースに、RSSI信号入力端に対する
RSSI信号出力端の電位差を検出し増幅する増幅器の
出力端を接続することによって、出力低下回路を実現で
きる。更に、立上りのスピードアップに際しダイオード
の電流にて時定数回路中のコンデンサを充電しているた
め、特開平9−261188号に記載の回路と異なり、
チャージ回路を別途設ける必要がない。
Furthermore, since the functions relating to the bypass circuit and the output reduction circuit can be realized by diodes and transistors, the circuit configuration is simplified in this respect as well. That is, a bypass circuit can be realized by a diode whose anode is connected to the RSSI signal input terminal and whose cathode is connected to the RSSI signal output terminal. Further, by connecting the output terminal of an amplifier that detects and amplifies the potential difference between the RSSI signal output terminal and the RSSI signal output terminal to the base of the transistor whose collector and emitter are connected to the RSSI signal output terminal and the ground, the output is reduced. A circuit can be realized. Further, since the capacitor in the time constant circuit is charged by the current of the diode at the time of rising speed, unlike the circuit described in JP-A-9-261188,
There is no need to provide a separate charge circuit.

【0008】[0008]

【発明の実施の形態】以下、本発明の好適な実施形態に
関し図面に基づき説明する。なお、以下の説明ではPH
Sのキャリアセンス回路を例とするが、本発明は、バー
スト信号の立上り及び立下りのタイミングや受信レベル
を正確に検出することが必要な様々な用途に適用でき
る。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. In the following description, PH
Although an S carrier sense circuit is taken as an example, the present invention can be applied to various applications that require accurate detection of the rising and falling timings and reception levels of burst signals.

【0009】図1に、本発明の一実施形態に係る回路の
構成を示す。この実施形態においては、RSSI信号入
力端INからRSSI信号出力端OUTに向けて即ち順
方向に、ダイオードDが接続されている。更に、RSS
I信号入力端IN即ち時定数回路20の入力側には抵抗
Ri1が、RSSI信号出力端OUT即ち時定数回路2
0の出力側には抵抗Ri2が、それぞれ接続されてい
る。抵抗Ri1は増幅器AMPの非反転入力端の入力抵
抗であり、抵抗Ri2は増幅器AMPの反転入力端の入
力抵抗である。この増幅器AMPの出力端はトランジス
タTrのベースに接続されている。トランジスタTrの
コレクタは抵抗Roを介してRSSI信号出力端OUT
に接続されており、またエミッタは接地されている。な
お、抵抗Rfは増幅器AMPの出力端から反転入力端へ
の帰還抵抗である。
FIG. 1 shows a circuit configuration according to an embodiment of the present invention. In this embodiment, a diode D is connected from the RSSI signal input terminal IN to the RSSI signal output terminal OUT, that is, in the forward direction. In addition, RSS
The resistor Ri1 is connected to the I signal input terminal IN, that is, the input side of the time constant circuit 20, and the RSSI signal output terminal OUT, that is, the time constant circuit 2
A resistor Ri2 is connected to the output side of 0. The resistance Ri1 is the input resistance of the non-inverting input terminal of the amplifier AMP, and the resistance Ri2 is the input resistance of the inverting input terminal of the amplifier AMP. The output terminal of the amplifier AMP is connected to the base of the transistor Tr. The collector of the transistor Tr is connected to the RSSI signal output terminal OUT via a resistor Ro.
And the emitter is grounded. Note that the resistor Rf is a feedback resistor from the output terminal of the amplifier AMP to the inverting input terminal.

【0010】この実施形態においては、バースト信号の
立上りに伴いRSSI信号入力端INの電位が急峻に上
昇すると、ダイオードDに電流が流れる。即ち、時定数
回路20には応答の遅れがあるため、RSSI信号入力
端INの電位が急峻に上昇してもRSSI信号出力端O
UTの電位は直ちには上昇せず、従って過渡的に時定数
回路20の前後に電位差が生じる。この電位差によって
ダイオードDに電流が流れると、コンデンサCがこの電
流により充電されるため、RSSI信号出力端OUTの
電位が上がる。このように、時定数回路20をバイパス
するダイオードDの順方向電流によりコンデンサCを充
電することにより、バースト信号の立上りの際にRSS
I信号出力端OUTの電位を素早く立ち上げることがで
きる。
In this embodiment, when the potential of the RSSI signal input terminal IN rises sharply with the rise of the burst signal, a current flows through the diode D. That is, since the time constant circuit 20 has a response delay, even if the potential of the RSSI signal input terminal IN rises sharply, the RSSI signal output terminal O
The potential of the UT does not immediately rise, and thus a potential difference transiently occurs before and after the time constant circuit 20. When a current flows through the diode D due to this potential difference, the capacitor C is charged by the current, and the potential of the RSSI signal output terminal OUT rises. As described above, the capacitor C is charged by the forward current of the diode D bypassing the time constant circuit 20, so that the rising edge of the burst signal causes the RSSR to rise.
The potential of the I signal output terminal OUT can quickly rise.

【0011】また、バースト信号の立下りに伴いRSS
I信号入力端INの電位が急峻に低下すると、増幅器A
MPの反転入力端の電位が急峻に下がる結果、増幅器A
MPの出力端の電位が上昇する。即ち、時定数回路20
には応答の遅れがあるため、RSSI信号入力端INの
電位が急峻に低下してもRSSI信号出力端OUTの電
位は直ちには低下せず、従って過渡的に時定数回路20
の前後に電位差が生じる。増幅器AMPはこの電位差を
検出及び増幅する手段であり、増幅器AMPの出力端の
電位がトランジスタTrのオン電圧以上になるとトラン
ジスタTrがオンしてRSSI信号出力端OUTが接地
される。このように、トランジスタTrのオン電圧相当
値以上の電位差を検出したときRSSI信号出力端OU
Tの電位を強制的に低下させるようにしているため、バ
ースト信号の立下りの際にRSSI信号出力端OUTの
電位を素早く立ち下げることができる。
[0011] Further, when the burst signal falls, RSS
When the potential of the I signal input terminal IN sharply drops, the amplifier A
As a result, the potential at the inverting input terminal of MP drops sharply,
The potential at the output terminal of MP rises. That is, the time constant circuit 20
Has a response delay, the potential of the RSSI signal output terminal OUT does not immediately decrease even if the potential of the RSSI signal input terminal IN drops sharply.
Before and after the potential difference. The amplifier AMP is means for detecting and amplifying this potential difference. When the potential at the output terminal of the amplifier AMP becomes equal to or higher than the ON voltage of the transistor Tr, the transistor Tr is turned on and the RSSI signal output terminal OUT is grounded. As described above, when the potential difference equal to or more than the value corresponding to the ON voltage of the transistor Tr is detected, the RSSI signal output terminal OU
Since the potential of T is forcibly reduced, the potential of the RSSI signal output terminal OUT can quickly fall when the burst signal falls.

【0012】図3(c)に、この実施形態にて得られる
整形後波形を示す。この実施形態における立上り時及び
立下り時の遅れは約20μsにとどまり、受信機10の
出力である図3(a)の波形における約10μsに比べ
れば大きいものの、図2に示す従来回路の出力である図
3(b)の波形における約100μsに比べれば小さく
なる。更に、時定数回路20による積分・平滑効果があ
るため、RSSI入力端INにおける変動がトランジス
タTrのオン電圧相当値以下である限り、振幅は従来回
路と同程度になる。
FIG. 3C shows a waveform after shaping obtained in this embodiment. The delay at the time of rising and falling in this embodiment is only about 20 μs, which is larger than the output of the receiver 10 of about 10 μs in the waveform of FIG. This is smaller than about 100 μs in the waveform of FIG. 3B. Furthermore, since the time constant circuit 20 has an integrating / smoothing effect, the amplitude is almost the same as that of the conventional circuit as long as the fluctuation at the RSSI input terminal IN is equal to or less than the ON voltage of the transistor Tr.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本発明の一実施形態に係る波形整形回路の構
成を示す回路図である。
FIG. 1 is a circuit diagram showing a configuration of a waveform shaping circuit according to an embodiment of the present invention.

【図2】 一従来技術に係る波形整形回路の構成を示す
回路図である。
FIG. 2 is a circuit diagram showing a configuration of a waveform shaping circuit according to one related art.

【図3】 RSSI信号の波形を示す図であり、特に
(a)は波形整形回路への入力を、(b)は従来回路の
出力を、(c)は実施形態回路の出力を、それぞれ示す
図である。
3A and 3B are diagrams showing a waveform of an RSSI signal, in particular, FIG. 3A shows an input to a waveform shaping circuit, FIG. 3B shows an output of a conventional circuit, and FIG. FIG.

【符号の説明】[Explanation of symbols]

10 受信機、20 時定数回路、D ダイオード、A
MP 増幅器、Trトランジスタ。
10 receiver, 20 time constant circuit, D diode, A
MP amplifier, Tr transistor.

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 バースト信号の受信レベルを示すRSS
I信号をそのRSSI信号入力端から入力して波形整形
し、波形整形後のRSSI信号を出力する波形整形回路
において、 上記RSSI信号入力端と上記RSSI信号出力端との
間に接続され、所定の時定数を以て上記RSSI信号を
積分する時定数回路と、 上記RSSI信号入力端の電位が上記RSSI信号出力
端の電位より所定値以上高いことを検出し、これに応
じ、上記時定数回路をバイパスして上記RSSI信号入
力端を上記RSSI信号出力端に接続するバイパス回路
と、 上記RSSI信号出力端の電位が上記RSSI信号入力
端の電位より所定値以上高いことを検出し、これに応
じ、上記RSSI信号出力端の電位を強制的に低下させ
る出力低下回路と、 を備えることを特徴とする波形整形回路。
1. An RSS indicating a reception level of a burst signal.
A waveform shaping circuit for inputting the I signal from the RSSI signal input terminal and shaping the waveform and outputting the RSSI signal after the waveform shaping, wherein the predetermined signal is connected between the RSSI signal input terminal and the RSSI signal output terminal, A time constant circuit that integrates the RSSI signal with a time constant, and detects that the potential of the RSSI signal input terminal is higher than a potential of the RSSI signal output terminal by a predetermined value or more, and accordingly, bypasses the time constant circuit. A bypass circuit connecting the RSSI signal input terminal to the RSSI signal output terminal, and detecting that the potential of the RSSI signal output terminal is higher than the potential of the RSSI signal input terminal by a predetermined value or more. A waveform shaping circuit comprising: an output lowering circuit for forcibly lowering a potential of a signal output terminal.
【請求項2】 請求項1記載の波形整形回路において、 上記バイパス回路が、そのアノードが上記RSSI信号
入力端にまたそのカソードが上記RSSI信号出力端に
それぞれ接続されたダイオードであることを特徴とする
波形整形回路。
2. The waveform shaping circuit according to claim 1, wherein said bypass circuit is a diode whose anode is connected to said RSSI signal input terminal and whose cathode is connected to said RSSI signal output terminal, respectively. Waveform shaping circuit.
【請求項3】 請求項1又は2記載の波形整形回路にお
いて、 上記出力低下回路が、上記RSSI信号入力端に対する
上記RSSI信号出力端の電位差を検出し増幅する増幅
器と、そのコレクタ及びエミッタが上記RSSI信号出
力端及び接地にまたそのベースが上記増幅器の出力端に
それぞれ接続されたトランジスタと、を有することを特
徴とする波形整形回路。
3. The waveform shaping circuit according to claim 1, wherein the output reduction circuit detects and amplifies a potential difference between the RSSI signal input terminal and the RSSI signal output terminal, and the collector and the emitter include the amplifier. A transistor having an RSSI signal output terminal, a transistor connected to ground, and a base connected to the output terminal of the amplifier, respectively.
JP10134091A 1998-05-15 1998-05-15 Waveform shaping circuit Pending JPH11331005A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10134091A JPH11331005A (en) 1998-05-15 1998-05-15 Waveform shaping circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10134091A JPH11331005A (en) 1998-05-15 1998-05-15 Waveform shaping circuit

Publications (1)

Publication Number Publication Date
JPH11331005A true JPH11331005A (en) 1999-11-30

Family

ID=15120226

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10134091A Pending JPH11331005A (en) 1998-05-15 1998-05-15 Waveform shaping circuit

Country Status (1)

Country Link
JP (1) JPH11331005A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8155618B2 (en) 2007-07-20 2012-04-10 Denso Corporation Receiving device for frequency modulated signals with voltage-limited reference input to demodulated signal binarization comparator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8155618B2 (en) 2007-07-20 2012-04-10 Denso Corporation Receiving device for frequency modulated signals with voltage-limited reference input to demodulated signal binarization comparator

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