JPH11330960A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the PLL circuit which can autonomously switch voltage- controlled oscillators and frequency division ratios of oscillation clocks corresponding to the frequency of a reference clock. SOLUTION: The PLL circuit 10 which is mounted with two voltage- controlled oscillators 26-1 and 26-2 having different oscillation frequency bands and properly switch them corresponding to the frequency of the reference clock RCK is provided with a potential difference detecting circuit 31 which monitors the output voltage of a sense amplifier 25 and also provided with a counter circuit 32 which counts the output signal Y of the potential difference detecting circuit 31, and the count output of this count circuit 31 is used as a switching signal SEL for a selector 27 to autonomously switch the voltage-controlled oscillators 26-1 to 26-2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a PLL (phase loc).
More particularly, the present invention relates to a PLL circuit capable of widening a frequency band that can be locked to a reference clock or locking to a plurality of different frequency bands.

[0002]

2. Description of the Related Art A PLL circuit is a feedback closed circuit including a frequency / phase comparator 101, a loop filter 102, a voltage controlled oscillator (VCO) 103, etc., as shown in FIG. Reference clock)
The frequency and phase of the oscillation clock of the voltage controlled oscillator 103 and the frequency and phase of the
And the comparison result is supplied to the voltage controlled oscillator 103 via the loop filter 102, whereby the frequency and phase of the oscillation clock of the voltage controlled oscillator 103 are controlled.

The frequency at which this PLL circuit can be locked is
It is within the frequency band in which the voltage controlled oscillator can oscillate. On the other hand, in a system using a PLL circuit,
The frequency band of the system clock may vary greatly depending on the type of the system. From such a viewpoint, in order to enable a single PLL circuit to cope with a plurality of types of the system, a PLL circuit that can lock a wide frequency band or lock a plurality of different frequency bands is required. Is done.

[0004]

As described above, in order to make a PLL circuit which can be locked to a reference clock having a plurality of frequencies which cannot be covered by the frequency band of one voltage-controlled oscillator, a plurality of PLL circuits having different oscillation frequency bands are required. Equipped with voltage-controlled oscillators, these voltage-controlled oscillators are appropriately switched in accordance with the frequency of the reference clock, and the frequency division ratio of the frequency divider that divides the oscillation clock of the voltage-controlled oscillator is made variable,
In general, a configuration is adopted in which the frequency division ratio is appropriately switched according to the frequency of the reference clock.

However, in this type of conventional circuit, a plurality of voltage controlled oscillators are appropriately switched according to the frequency of the reference clock, and the frequency division ratio of a frequency divider for dividing the oscillation clock of the voltage controlled oscillator is appropriately switched. Each time, a switching signal must be supplied from the outside to switch.

Therefore, the present invention provides a PLL capable of autonomously switching between a plurality of voltage controlled oscillators and switching the frequency division ratio of an oscillation clock in accordance with the frequency of a reference clock.
It is intended to provide a circuit.

[0007]

A PLL circuit according to the present invention comprises a plurality of oscillators having different oscillation frequency bands, a selector for selecting one of the plurality of oscillators, and a selector for selecting one of the oscillators. Phase divider that compares the phase of the frequency-divided clock divided by the frequency divider with the externally supplied reference clock and outputs pulse-like comparison information Means, voltage applying means for applying a voltage signal corresponding to the pulse-shaped comparison information to the oscillator as its control voltage, detecting that the voltage signal has become larger than a predetermined level, and sending the detection result to the selector. And a detecting means for giving the selection information.

Another PLL circuit according to the present invention provides a single oscillator, a variable frequency divider which divides an oscillation clock of the oscillator and has a variable frequency division ratio, and a reference clock supplied from the outside. Phase comparing means for comparing the phases of the frequency-divided clocks divided by the frequency divider and outputting pulse-like comparison information, and applying a voltage signal corresponding to the pulse-like comparison information to the oscillator as a control voltage thereof. A voltage applying means and a detecting means for detecting that the voltage signal has become larger than a predetermined level and providing the detection result to the variable frequency divider as selection information of the frequency division ratio are provided. .

A PLL circuit according to the present invention, that is, a plurality of oscillators having different oscillation frequency bands is mounted, and these oscillators are appropriately switched according to the frequency of a reference clock, or a frequency divider for dividing the oscillation clock of the oscillator. In a PLL circuit in which the frequency division ratio of the frequency divider is made variable and the frequency division ratio is appropriately switched in accordance with the frequency of the reference clock, when the phase shift of the frequency division clock with respect to the reference clock increases, the voltage increases accordingly. The level of the voltage signal output from the applying means increases. When the voltage signal level exceeds a predetermined level, the oscillator cannot oscillate any more. Therefore, the limit is detected by the detecting means, and the detection result is used as information for selecting one of the plurality of oscillators or information for selecting the frequency division ratio of the variable frequency divider.

[0010]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. As is clear from FIG. 1, the PLL circuit 10 according to the present embodiment includes a plurality of voltage-controlled oscillators (VC
O), a phase control loop system 20 for performing normal phase lock control, and a band switching circuit system 30 for switching a band (frequency band) by appropriately selecting one of a plurality of voltage controlled oscillators. It is composed of

The phase control loop system 20 includes a frequency phase comparator 21, a gate circuit 22, charge pump (CP) circuits 23U and 23D, a loop filter 24, and a sense amplifier 2.
5, for example, two voltage controlled oscillators 26-1 and 26-2, a selector 27 and a frequency divider 28.
A reference clock RCK is input to the phase control loop system 20 from outside. As this reference clock RCK, a clock having a different frequency depending on the purpose of use is input, and its frequency band is one voltage-controlled oscillator 26-1 / 2.
It is assumed to be wider than 6-2.

In the phase control loop system 20, a frequency phase comparator 21 is provided with an externally applied reference clock RC.
K is one input, the frequency-divided clock VCK of the frequency divider 28 is the other input, the frequency and the phase of the frequency-divided clock VCK are compared with the reference clock RCK, and the UP / DOWN signal is output as the comparison result. . Here, the UP signal is a pulse-shaped signal for increasing the frequency or advancing the phase, and the DOWN signal is a pulse-shaped signal for decreasing the frequency or delaying the phase.

The gate circuit 22 includes two 2-input AND gates 22U and 22D. AND gates 22U and 22D receive the UP signal and the DOWN signal output from frequency phase comparator 21 as one input, respectively.
A gate control signal GCS output from a band switching circuit system 30 described later is used as the other input. In the AND gates 22U and 22D, the other inputs to which the gate control signal GCS is applied are negative logic inputs.

The charge pump circuit 23U outputs a current pulse-width modulated by the UP signal supplied from the frequency phase comparator 21 through the AND gate 22U.
Similarly, the charge pump circuit 23D also receives DOW supplied from the frequency / phase comparator 21 through the AND gate 22D.
The pulse width modulated current is output by the N signal. The loop filter 24 includes resistors R11 and R12 and a capacitor C11, and includes charge pump circuits 23U and 23U.
The output current of D is smoothed to generate a DC voltage at both ends.

The sense amplifier 25 includes a loop filter 24
POS and NEG are sensed with respect to the voltage control oscillators 26-1 and 26-2, and the control voltages FAST and FAST are used to advance or delay the phase of the oscillation clock.
It has a function as a voltage applying means given as SLOW. An example of a specific circuit configuration of the sense amplifier 25 is shown in FIG.

As is apparent from FIG. 2, the sense amplifier 25 has input terminals 251 and 252 to which the voltages POS and NEG across the loop filter 24 are supplied, and a control input to which a discharge control signal DIS is supplied from the hand switching circuit system 30. It has a terminal 253 and output terminals 254 and 255 for outputting control voltages FAST and SLOW.

The circuit configuration is such that the base is connected to the input terminal 252 and the output terminal 255, and the collector is connected to the input terminal 252.
The transistor Q11 has a base connected to the input terminal 251 and the output terminal 254, and a collector connected to the output terminal 255.
12, resistors R13 and R14 connected between the collectors of the transistors Q11 and Q12 and the power supply Vcc, resistors R15 and R16 each having one end connected to each emitter of the transistors Q11 and Q12, and each of the resistors R15 and R16. It has a constant current source 256 connected between the other end and the ground, and a negative logic control terminal of the constant current source 256 is connected to the control input terminal 253.

In the sense amplifier 25 having the above-described configuration, when the discharge control signal DIS applied to the control input terminal 253 is at the "L" level, the constant current source 256 is activated, and the constant current I0 flows through the constant current source 256. . As a result, the voltages POS and NEG across the loop filter 24 applied to the input terminals 251 and 252 are held, and are used as the control voltages FAST and SLOW.
55 to the voltage controlled oscillators 26-1 / 26-2.

On the other hand, when the discharge control signal DIS applied to the control input terminal 253 goes high, the constant current source 2
56 becomes inactive, and the current I0 flowing through the constant current source 256 becomes zero. At this time, the input terminals 251, 25
2 is pulled up to the power supply voltage Vcc by the resistors R13 and R14. As a result, the sense amplifier 25 loses the voltage holding ability.

Accordingly, the potential difference ΔV between the input terminals 251 and 252 (difference between the voltages POS and NEG), that is, the electric charge charged in the capacitor C11 is changed by the resistors R11 and R12 of the loop filter 24 and the capacitor C11. Discharge takes time determined by the time constant, and the potential difference ΔV
Becomes 0V. The waveform of the potential difference ΔV at this time is shown in the waveform diagram of FIG.

The output voltages FAST, S of the sense amplifier 25
LOW is given as a control voltage to the voltage controlled oscillators 26-1 and 26-2, and the band switching circuit system 3
Also given to 0. The voltage controlled oscillators 26-1 and 26-2 have different oscillation frequency bands, and oscillate at a frequency N times (N is a natural number) the frequency of the reference clock RCK (depending on the intended use) in each frequency band. . Each oscillation clock of the voltage controlled oscillators 26-1 and 26-2 is provided to the selector 27.

The selector 27 has a band switching circuit system 3
A clock CL which selects one of the two oscillation clocks based on a band switching signal SEL described later given from 0 and locks this to the reference clock RCK.
The signal is output as K and supplied to the frequency divider 28. The frequency divider 28 converts the oscillation clock supplied from one voltage-controlled oscillator 26-1 / 26-2 via the selector 27 into 1 / N
The clock V having the same frequency as the reference clock RCK is divided.
CK is generated, and the frequency-divided clock VCK is supplied to the frequency / phase comparator 21 as another input.

On the other hand, the band switching circuit system 30 has a configuration including a potential difference detection circuit 31 and a counter circuit 32. The band switching circuit system 30 is supplied with control voltages FAST and SLOW from the phase control loop system 20, while the band switching circuit system 30 supplies a gate control signal GCS and a loop for gate control to the phase control loop system 20. A discharge control signal DIS for controlling discharge of the capacitor C11 of the filter 24 and a band switching signal SEL for band switching are provided.

In the band switching circuit system 30, the potential difference detection circuit 31 has a hysteresis function, and as shown in the waveform diagram of FIG. 5, the potential difference between the output terminals 254 and 255 of the sense amplifier 25 (control voltage FAST, SLO
W difference) ΔV rises from 0V, and the voltage controlled oscillator 26−
The output signal Y is set to the "H" level when the oscillation frequency of the oscillation frequency of 1, 26-2 becomes close to the upper limit or the lower limit, and when the oscillation signal falls to a level close to 0 V, the output signal Y is changed to the "H" level. Set to “L” level.

Here, as an example, the voltage controlled oscillator 2
When the upper and lower limits of the oscillation frequencies of 6-1 and 26-2 are set to a potential difference ΔV = 310 mV, the potential difference detection circuit 31
When ΔV = 300 mV, the output signal Y becomes “H” level,
It is assumed that the output signal Y is set to the “L” level when ΔV = 100 mV. FIG. 4 shows an example of a specific circuit configuration of the potential difference detection circuit 31.

In FIG. 4, control voltages FAST, SLO
W is the base input of each of the transistors Q21 and Q22. The collectors of the transistors Q21 and Q22 and the power supply V
The resistors R21 and R22 are connected between cc.
A resistor R is connected between the emitters of the transistors Q21 and Q22.
23 are connected, and constant current sources 311 and 312 are connected between each emitter and the ground. Transistor Q2
1 and Q22 have transistors Q23 and Q23, respectively.
24 bases are connected.

The transistors Q23 and Q24 have their collectors connected to the power supply Vcc and their emitters connected in common. Between this emitter common connection point and ground,
The constant current source 313 is connected. Transistor Q2
The transistor Q is connected to the common emitter connection point of the transistors Q3 and Q24.
Twenty-five bases are connected. The emitter of the transistor Q25 is commonly connected to the emitter of the transistor Q26. A constant current source 314 is connected between the emitter common connection point and the ground. Between each collector of the transistors Q25 and Q26 and the power supply Vcc,
The resistors R24 and R25 are connected.

The collector of the transistor Q25 is connected to the base of the transistor Q27. Transistor Q27 has a collector connected to power supply Vcc and an emitter connected to the base of transistor Q26. Then, the collector output of the transistor Q26 is derived as the output signal Y of the potential difference detection circuit 31. The output signal Y is supplied to the counter circuit 32 at the next stage, supplied to the gate circuit 22 as its gate control signal GCS, and further supplied to the sense amplifier 25 as its discharge control signal DIS.

The counter circuit 32 in the band switching circuit system 30, for example, responds to switching of two bands by one.
The D-type flip-flop (hereinafter, referred to as D-FF) receives the output signal Y of the potential difference detection circuit 31 as a clock input, and outputs the opposite phase output Qx to the D (data). The switching signal SEL is supplied to the selector 27.

Next, the PL according to the first embodiment having the above configuration is described.
The circuit operation of the L circuit 10 will be described with reference to the timing chart of FIG. In the description of the operation of the present example, as an example, the reference clock RCK is a voltage-controlled oscillator (VC
O2) A frequency which can be locked in the oscillation frequency band of 26-2, and the anti-phase output Qx of the D-FF constituting the counter circuit 32 is currently at the "L" level.
Is selecting the oscillation clock of the voltage controlled oscillator (VCO1) 26-1.

In this state, the voltage controlled oscillator (V
Since CO1) 26-1 cannot be locked to the reference clock RCK, it settles at the upper or lower limit frequency at which oscillation is possible. Therefore, either the UP signal or the DOWN signal is frequently output from the frequency phase comparator 21. Then, the output terminals 254 and 25 of the sense amplifier 25
5 (difference between control voltages FAST and SLOW) ΔV
The output signal Y of the potential difference detection circuit 31 goes high when ΔV = 300 mV.

The output signal Y of the potential difference detection circuit 31 is "H"
At the level, the D-FF constituting the counter circuit 32
Is inverted to “H” level, the selector 27 using this as the band switching signal SEL
The oscillation clock of the voltage controlled oscillator (VCO2) 26-2 is selected. At this time, the output signal Y at the “H” level is supplied to the gate circuit 22 as the gate control signal GCS, and also supplied to the sense amplifier 25 as the discharge control signal DIS.

Then, AND gates 22U and 22D stop supplying the UP / DOWN signal to charge pump circuits 23U and 23D, and sense amplifier 25 starts discharging the charge stored in capacitor C11 of loop filter 24 by its discharging function. I do. That is, in the sense amplifier 25 shown in FIG.
By setting 0 = 0, the charge of the capacitor C11 is discharged. By this discharging operation, the potential difference ΔV between the output terminals 254 and 255 of the sense amplifier 25 becomes smaller and smaller, and when ΔV = 100 mV, the output signal Y of the potential difference detection circuit 31 becomes “L” level.

The output signal Y of the potential difference detection circuit 31 is "L"
When the level becomes the level, the AND gates 22U and 22D start supplying the UP / DOWN signal to the charge pump circuits 23U and 23D, and at the same time, the sense amplifier 25 stops the discharging operation. That is, the sense amplifier 2 shown in FIG.
5, the constant current source 256 is set to the operating state, and the constant current I
Flow 0. As a result, the capacitor C11 of the loop filter 24 can be charged. Then, the divided clock VC of the oscillation clock of the voltage controlled oscillator (VCO2) 26-2
The phase of K and the reference clock RCK are compared, and the phase control of the oscillation clock is performed based on the comparison result, thereby leading to the locked state.

As described above, a plurality (two in this example) of voltage-controlled oscillators 26 having different oscillation frequency bands are provided.
1 and 26-2, these voltage controlled oscillators 26-1 and 26-2
6-2 in the PLL circuit 10 configured to switch appropriately in accordance with the frequency of the reference clock RCK.
5 is monitored, and the selector 27 is switched when the output voltage reaches a predetermined level, thereby switching the oscillation clocks of the voltage controlled oscillators 26-1 and 26-2 to the reference clock RCK. It can be performed autonomously according to the frequency.

FIG. 7 is a block diagram showing a second embodiment of the present invention. As is apparent from FIG. 7, the PLL circuit 40 according to the present embodiment includes a phase control loop system 50 having a variable frequency divider having a variable frequency division ratio in a feedback loop.
And a band switching circuit system 60 for switching a band (frequency band) by appropriately selecting the frequency division ratio of the variable frequency divider.

The phase control loop system 50 includes a frequency phase comparator 51, a gate circuit 52, a charge pump circuit 53U,
53D, a loop filter 54, a sense amplifier 55, a voltage controlled oscillator 56, and a variable frequency divider 57. This phase control loop system 50 receives a reference clock RCK from outside. This reference clock RC
As K, clocks having different frequencies are input depending on the purpose of use, and the frequency band is wider than the band of the voltage controlled oscillator 56.

In the phase control loop system 50, a frequency phase comparator 51 is provided with a reference clock RC externally supplied.
K is one input, a frequency-divided clock VCK of the variable frequency divider 57
As the other input, compares the frequency and phase of the divided clock VCK with the reference clock RCK, and outputs an UP / DOWN signal as a result of the comparison. Where UP
The signal is a pulse-like signal for increasing the frequency or advancing the phase, and the DOWN signal is for decreasing the frequency,
This is a pulse-like signal for delaying the phase.

The gate circuit 52 comprises two 2-input AND gates 52U and 52D. The AND gates 52U and 52D receive the UP signal and the DOWN signal output from the frequency / phase comparator 51 as one input, respectively.
A gate control signal GCS output from a band switching circuit system 60 described later is used as the other input. In the AND gates 52U and 52D, the other inputs to which the gate control signal GCS is applied are negative logic inputs.

The charge pump circuit 53U outputs a current pulse-width modulated by the UP signal supplied from the frequency phase comparator 51 through the AND gate 52U.
Similarly, the charge pump circuit 52D also receives DOW supplied from the frequency / phase comparator 51 through the AND gate 52D.
The pulse width modulated current is output by the N signal. The loop filter 54 includes resistors R31 and R32 and a capacitor C31, and includes charge pump circuits 53U and 53U.
The output current of D is smoothed to generate a DC voltage at both ends.

The sense amplifier 55 includes a loop filter 54
Control voltages FAST and SLOW for sensing the voltages POS and NEG at both ends of the oscillating clock to advance or delay the phase of the oscillation clock to the voltage controlled oscillator 56.
It functions as voltage applying means. As the sense amplifier 25, the one having the circuit configuration shown in FIG. 2 is used as in the case of the first embodiment.

The voltage controlled oscillator 56 oscillates in the frequency band at a frequency N times (N is a natural number) the frequency of the reference clock RCK (depending on the purpose of use), and a clock obtained by phase-locking the oscillation clock to the reference clock RCK. CLK as well as being supplied to the variable frequency divider 57.

The variable frequency divider 57 has a variable frequency division ratio (N value), divides the oscillation clock CLK supplied from the voltage controlled oscillator 56 by 1 / N, and generates a clock having the same frequency as the reference clock RCK. VCK is generated, and this frequency-divided clock VCK is supplied to the frequency / phase comparator 51 as the other input. Here, assuming that the frequency band of the reference clock RCK differs in two stages depending on the purpose of use, the frequency division ratio of the variable frequency divider 57 can be switched in two stages. The switching of the frequency division ratio is performed by a frequency division ratio switching signal SEL provided from the band switching circuit system 60.

On the other hand, the band switching circuit system 60 has a configuration including a potential difference detection circuit 61 and a counter circuit 62. The band switching circuit system 60 is supplied with control voltages FAST and SLOW from the phase control loop system 50, while the band switching circuit system 60 supplies a gate control signal GCS and a loop for gate control to the phase control loop system 50. A discharge control signal DIS for controlling the discharge of the capacitor C31 of the filter 54 and a switching signal SEL for switching the frequency division ratio of the variable frequency divider 57 are provided.

In the band switching circuit system 60, the potential difference detection circuit 61 has a hysteresis function, and the potential difference between the output terminals of the sense amplifier 55 (control voltage FAS).
(T, SLOW difference) When ΔV rises from 0V and reaches a level close to the upper limit or lower limit of the oscillation frequency of the voltage controlled oscillator 56, the output signal Y is set to the “H” level, and then falls to 0V. When the level becomes close, the output signal Y is set to the “L” level.

As the potential difference detection circuit 61, the circuit configuration shown in FIG. 4 is used as in the first embodiment. Similarly to the first embodiment, the counter circuit 62 is constituted by one D-FF corresponding to switching of two bands, for example, and the output signal Y of the potential difference detection circuit 61 is clocked. As an input, the opposite phase output Qx becomes the D input, and is supplied to the variable frequency divider 57 as a frequency division ratio switching signal SEL. With this configuration, the circuit operation of the band switching circuit system 60 is exactly the same as in the first embodiment.

As described above, in the PLL circuit 40 configured to appropriately switch the frequency division ratio of the variable frequency divider 57 for dividing the oscillation clock CLK of the voltage controlled oscillator 56 in accordance with the frequency of the reference clock RCK. Amplifier 55
By monitoring the output voltage of the variable frequency divider 57 and switching the frequency division ratio of the variable frequency divider 57 when the output voltage becomes a predetermined level, the frequency division ratio of the variable frequency divider 57 can be switched.
It can be performed autonomously in accordance with the frequency of the reference clock RCK.

[0049]

As described above, according to the present invention,
Equipped with multiple oscillators with different oscillation frequency bands,
These oscillators are appropriately switched in accordance with the frequency of the reference clock, or the frequency division ratio of a frequency divider for dividing the oscillation clock of the oscillator is made variable, and the frequency division ratio is appropriately switched in accordance with the frequency of the reference clock. PLL with orbit configuration
In the circuit, switching of a plurality of oscillators or switching of the division ratio of the oscillation clock can be performed autonomously according to the frequency of the reference clock.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a specific circuit configuration of a sense amplifier and its peripheral circuits.

FIG. 3 is a waveform chart for explaining the operation of the sense amplifier.

FIG. 4 is a circuit diagram illustrating an example of a specific circuit configuration of a potential difference detection circuit.

FIG. 5 is a waveform chart for explaining the operation of the potential difference detection circuit.

FIG. 6 is a timing chart for explaining an operation according to the first embodiment.

FIG. 7 is a block diagram showing a second embodiment of the present invention.

FIG. 8 is a block diagram showing a basic system of a PLL circuit.

[Explanation of symbols]

10, 40 ... PLL circuit, 20, 50 ... phase control loop system, 21, 51 ... frequency phase comparator, 22, 52 ... gate circuit, 23U, 23D, 53U, 53D ... charge pump (CP) circuit, 24, 54 ... Loop filter, 2
5, 55: sense amplifier, 26-1, 26-2, 56: voltage controlled oscillator (VCO), 27: selector, 28: frequency divider, 30, 60: band switching circuit system, 31, 61:
Potential difference detection circuit, 32, 62 ... counter circuit, 57 ... variable frequency divider

Claims (6)

[Claims] 1. A plurality of oscillators having different oscillation frequency bands, a selector for selecting one of the plurality of oscillators, and a frequency divider for dividing an oscillation clock of the oscillator selected by the selector. A phase comparator for comparing the phase of the frequency-divided clock divided by the frequency divider with a reference clock supplied from outside, and outputting pulse-like comparison information; Voltage applying means for providing a corresponding voltage signal to the oscillator as its control voltage, and detecting means for detecting that the voltage signal has become larger than a predetermined level and providing the detection result to the selector as the selection information. A PLL circuit, comprising: 2. The PLL circuit according to claim 1, wherein said voltage applying means holds said voltage signal and releases holding of said voltage signal when said voltage signal is detected by said detecting means. 3. The PLL circuit according to claim 1, wherein the reference clock has a different clock frequency depending on a purpose of use, and a frequency band thereof is wider than an oscillation frequency band of each of the plurality of oscillators. 4. A single oscillator, a variable frequency divider that divides an oscillation clock of the oscillator and has a variable frequency division ratio, and a frequency divider that divides an externally supplied reference clock by the frequency divider. Phase comparing means for comparing the phases of the divided frequency-divided clocks and outputting pulse-shaped comparison information; and voltage applying means for applying a voltage signal corresponding to the pulse-shaped comparison information to the oscillator as a control voltage thereof, A PLL circuit comprising: a detection unit that detects that the voltage signal has become larger than a predetermined level, and provides a detection result to the variable frequency divider as selection information of the frequency division ratio. 5. The PLL circuit according to claim 4, wherein said voltage applying means holds the voltage signal and releases the holding of the voltage signal when the voltage signal is detected by the detecting means. 6. The PLL circuit according to claim 4, wherein a clock frequency of the reference clock varies depending on a purpose of use, and a frequency band thereof is wider than an oscillation frequency band of the oscillator.