JPH11329967A - Fabrication of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accelerate crystallization furthermore by irradiating a crystallized amorphous semiconductor film with intensive light while enhancing crystalinity through compaction of the film quality and to suppress thermal effect onto a glass substrate by lowering the heating temperature. SOLUTION: An underlying film 102 of silicon oxide is formed on a substrate 101 and a metal mask 103 is provided thereon. After depositing a nickel silicon film selectively in a region 100, the mask 103 is removed to form an intrinsic (I type) amorphous silicon film 104 which is then irradiated with infrared light to convert amorphous silicon film into nickel silicide in the region 100. It is then annealed at 550 deg.C for 4 hours in hydrogen reducing atmosphere in order to crystallize the amorphous silicon film 104. It is further annealed by irradiating with infrared light in order to accelerate crystallization of the amorphous silicon film 104. Crystal structure growing acicularly or columnarly in the parallel direction on the substrate can thereby be made compact furthermore.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device having a TFT (thin film transistor) provided on an insulating substrate such as glass, and a method for manufacturing the same.

[0002]

2. Description of the Related Art As a device having a TFT on an insulating substrate such as glass, an active liquid crystal display device and an image sensor using the TFT for driving pixels are known.

[0003] Thin film silicon semiconductors are generally used for TFTs used in these devices. Thin-film silicon semiconductors are roughly classified into two types: those made of an amorphous silicon semiconductor (a-Si) and those made of a crystalline silicon semiconductor. Amorphous silicon semiconductors are most commonly used because they have a low manufacturing temperature, can be manufactured relatively easily by a gas phase method, and have high mass productivity. Since it is inferior to a silicon semiconductor having
In order to obtain higher-speed characteristics in the future, it has been strongly required to establish a method for manufacturing a TFT made of a crystalline silicon semiconductor. Note that, as a silicon semiconductor having crystallinity, polycrystalline silicon, microcrystalline silicon, amorphous silicon containing a crystal component, semi-amorphous silicon having an intermediate state between crystalline and amorphous, and the like are known. .

A method for obtaining a silicon semiconductor in the form of a thin film having crystallinity is as follows: (1) A film having crystallinity is directly formed at the time of film formation. (2) An amorphous semiconductor film is formed, and crystallinity is imparted by the energy of laser light. (3) An amorphous semiconductor film is formed and crystallinity is imparted by applying thermal energy. Is known. However, in the method (1), it is technically difficult to uniformly form a film having good semiconductor properties over the entire surface of the substrate, and the film forming temperature is as high as 600 ° C. or higher, so that the method is inexpensive. There was also a cost problem that a glass substrate could not be used. Also, (2)
Taking the excimer laser, which is currently most commonly used, as an example, there is a problem that the irradiation area of the laser beam is small, so that the throughput is low, and the entire surface of the large-area substrate is uniformly processed. The stability of the laser is not enough, and it seems to be a next-generation technology. (3)
The method (1) has an advantage that it can cope with a large area as compared with the methods (1) and (2), but also requires a high heating temperature of 600 ° C. or more, and uses an inexpensive glass substrate. Considering this, it is necessary to further lower the heating temperature. In particular, in the case of the current liquid crystal display device, the screen size is increasing, and therefore, it is necessary to use a large glass substrate as well. When such a large glass substrate is used, shrinkage and distortion in a heating step which is indispensable for semiconductor fabrication lowers the accuracy of mask alignment and the like, and is a serious problem. In particular, in the case of 7059 glass, which is currently most commonly used, the strain point is 593 ° C., and the conventional heating crystallization method causes large deformation. In addition to the problem of the temperature, the heating time required for crystallization in the current process is several tens of hours or more, so that it is necessary to further shorten the heating time.

[0005]

SUMMARY OF THE INVENTION The present invention provides means for solving the above problems. More specifically, in the case where a method of crystallizing a thin film made of amorphous silicon by heating is used, good crystallinity and a lowering of the heating temperature, in other words, a process that can reduce the influence on the glass substrate can be reduced. For the purpose of establishment.

[Means for Solving the Problems]

The present invention is characterized in that a non-single-crystal semiconductor film crystallized by heating at a temperature of 600 ° C. or less is irradiated with strong light to further promote the crystallinity and at the same time to densify the film. In particular, a silicon film that has been crystallized by heating using a metal element that promotes crystallization, for example, nickel, emits strong light, specifically, infrared light (for example, infrared light having a peak at a wavelength of 1.3 μm). ), The silicon film is heated, and annealing is further performed to promote crystallinity.

The crystallization-promoting elements which can be used in the present invention include Group 8 elements Fe, Co, N
i, Ru, Rh, Pd, Os, Ir, and Pt can be used. The 3d elements Sc, Ti, V, Cr,
Mn, Cu, Zn can also be used. Further, according to the experiment, the action of crystallization was confirmed also in Au and Ag. In particular, a remarkable effect is obtained among the above-mentioned elements, and a TFT using a crystalline silicon film crystallized by the effect is obtained.
The operation of Ni has been confirmed for Ni.

[0008]

By irradiating infrared light to a thin-film silicon semiconductor crystallized by heating at a temperature of 600 ° C. or less, the silicon film can be selectively heated, and the crystallinity can be further promoted. . At this time, since infrared light is not easily absorbed by the glass substrate, annealing can be performed without heating the glass substrate so much.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION

[0010]

[Embodiment 1] In this embodiment, a P-channel TFT (P-type TFT) using a crystalline silicon film formed on a glass substrate is used.
This is an example of forming a circuit in which a TFT and an N-channel TFT (NTFT) are combined in a complementary manner. The configuration of this embodiment can be used for a switching element of a pixel electrode and a peripheral driver circuit of an active type liquid crystal display device, as well as an image sensor and an integrated circuit.

FIG. 1 is a sectional view showing a manufacturing process of this embodiment. First, a 2000-nm-thick silicon oxide base film 102 is formed on a substrate (Corning 7059) 101 by a sputtering method. Next, a mask 103 formed of a metal mask, a silicon oxide film, or the like is provided. The mask 103 exposes the base film 102 in a slit shape. That is, when the state of FIG. 1A is viewed from above, the base film 102 is exposed in a slit shape, and the other portions are masked. After the mask 103 is provided, the thickness is 5 to 200 ° by a sputtering method.
For example 20Å of nickel silicide film (chemical formula NiSi _x,
0.4 ≦ x ≦ 2.5 (for example, x = 2.0) is selectively formed in 100 regions. In this state, nickel is 10
0 will be introduced selectively.

Next, the mask 103 is removed. Then, the thickness is 500 to 1500 by the plasma CVD method.
{, For example, 1000} intrinsic (I-type) amorphous silicon film 1
04 is formed. And 0.5 to 5 μm, here 1 to
Irradiation with infrared light having a peak at 1.5 μm is performed for several seconds to several minutes, and the amorphous silicon film is made into nickel silicide in the region of 100. This step is effective for effectively diffusing nickel into the silicon film.

Then, under a hydrogen reducing atmosphere (preferably,
Annealing is performed for 4 hours at 550 ° C. or at 550 ° C. in an inert atmosphere (atmospheric pressure) at a partial pressure of hydrogen of 0.1 to 1 atm. At this time, in the region 100 where the nickel silicide film is selectively formed, crystallization of the crystalline silicon film 104 occurs in a direction perpendicular to the substrate 101. Then, in a region other than the region 100, as shown by an arrow 105, crystal growth is performed in a lateral direction (a direction parallel to the substrate) from the region 100.

After this step, the above-described infrared light irradiation is performed.
Annealing for further crystallization of the silicon film 104
Lengthen. During this annealing, a protective film is formed on the surface
It is preferable to form a silicon nitride film. This is silicon
This is for improving the state of the surface of the film 104. Also,
In order to improve the state of the surface of the silicon film 104 of FIG. _Two 
Perform this annealing in an atmosphere or HCl atmosphere.
Both are effective.

Since the annealing selectively heats the silicon film, the heating of the glass substrate can be minimized. And it is very effective in reducing the defects and the dangling bonds in the silicon film.

It is important that the infrared light annealing is performed after the crystallization step by heating. When the amorphous silicon film is annealed by the infrared light without being crystallized by heating, a crystalline silicon film having a large grain size on the order of μm can be obtained. However, this crystal has a well-defined grain boundary structure, and is not suitable for use in devices. For example, there are many clear grain boundaries in the channel formation region,
The structure is such that the movement of carriers is inhibited, which is not preferable.

On the other hand, when the silicon film crystallized in a direction parallel to the substrate by the above-described crystallization by heating is annealed by infrared light, the silicon film grown parallel to the substrate can be obtained. The crystal structure grown in the direction of needles or columns can be further densified. This further promotes the growth of a crystal having anisotropy in a one-dimensional direction, and has a feature that movement of carriers in this direction is hardly affected by crystal grain boundaries.

As a result of the above steps, the crystalline silicon film 104 can be obtained by crystallizing the amorphous silicon film. After that, isolation between elements is performed, and an active layer region of the TFT is determined. At this time, it is important that the tip of crystal growth indicated by 105 does not exist in a portion to be a channel formation region. This makes it possible to prevent carriers moving between the source and the drain from being affected by the nickel element in the channel formation region.

Next, a thickness of 10
A silicon oxide film 106 having a thickness of 00 ° is formed as a gate insulating film. For sputtering, silicon oxide was used as a target, and the substrate temperature during sputtering was 200 to 400.
° C, for example, 350 ° C, the sputtering atmosphere is oxygen and argon, and argon / oxygen = 0 to 0.5, for example, 0.1
The following is assumed.

The silicon oxide film 106 serving as the gate insulating film
After the film formation, annealing by infrared light irradiation is performed again. By this annealing, the level mainly at the interface between the silicon oxide film 106 and the silicon film 104 and in the vicinity thereof can be eliminated. This is extremely useful for an insulated gate field effect semiconductor device in which the interface characteristics between the gate insulating film and the channel formation region are extremely important.

Subsequently, by a sputtering method,
Aluminum (containing 0.1 to 2% of silicon) having a thickness of 6000 to 8000 °, for example, 6000 ° is deposited.
Then, the aluminum film is patterned to form gate electrodes 107 and 109. Further, the surface of the aluminum electrode is anodized to form an oxide layer 10 on the surface.
8, 110 are formed. In this anodization, tartaric acid is 1 to
The test was performed in an ethylene glycol solution containing 5%. The thickness of the obtained oxide layers 108 and 110 was 2000 °. Since the oxides 108 and 110 have a thickness for forming an offset gate region in a later ion doping process, the length of the offset gate region can be determined in the anodic oxidation process.

Next, an impurity for imparting one conductivity type is added to the active layer region (constituting the source / drain and the channel) by ion implantation. In this doping step, impurities (phosphorus and boron) are implanted using the gate electrode 107 and the surrounding oxide layer 108 and the gate electrode 109 and the surrounding oxide layer 110 as masks. Phosphine (PH ₃ ) and diborane (B
₂ H ₆ ), and in the former case, the accelerating voltage is 60 to 90
kV, for example 80 kV, in the latter case 40-80 k
V, for example, 65 kV. Dose amount is 1 × 10 ¹⁵ -8
× 10 ¹⁵ cm ^-2 , for example, phosphorus is 2 × 10 ¹⁵ cm ^-2 and boron is 5 × 10 ¹⁵ . At the time of doping, each element is selectively doped by covering one region with a photoresist. As a result, N-type impurity regions 114 and 116 and P-type impurity regions 111 and 11
3 is formed, and a region of a P-channel TFT (PTFT) and a region of an N-channel TFT (NTFT) can be formed.

Thereafter, annealing is performed by laser light irradiation. As the laser light, a KrF excimer laser (wavelength: 248 nm, pulse width: 20 nsec) was used, but another laser may be used. The irradiation condition of the laser beam is such that the energy density is 200 to 400 mJ / cm ² ,
For example, 250 mJ / cm ^2, and ² to 10
A shot, for example, two shots is irradiated. It is useful to heat the substrate to about 200 to 450 ° C. at the time of this laser light irradiation. In this laser annealing step, nickel is diffused in the previously crystallized region, so that the laser light irradiation facilitates recrystallization, and the impurity doped with an impurity imparting a P-type. Area 1
The impurity regions 11 and 113 and the impurity regions 114 and 116 doped with an impurity for imparting N can be easily activated.

This step may be performed by lamp annealing using infrared light. Infrared rays are easily absorbed by silicon, and effective annealing comparable to thermal annealing of 1000 degrees or more can be performed. On the other hand, since it is hardly absorbed by the glass substrate, it is not necessary to heat the glass substrate to a high temperature, and the process can be performed in a short time. .

Subsequently, a silicon oxide film 11 having a thickness of 6000.degree.
8 is formed as an interlayer insulator by a plasma CVD method. Polyimide may be used as the interlayer insulator. Further, a contact hole is formed, and TF is formed by a metal material, for example, a multilayer film of titanium nitride and aluminum.
T electrodes / wirings 117, 120 and 119 are formed. Finally, annealing is performed at 350 ° C. for 30 minutes in a hydrogen atmosphere at 1 atm to complete a semiconductor circuit in which the TFTs are configured to be complementary. (Fig. 1 (D))

The circuit shown above has a CMOS structure in which a PTFT and an NTFT are provided in a complementary manner. In the above-described process, two TFTs are simultaneously formed and cut at the center, whereby two independent TFTs are simultaneously formed. It is also possible to produce.

FIG. 2 shows an outline of FIG. 1D viewed from above. The reference numerals in FIG. 2 correspond to those in FIG. FIG.
As shown in (1), the direction of crystallization is the direction indicated by the arrow, and the crystal is grown in the direction of the source / drain region (the line direction connecting the source region and the drain region). During the operation of the TFT having this configuration, carriers move between the source and the drain along the crystal grown in a needle or column shape. That is, the carriers move along the crystal grain boundaries of needle-like or columnar crystals. Therefore, it is possible to reduce the resistance received when the carrier moves, and to obtain a TF having high mobility.
T can be obtained.

In the present embodiment, as a method of introducing Ni, Ni is selectively thinned on the base film 102 under the amorphous silicon film 104 (it is difficult to observe Ni as a thin film). Although a method of forming a crystal and performing crystal growth from this portion is adopted, a method of selectively forming a nickel silicide film after forming the amorphous silicon film 104 may be used. That is, crystal growth may be performed from the upper surface of the amorphous silicon film or from the lower surface. Alternatively, a method in which an amorphous silicon film is formed in advance and nickel ions are selectively implanted into the amorphous silicon film 104 by using an ion doping method may be employed. This case has a feature that the concentration of the nickel element can be controlled. Alternatively, a method using a plasma treatment or a CVD method may be used.

[Embodiment 2] This embodiment is an example in which an N-channel TFT is provided in each pixel as a switching element in an active liquid crystal display device. Hereinafter, one pixel will be described, but a large number (generally, hundreds of thousands) of other pixels are formed in a similar structure. Also, N
It goes without saying that a P-channel type may be used instead of a channel type. Further, it can be used not only for the pixel portion of the liquid crystal display device but also for the peripheral circuit portion. Further, it can be used for image sensors and other devices. That is, as long as it is used as a thin film transistor, its use is not particularly limited.

FIG. 3 shows an outline of the manufacturing process of this embodiment.
In this embodiment, the substrate 201 is Corning 70
59 glass substrate (1.1 mm thick, 300 × 400 m
m) was used. First, a base film 202 (silicon oxide) is formed to a thickness of 2000 ° by a sputtering method. Thereafter, in order to selectively introduce nickel, a mask 20 is formed using a metal mask, a silicon oxide film, a photoresist, or the like.
Form 3 Then, a nickel silicide film is formed by a sputtering method. This nickel silicide film is formed to a thickness of 5 to 200 °, for example, 20 ° by a sputtering method. This nickel silicide film has the chemical formula NiS
_{i x, 0.4 ≦ x ≦ 2.5} , for example, represented by x = 2.0. Thus, a nickel silicide film is selectively formed in the region 204.

Thereafter, LPCVD or plasma C
An amorphous silicon film 205 is formed to a thickness of 1000 ° by the VD method. After that, annealing by irradiation of infrared light is performed,
A silicide of the nickel silicide film and the amorphous silicon film 205 is formed. This step is to simultaneously effectively diffuse nickel into the amorphous silicon film. Then, after performing dehydrogenation at 400 ° C. for 1 hour, crystallization is performed by heat annealing. This annealing step is performed under a hydrogen reducing atmosphere (preferably, when the partial pressure of hydrogen is 0.
(1 to 1 atm) at 550 ° C. for 4 hours. This heat annealing step may be performed in an inert atmosphere such as nitrogen.

In this annealing step, since the nickel silicide film is formed in the region 204 below the amorphous silicon film 205, crystallization occurs from this portion. During this crystallization, silicon crystal growth proceeds in a direction perpendicular to the substrate 201 in the portion 204 where the nickel silicide is formed, as indicated by arrows in FIG. Similarly, as indicated by arrows, in regions where nickel silicide is not formed (regions other than region 205), crystal growth is performed in a direction parallel to the substrate.

After this heating step, the mask 103 is removed. Then, the silicon film 205 is again heat-annealed by irradiation with infrared light. Thus, a silicon film 205 made of crystalline silicon can be obtained. Next, the semiconductor film 2
05 is patterned to form an island-shaped semiconductor region (TFT active layer). At this time, it is important that the tip of the crystal grown as indicated by the arrow does not exist in the active layer, particularly in the channel formation region. Specifically, FIG.
In the case where the tip of the arrow (B) is the end point (end) for crystal growth, the crystalline silicon film 205 at the portion 204 where nickel is introduced and the portion at the end (left end in the drawing) of the arrow are removed by etching. However, it is useful to use an intermediate portion of the crystalline silicon film 205 that has grown in a direction parallel to the substrate as an active layer. This is to prevent the concentration of nickel at the tip from adversely affecting the characteristics of the TFT, based on the fact that nickel is concentrated at the tip of the crystal growth.

Further, tetraethoxysilane (TEO)
S) as a raw material, a gate insulating film of silicon oxide (thickness of 70 to 120 n) is formed by a plasma CVD method in an oxygen atmosphere.
m, typically 100 nm) 206. The substrate temperature is set to 400 ° C. or less, preferably 200 to 350 ° C. in order to prevent shrinkage and warpage of the glass.

Thereafter, heating by irradiation of infrared light is performed again to improve the interface characteristics between the silicon film 205 and the silicon oxide film 206. Next, a gate electrode 207 is formed by forming a known film containing silicon as a main component by a CVD method and performing patterning. After that, phosphorus is implanted as an N-type impurity by an ion implantation method, and a source region 208, a channel formation region 209, and a drain region 210 are formed in a self-aligned manner. By irradiating a KrF laser beam, the crystallinity of the silicon film having deteriorated crystallinity due to ion implantation is improved. At this time, the energy density of the laser beam is set to 250 to 300 mJ / cm ² . By this laser irradiation, the source / drain sheet resistance of the TFT becomes 300 to 800 Ω / cm ² . It is useful to perform this step by lamp annealing with infrared light.

In this embodiment, since the gate electrode 207 is mainly composed of silicon, the film quality of the gate electrode can be hardened by the above-described ion implantation and subsequent annealing.

Thereafter, an interlayer insulator 211 is formed of silicon oxide or polyimide, and further, a pixel electrode 212 is formed.
Is formed by ITO. Then, a contact hole is formed, and a chromium /
The electrodes 213 and 214 are formed of an aluminum multilayer film, and one of the electrodes 214 is also connected to the ITO 212. Finally, hydrogenation is completed by annealing in hydrogen at 200 to 300 ° C. for 2 hours. Thus, T
Complete FT. This process is performed simultaneously in many other pixel regions.

In the TFT manufactured in this embodiment, a crystalline silicon film grown in the direction in which carriers flow is used as an active layer constituting a source region, a channel formation region, and a drain region. , Ie, the carriers move along the crystal grain boundaries of needle-like or columnar crystals, so that a TFT having high carrier mobility can be obtained. The TFT manufactured in this example is an N-channel type, and has a mobility of 9
0 to 130 (cm ² / Vs). Conventional 600
This is large compared to the fact that the transfer to an N-channel TFT using a crystalline silicon film obtained by crystallization by thermal annealing at 48 ° C. for 48 hours is 80 to 100 (cm ² / Vs). It is an improvement in characteristics. Without annealing by irradiation with infrared light during the crystallization step and annealing by irradiation with infrared light after forming the gate insulating film, generally only low mobility and low on / off ratio can be obtained. Was.

[Embodiment 3] This embodiment is a further development of the structure of Embodiment 1 and is an example in which a TFT is formed using only a region having a low metal concentration for promoting crystallization. It is.

FIG. 4 shows a manufacturing process of this embodiment. In FIG. 4, the same reference numerals as those in FIG. 1 indicate those shown in FIG. First, a base film 102 is formed on a glass substrate 101.
Is formed, and a nickel silicide film is formed in a region of 100 using the mask 103 in the same manner as in the first embodiment. Thus 1
After nickel is introduced into the area of No. 00, annealing by infrared light is performed. Then, the mask 103 is removed. Further, an amorphous silicon film 104 is formed. Next, heat annealing at 550 ° C. for 4 hours is performed to crystallize the silicon film 104. At this time, as indicated by an arrow 105, crystal growth is performed in a direction parallel to the substrate. After the annealing by heating, annealing by irradiation with infrared light is performed again to further promote crystallinity.

In this state, the state shown in FIG. 4B is realized. In this state, a region indicated by 42 is a region where nickel is directly introduced, and is a region where nickel is present at a high concentration. The regions indicated by 41 and 43 are the end points of the crystal growth, and are also regions where nickel is present at a high concentration. It has been found that these regions have a nickel concentration that is nearly an order of magnitude higher than the crystallized regions between them.

The present embodiment is characterized in that the region having a high nickel concentration is not used. Therefore, FIG.
As shown in (C), resists 44 and 45 serving as masks
Is formed, and portions 41, 42 and 43 are removed by etching. This etching is performed by the RIE method having anisotropy in the vertical direction.

After the etching, the masks 44 and 45 are removed to obtain the shape shown in FIG. In this state, crystal growth is performed in a direction parallel to substrate 101, and crystalline silicon films 46 and 47 having a relatively low nickel concentration can be obtained. Each of the crystalline silicon films 46 and 47 functions as an active layer of a TFT or another semiconductor device, for example, a thin film semiconductor forming a thin film diode, and is a crystalline silicon film having an orientation. The nickel concentration in the film is 1
It is about 0 ¹⁷ to 10 ¹⁹ cm ^-3 .

Here, the silicon films 46 and 47 are
FIG. 4E shows a structure in which a TFT circuit is obtained which is configured to be complementary and used as an active layer of T. The configuration shown in FIG. 4E is almost the same as the configuration shown in FIG.
The structure shown in (D) is different in that the active layers of the two TFTs are continuously connected, and the nickel concentration is high in the intermediate region.

In the case where the structure as shown in FIG. 4E is employed, since there is no region having a high nickel concentration in the active layer, the operation stability can be improved.

Also in this embodiment, it is extremely effective to improve the interface characteristics between the active layers 46 and 47 and the gate insulating film by performing annealing by irradiating infrared light after forming the gate insulating film. .

[0047]

[Effect] By continuously annealing the crystalline silicon film which has been crystallized by heating with infrared light, it is possible to promote the crystallinity and at the same time to densify the film, and to obtain a good crystal. A silicon film having properties can be obtained. Furthermore, by performing annealing by irradiating infrared light after forming an insulating film on the silicon film, the interface state can be reduced, which is extremely effective particularly for forming an insulating gate type semiconductor device.

[Brief description of the drawings]

FIG. 1 shows a manufacturing process of an example.

FIG. 2 shows an outline of an embodiment.

FIG. 3 shows a manufacturing process of an example.

FIG. 4 shows a manufacturing process of an example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 Glass substrate 102 Base film (silicon oxide film) 103 Mask 104 Silicon film 105 Crystallization direction 106 Gate insulating film 107 Gate electrode 108 Anodized layer 109 Gate electrode 110 Anodized layer 111 Source / drain region 112 Channel formation region 113 Drain / Source region 114 source / drain region 115 channel formation region 116 drain / source region 117 electrode 118 interlayer insulator 120 electrode 119 electrode 201 glass substrate 202 base film (silicon oxide film) 203 mask 204 nickel trace addition region 205 silicon film 206 gate Insulating film 207 Gate electrode 208 Source / drain region 209 Channel formation region 210 Drain / source region 211 Interlayer insulator 213 Electrode 214 Electrode 212 ITO (pixel electrode)

Claims (6)

[Claims] A step of forming a semiconductor film containing amorphous silicon on an insulating surface; a step of placing a substance that promotes crystallization of the amorphous silicon in contact with the semiconductor film; A method for manufacturing a semiconductor device, comprising: a step of heating; and a step of irradiating the semiconductor film with light after the step. A step of forming a semiconductor film containing amorphous silicon on an insulating surface; a step of arranging a substance which promotes crystallization of the amorphous silicon in contact with a part of the semiconductor film; A method for manufacturing a semiconductor device, comprising: a step of heating a semiconductor film; and a step of irradiating the semiconductor film with light after the step. A step of forming a semiconductor film containing amorphous silicon on an insulating surface; a step of placing a substance which promotes crystallization of the amorphous silicon in contact with the semiconductor film; Heating; irradiating the semiconductor film with light after the step; patterning the semiconductor film; forming a gate insulating film on the patterned semiconductor film; A method of manufacturing a semiconductor device, comprising: annealing a film and the patterned semiconductor layer; and forming a gate electrode on the gate insulating film. A step of forming a semiconductor film containing amorphous silicon on an insulating surface; a step of placing a substance which promotes crystallization of the amorphous silicon in contact with a part of the semiconductor film; Heating the semiconductor film; irradiating the semiconductor film with light after the step; patterning the semiconductor film and removing the part; and gate insulating on the patterned semiconductor film Forming a film, annealing the gate insulating film and the patterned semiconductor layer, and forming a gate electrode on the gate insulating film. . 5. The method according to claim 1, wherein:
The method for manufacturing a semiconductor device, wherein the light is infrared light. 6. The method according to claim 5, wherein the infrared light is set to 0.1.
A method for manufacturing a semiconductor device, wherein a peak is in a range of 5 to 5 μm.