JPH11328360A - Automatic picture quality control unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent picture quality from being deteriorated by automatically adjusting a clock phase to an optimum value when an image signal input is converted from analog to digital. SOLUTION: The automatic picture quality control unit is equipped with a clock generation part 3 which generates a clock in a reference signal cycle and an A/D converter 2 which samples the analog image signal input with the clock and converts it into digital image data and further a phase difference detecting circuit 1 is added which detects the total of absolute values of temporal variation quantities of the digital image data; and the phase of the clock generated by the clock generation part 3 is optimized so that the detection value becomes the maximum, thereby minimizing deterioration in the picture quality of the digital image data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic image quality adjusting device used for displaying or transmitting an image, and more particularly to an analog / digital (A / D) conversion for converting an analog image signal input into a digital signal. The present invention relates to an automatic image quality adjustment device for preventing image quality deterioration when converting image data.

[0002]

2. Description of the Related Art For example, when an image is displayed using a liquid crystal display element, the image quality is degraded if one input data does not match exactly for each dot of the liquid crystal display element.
Therefore, in such a case, in an image display device or an image signal transmission device, a clock signal used when an image signal input is converted into digital data using an A / D converter,
It is necessary that the phase relationship with the clock signal used to generate the input data be properly maintained. Therefore, in such a signal system, if the phase of the clock signal used for performing the A / D conversion is different from the optimum point due to the change of the connected device, the deterioration of the image quality is reduced. Therefore, it is necessary to adjust the clock phase to the optimum point.However, conventionally, in such a case, the adjustment of the clock phase for image quality adjustment is performed by the operator while checking the image screen or the like. An adjusting method is used.

As another method, there has been a method of adjusting the image quality by compensating for the resolution of a high-saturation image in an analog manner, instead of optimizing the clock phase. An example of such a conventional image quality adjustment circuit is disclosed in Japanese Patent Application Laid-Open No. 4-44.
No. 492. The image quality adjustment circuit of this known example detects saturation information from a color signal, obtains a linear control signal corresponding to the level of saturation, converts this to a non-linear control signal, and uses this signal. By controlling the gain of the high-frequency component of the luminance signal to reduce the amplification factor on the high-saturation side rather than the low-saturation side, it compensates for the deterioration of the resolution of the high-saturation image of the television signal in the transmission path. I am trying to do it.

[0004]

However, the conventional image quality adjusting device has the following problems. That is, in an apparatus for converting an image signal input into digital data using an A / D converter, a device connected to the input side is changed so that the phase of a clock used when performing A / D conversion is optimized. If this is not the case, the image quality will be degraded, so it is necessary to adjust the clock phase to the optimum point. However, this adjustment must be made while the operator checks the video screen and the like. There was a point. This is because the phase at the time of clock recovery from the input synchronization signal cannot be managed, or even if the clock phase is managed, the A / D conversion is not actually performed at the optimum clock phase. Because there is.

Further, when an input signal is connected such that the phase of a clock used for generating an image signal is not stable at a signal generation source with the passage of time, the image signal input is converted into digital data by A / D conversion. When converting, the optimum point of the clock phase changes. However,
In the conventional image quality adjustment method, the adjustment of the clock phase was not performed automatically. Therefore, once the clock phase was adjusted, the adjustment remains unchanged from the optimum point unless the operator adjusts again. There was a problem that

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and in order to prevent the image quality from deteriorating when an image signal input is converted into digital data by performing A / D conversion, the clock phase is always adjusted to an optimum point. It is an object of the present invention to provide an automatic image quality adjustment device that can maintain the image quality.

[0007]

According to a first aspect of the present invention, there is provided a clock generating means for generating a clock at a reference signal period, and sampling an analog image signal input by the clock to obtain a digital signal. The present invention relates to an automatic image quality adjusting apparatus including an analog / digital conversion means for converting image data into image data, wherein phase difference detection means for detecting the total absolute value of the temporal change amount of the digital image data is added, It is characterized in that the phase of the generated clock in the clock generating means is optimally controlled so that the detected value is maximized.

According to a second aspect of the present invention, there is provided the automatic image quality adjusting apparatus according to the first aspect, wherein the phase difference detecting means delays the digital image data for a predetermined period, the digital image data and the delay. It is characterized by comprising a synthesizer for obtaining a difference from data, an absolute value generating means for obtaining an absolute value of the difference, and an adding means for adding the absolute value for a predetermined range of the screen to obtain a total.

According to a third aspect of the present invention, there is provided the automatic image quality adjusting apparatus according to the second aspect, wherein the storage means is configured to output the digital image data with a delay of one clock period. I have.

According to a fourth aspect of the present invention, there is provided the automatic image quality adjusting apparatus according to the second or third aspect, wherein the adding means adds the absolute value of the difference over a two-dimensional range on the screen. It is characterized by:

According to a fifth aspect of the present invention, there is provided the automatic image quality adjusting apparatus according to the second or third aspect, wherein the adding means adds the absolute value of the difference over a one-dimensional range on the screen. It is characterized by:

According to a sixth aspect of the present invention, there is provided the automatic image quality adjusting apparatus according to the fifth aspect, wherein the one-dimensional range is a range of one horizontal line.

[0013]

According to the present invention, there is provided an apparatus comprising: a clock generating means for generating a clock at a reference signal period; and an analog / digital converting means for sampling an analog image signal input by the clock and converting the input into digital image data. A phase difference detecting means for detecting a total of absolute values of a temporal change amount of the digital image data, and optimally controlling a phase of a generated clock in the clock generating means so that the detected value is maximized. Therefore, it is possible to control image quality deterioration in the digital image data to a minimum.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. The description will be specifically made using an embodiment. FIG. 1 is a block diagram showing an electrical configuration of an embodiment of the present invention, FIG. 2 is a diagram showing an example of a configuration of a phase difference detection circuit, and FIG. 3 is a diagram showing a relationship between image digital data and position data on a screen. FIG. 4 is a diagram illustrating a relationship between a clock phase and an addition result output. FIG. 5 is a diagram illustrating an effect of clock phase control. FIG. 6 is a flowchart illustrating an automatic image quality adjustment operation. As shown in FIG. 1, the automatic image quality adjustment device of this example includes a phase difference detection circuit 1 and an A / D
It is roughly composed of a converter 2, a clock generator 3, and a controller 4. The phase difference detection circuit 1 adds the absolute value of the change amount of the digital image data within a certain period for a predetermined range of the screen, and outputs an addition result. A /
The D converter 2 converts an image signal input composed of analog data into digital data. The clock generator 3 generates a clock having a frequency dependent on the external reference signal, and changes the phase of the output clock according to the phase delay amount setting data. The control unit 4 includes the phase difference detection circuit 1
And controls the entire operation of the automatic image quality adjustment device including the clock generation unit 3 and the clock generation unit 3.

The phase difference detecting circuit 1 comprises a pixel memory 11, a synthesizer 12, and an absolute value circuit 13 as shown in FIG.
And an adder circuit 14. The pixel memory 11 holds the digital data output from the A / D converter 2 for one clock period and outputs the digital data. In addition, the synthesizer 12 has A
Digital data output from the / D converter 2 and the pixel memory 11
From the digital data delayed by one clock period. Further, the absolute value circuit 13 includes the synthesizer 1
The absolute value of the output signal is obtained and output. Adder circuit 14
Generates an output by adding the output of the absolute value circuit 13 for a predetermined period.

Next, the operation of the automatic image quality adjusting apparatus of this embodiment will be described with reference to FIGS. The image signal input a composed of analog data is sampled in the A / D converter 2 with reference to the clock signal b from the clock generator 3 and converted into digital data c.
The data is output to an image data processing unit (not shown). The clock generating unit 3 is composed of a PLL (Phase Locked Loop) or the like, and generates a clock signal b based on an external reference signal input d composed of a vertical synchronizing signal or a horizontal synchronizing signal of an image signal. The phase of the output clock is controlled by the clock phase delay amount setting data e from the unit 4. The clock phase delay amount setting data e is digital data composed of an arbitrary number of bits, and one bit thereof corresponds to the minimum unit delay amount of the phase delay amount necessary for automatic image quality adjustment. The digital data c from the A / D converter 2 is also input to the phase difference detection circuit 1. The phase difference detection circuit 1 outputs to the control unit 4 an addition result output g during a period specified by the phase difference detection circuit control signal f output from the control unit 4.

In the phase difference detecting circuit 1, the digital data from the A / D converter 2 is stored in the image memory 11 and the combiner 1
2 + input. The image memory 11 delays the digital data from the A / D converter 2 by one clock period and outputs the digital data from the A / D converter 2 by a clock signal in the phase difference detection circuit control signal f input from the control unit 4. The synthesizer 12 takes the difference between the digital data from the A / D converter 2 and the digital data delayed by one clock from the image memory 11 and outputs the result. The difference signal is converted into an absolute value by the absolute value circuit 13 and then added by the adding circuit 14 at a clock timing. However, the addition in this case is performed only for a predetermined period according to the addition on / off signal in the phase difference detection circuit control signal f. This is to prevent addition of unnecessary data such as a blanking signal on the screen. The image memory 11 and the adder circuit 14 are reset as necessary, for example, at the start of an automatic image quality adjustment operation, in response to a reset signal in the phase difference detection circuit control signal f.

FIG. 3 shows an example of the correspondence between digital image data and position data on the screen. The position data is configured as two-dimensional data. Here, for convenience of description, the image is composed of n + 1 pieces of data from 0 to n in the horizontal direction and 26 lines of data from A to Z in the vertical direction. It is assumed that Here, the digital image data is first input in the horizontal direction from left to right in the order of A0, A1, A2,..., An-1, and An. When it reaches the right end, it returns to the left again and goes down by one line. B0, B1, B2,..., Bn−1,
Bn, and Z0, Z1, Z2,.
n-1 and Zn are input in this order. The control unit 4 can perform addition by using position data at an arbitrary position on an arbitrary line as an addition on / off signal as needed. For example, assuming that an image required for addition of image data surrounded by a dotted line in FIG. 3 is a range surrounded by a rectangle having B1 and Yn-1 as diagonals, the addition ON / OFF signal is A0
To An and B0 are off, B1 to Bn-1 are on, Bn and C0 are off, C1 to Cn-1 are on, and similarly, Y1 to Yn-1 are on. , Yn and Z0 to Zn are turned off.

FIG. 4 shows the relationship between the addition result output g and the clock phase at the optimum point when the phase of the clock signal in the phase difference detection circuit control signal f is changed. In this case, the point at which the addition result output g is maximum is determined as the clock phase optimum point, and the value of the clock phase delay amount setting data e at that time is determined as the phase difference between the optimum points.

FIG. 5 illustrates how to control the clock phase when A / D-converting the image signal input in this example to minimize the deterioration of the image quality of the digital image data. As shown in FIG. 5A, in the screen X, one image signal is output during the black level as an image signal.
Consider the case where a white level signal P for a pixel is input.
This signal usually has a rounded waveform on the transmission line, and
As shown in (b), the waveform has a slope at the rise and fall. Now, it is assumed that this waveform has an amplitude as shown at each clock phase point. In this case, when sampling the input waveform example at the peak point, FIG. 5 (c), the clock phase A ₁ and by being sampled at A _2, A ₁ point and A ₂
As a result of the amplitude changes of (1.0) and (-1.0) at the points, the sum of the absolute values of the temporal changes of the output digital data is (2.0). Also, when sampling the input waveform in the middle of the rise, as shown in FIG. 5 (d), the clock phase B _1, B _2, B ₃ results sampled at, B ₁ point, B ₂ points, B As a result of generating amplitude changes of (0.6), (-0.2), and (-0.4) at _three points, the sum of the absolute values of the temporal changes of the output digital data is (1.2). . As described above, the magnitude of the sum of the absolute values of the temporal changes in the output digital data changes according to the change in the clock phase for sampling the input signal. As a result of such phenomena occurring in various parts of the screen, when the total absolute value of the temporal change of the output digital data is obtained for a certain range of the screen, the sampling clock phase is averaged over the entire target range. This value is maximized for the optimal point. Therefore, conversely, by controlling the clock phase so that the total value becomes maximum, the sampling clock phase can be controlled to the optimum point.

FIG. 6 shows an operation example of the automatic image quality adjusting apparatus of this embodiment. At the start of the operation of the automatic image quality adjustment, the clock phase delay amount setting data e is reset (step S
1) Adjustment is started from an initial value. Next, the pixel memory 1
1 and the contents of the adder circuit 14 and the position data of the control section 4 are reset (step S2) and set as initial values.
Next, it is determined whether or not the addition on / off signal from the control unit 4 is within the addition on range (step S3).
If the addition is ON, the absolute value of the output of the synthesizer 12 is added by the addition circuit 14 (step S4). If the addition is off, the addition by the addition circuit 14 is not performed. next,
The position data is incremented (step S5). It is determined whether or not the incremented value is an end value, that is, whether or not the processing for all data on the screen is completed (step S).
6) If not completed (NO), the process returns to step S3 to determine whether to add the next position data.
In the case of completion (YES), the addition result output g is recorded in the control section 4 (step S7), and the value of the clock phase delay amount setting data e is incremented by a value corresponding to the resolution required for image quality adjustment (step S8). ). next,
It is determined whether or not the value of the clock phase delay amount setting data e has reached an end value, that is, whether or not measurement of a range necessary for automatic image quality adjustment has been completed (step S9).
In the case of O), the flow returns to step S2 to add the data of one screen again, and in the case of termination (YES), the clock phase delay amount setting data e at which the addition result output g has the maximum value is obtained. Is set as the optimum point (step S10), thereby ending the automatic image quality adjustment processing.

As described above, according to the automatic image quality adjusting apparatus of this embodiment, the absolute value of the difference value with the delay data in the digital data obtained by A / D conversion of the image signal input by the clock signal is specified. Can be obtained as the optimum point, and the clock phase for A / D conversion of the image signal input can be controlled so as to always be optimal. Therefore, the image signal input can be controlled. Can be automatically and automatically minimized in image quality degradation of digital data when A / D conversion is performed.

Although the embodiment of the present invention has been described in detail with reference to the drawings, the specific configuration is not limited to this embodiment, and there are design changes and the like without departing from the gist of the present invention. Even this is included in the present invention. For example, in the phase difference detection circuit, the range of the image for which the optimum point of the clock phase is obtained is not limited to the two-dimensional image data shown in the embodiment, but may be any one-dimensional range on the screen, for example, one horizontal data. Focusing only on this, the phase delay amount setting data e may be obtained such that the addition result output g of the phase difference detection circuit with respect to this becomes maximum.

[0024]

As described above, according to the automatic image quality adjusting apparatus of the present invention, in an apparatus for converting an image signal input into digital data using an A / D converter, a device connected to the input side Is changed and the phase of the clock used for A / D conversion changes, the operator automatically adjusts to the optimum clock phase without having to adjust the clock phase while checking on the screen. can do. Further, according to the automatic image quality adjusting apparatus of the present invention, even when an input signal whose clock phase at the time of signal generation is not stable with time is connected, the optimum clock phase state is always maintained following the change of the input signal. Can be adjusted. Therefore, according to the automatic image quality adjusting device of the present invention, A /
In a device for converting an image signal input into digital data using a D converter, deterioration of the image quality of the converted digital data can always be kept to a minimum.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an electrical configuration of an embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration example of a phase difference detection circuit.

FIG. 3 is a diagram showing a relationship between image digital data and position data on a screen.

FIG. 4 is a diagram illustrating a relationship between a clock phase and an addition result output.

FIG. 5 is a diagram illustrating the effect of clock phase control.

FIG. 6 is a flowchart illustrating an automatic image quality adjustment operation.

[Explanation of symbols]

 Reference Signs List 1 phase difference detection circuit (phase difference detection means) 2 A / D converter (analog / digital conversion means) 3 clock generation unit (clock generation means) 4 control unit 11 pixel memory (storage means) 12 synthesizer (synthesis means) 13 Absolute value circuit (absolute value generation means) 14 Addition circuit (addition means)

Claims (6)

[Claims] 1. An automatic image quality adjusting apparatus comprising: clock generating means for generating a clock with a reference signal period; and analog / digital converting means for sampling an analog image signal input by the clock and converting it into digital image data. Phase difference detecting means for detecting the total absolute value of the temporal change amount of the digital image data, and optimally controlling the phase of the generated clock in the clock generating means so that the detected value is maximized. An automatic image quality adjustment device, characterized in that it is configured to perform 2. The storage device according to claim 1, wherein the phase difference detection unit delays the digital image data for a predetermined period, a synthesis unit obtains a difference between the digital image data and the delay data, and an absolute value obtains an absolute value of the difference. 2. The automatic image quality adjusting apparatus according to claim 1, further comprising: a value generating unit; and an adding unit that adds the absolute value to a predetermined range of the screen to obtain a total. 3. The automatic image quality adjustment device according to claim 2, wherein said storage means is configured to output said digital image data with a delay of one clock period. 4. The automatic image quality adjusting device according to claim 2, wherein said adding means adds the absolute value of said difference over a two-dimensional range on a screen. 5. The automatic image quality adjusting device according to claim 2, wherein said adding means adds the absolute value of said difference over a one-dimensional range on a screen. 6. The automatic image quality adjustment device according to claim 5, wherein the one-dimensional range is a range of one horizontal line.