JPH11327904A - Microprocessor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a microprocessor capable of normally advancing a program even in the case that an old branching instruction is executed at a position unpredictable by a programmer on the program. SOLUTION: This microprocessor is provided with an old branching instruction execution circuit 15 for executing the old branching instruction, stacking the return addresses of a relatively short word length in a stack area 32 and preserving the return addresses of a relatively long word length and a stack constructing instruction execution circuit 17 for executing a stack constructing instruction and changing the return addresses of the relatively short word length stacked in the stack area 32 to the return addresses of the relatively long word length.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a microprocessor that fetches and executes an instruction.

[0002]

2. Description of the Related Art With the development of LSI technology in recent years, the capacity of memories has been increased, and accordingly, a new type of microprocessor capable of handling a wide address space has been developed. These new microprocessors are so-called compatible so that they can use software that is a legacy asset developed for older microprocessors that can handle only a small address space. Is desired. Naturally, it is also desired to have so-called expandability so that a wide address space can be used freely.

[0003] Under such a demand, the conventional new microprocessor is designed to correspond to an old instruction which is used in software for the old microprocessor and assumes a narrow address space, and newly corresponds to the old instruction. There is a new instruction that assumes a wide address space, as defined in, and branch instructions such as call instructions and restart instructions that return addresses to the stack and branch to the branch destination address are stored in the narrower stack. An old branch instruction corresponding to an address space and having a short word-length return address stacked thereon, and a new branch instruction corresponding to a wide address space and having a long word-length return address stacked thereon are prepared.

When a branch is performed by such an old branch instruction, when returning from the branch destination to the branch source after the branch, it is necessary to return to the branch source based on a return address having a short word length. For this reason, in order for the program to proceed normally after the execution of the old branch instruction, the positional relationship between the branch destination and the branch source must satisfy a predetermined restriction condition. The program is designed so that the old branch instruction is executed at a position satisfying the restriction condition.

[0005]

However, the old branch instruction is not only executed at a position on the program that is planned by the programmer, but also by a peripheral circuit designed on the basis of the old branch instruction. In some cases, the program is executed at a location that cannot be predicted by the programmer.

For example, when an old branch instruction is interrupted by an interrupt circuit and executed preferentially, or when an instruction on a program is rewritten to an old branch instruction by a debugging device, the position at which an interrupt is generated is determined. The position where the instruction is rewritten cannot be predicted by the programmer. Therefore, there is a problem that normal progress of the program is not guaranteed.

Moreover, it may be difficult or impossible to redesign such a peripheral circuit designed on the assumption of the old branch instruction on the basis of the new branch instruction.

The present invention has been made in view of the above circumstances, and provides a microprocessor capable of normally executing a program even when an old branch instruction is executed at a position on a program which cannot be predicted by a programmer. The purpose is to do.

[0009]

According to a first aspect of the present invention, there is provided a first microprocessor connected to a memory having a stack area in which data is stacked and a program area in which a plurality of instructions are stored. A branch instruction execution circuit for executing a branch instruction that stacks a return address on a stack area and branches to a branch destination address on a program area,
A determination circuit for determining whether or not the instruction stored at the branch destination address is a predetermined stack construction instruction, wherein the branch instruction execution circuit determines whether the instruction stored at the branch destination address is a predetermined stack According to a feature of the present invention, a return address having a relatively long word length or a return address having a relatively short word length is loaded in the stack area in accordance with whether or not it is determined that the instruction is a construction instruction.

In a first microprocessor of the present invention, the memory has an address space including two address space portions each provided with both the program area and the stack area. The instruction execution circuit, depending on whether or not the instruction stored at the branch destination address is a predetermined stack construction instruction by the determination circuit, respectively, returns a relatively long word-length return address, Stack on the stack area provided in the address space where the stack construction instruction exists,
Alternatively, it is preferable that a return address having a relatively short word length be loaded on a stack area provided in the address space where the branch instruction exists.

A second microprocessor according to the present invention for achieving the above object is connected to a memory having a stack area for storing data and a program area in which a plurality of instructions are stored, and sequentially fetches and executes the instructions. In a microprocessor, a branch instruction execution circuit for executing a branch instruction for stacking a return address in a stack area and branching to a branch destination address, and a stack construction instruction for reconstructing the return address stacked in the stack area by the branch instruction execution circuit. A stack construction instruction execution circuit to be executed, wherein the branch instruction execution circuit stores a return address having a relatively short word length in the stack area and stores a return address having a relatively long word length. The stack construction instruction execution circuit uses a relatively short word-length return address stacked in the stack area. Wherein the relatively word length stored by branch instruction execution circuit is to change the long return address.

Here, "storing a return address having a relatively long word length" does not limit the place where the return address is saved, and may be saved inside the branch instruction execution circuit. A register or the like may be provided and stored in the register or the like, or may be stored in a stack area. Alternatively, the entire return address having a relatively long word length may be stored, or only the portion exceeding the return address having a relatively short word length may be stored.

According to a second microprocessor of the present invention, the memory has an address space composed of two address space portions each provided with both the program area and the stack area. The instruction execution circuit stores a return address having a relatively short word length in a stack area provided in the address space where the branch instruction exists, and stores the address space where the branch instruction exists in the two address space portions. In addition to storing the specified space portion information, the return address having a relatively long word length is stored. The stack construction instruction execution circuit is specified by the space portion information stored by the branch instruction execution circuit. Reads a return address with a relatively short word length stacked on the stack area provided in the To, the stack area provided in the address space portion where the stack building instruction is present, it is preferred that relatively word length stored by the branch instruction execution circuit is intended to gain long return address.

It is preferable that the first and second microprocessors of the present invention include an interrupt receiving circuit that receives the branch instruction and causes the branch instruction execution circuit to execute the received branch instruction preferentially. .

The interrupt accepting circuit may be a circuit provided with a circuit for inhibiting acceptance of a branch instruction until a return address is appropriately stacked on the stack area.

[0016]

Embodiments of the present invention will be described below.

FIG. 1 is a diagram showing a first embodiment of a microprocessor according to the present invention.

The microprocessor 10 can handle a 24-bit address space, and is compatible with an old microprocessor which assumes a 16-bit address space. The microprocessor 10
Is connected to an interrupt circuit 20 and a memory 30 via a bus 40. The memory 30 has a 24-bit address space, in which a program area 31 in which a program is stored, Are stacked.

In the microprocessor 10, an old branch instruction for stacking a 16-bit return address in the stack area 32 and branching to a branch address, and a 16-bit return address stacked in the stack area 32 are stored in a 24-bit area. A stack construction instruction for changing to a return address is prepared. The interrupt circuit 20 outputs an interrupt request signal of logic “1” to the microprocessor 10 as necessary, and also connects the bus 40 to the microprocessor 10. Output the old branch instruction via

The microprocessor 10 includes:
A bus control circuit 11 and an interrupt receiving circuit 12 are provided, and the bus control circuit 11 controls data input / output via the bus 40. An AND gate 121 is connected to the interrupt receiving circuit 12, and an interrupt request signal from the interrupt circuit 20 is input to the AND gate 121. Further, the interrupt receiving circuit 12
In response to the input of a signal of logic “1” from D gate 121, instructs bus control circuit 11 to receive data from interrupt circuit 20 in preference to reading data from memory. I do.

The microprocessor 10 includes:
A fetch / decode circuit 13 and a program counter 14 are provided. The fetch / decode circuit 13 fetches an instruction from the program area 31 via the bus 40 and the bus control circuit 11 or an instruction from the interrupt circuit 20. Is taken in. Thereafter, the instruction is decoded by the fetch / decode circuit 13, and a signal instructing the operation of each unit is sent to each unit of the microprocessor. When the fetch / decode circuit 13 decodes the old branch instruction, the fetch / decode circuit 13 outputs the logical "0" interrupt disable signal until the instruction stored at the branch destination address is fetched after decoding.
Output to the gate 121. As a result, the AND gate 12
The output of 1 becomes a signal of logic "0" which is the logical sum of the interrupt request signal and the interrupt disable signal, and this output is input to the interrupt accepting circuit 12 to disable the interrupt.
Each time an instruction is fetched by the fetch / decode circuit 13, the count value of the program counter 14 is updated to a value indicating the next address on the program area 31 where the fetched instruction was stored.

The microprocessor 10 includes:
An old branch instruction execution circuit 15 and a register 16 are provided. When the old branch instruction is decoded by the fetch / decode circuit 13, the old branch instruction execution circuit 15 returns a return address based on the count value of the program counter 14. Is recognized, and a 16-bit return address is stored in the stack area 32 via the bus 40 and the bus control circuit 11.
Stacked as shown in FIG. 2 described later, and a 24-bit return address is stored in the register 16. Thereafter, the old branch instruction execution circuit 15 updates the count value of the program counter 14 to a count value indicating the branch destination address, and the fetch / decode circuit 13 sets the bus 4 based on the count value of the program counter 14.
0 and the program area 3 via the bus control circuit 11
The instruction is fetched from the branch destination address on 1.

The fetch / decode circuit 13 includes a judgment circuit 1
The determination circuit 131 determines whether the instruction fetched by the fetch / decode circuit 13 next to the old branch instruction is a stack construction instruction.

The microprocessor 10 includes:
A stack construction instruction execution circuit 17 is provided. The stack construction instruction execution circuit 17 determines by the determination circuit 131 that the instruction fetched next to the old branch instruction by the fetch / decode circuit 13 is a stack construction instruction. In response to the result, a 16-bit return address is fetched from the stack area 32 via the bus 40 and the bus control circuit 11, and a 24-bit return address stored in the register 16 is fetched. 11
, A 24-bit return address is stacked in the stack area 32. As a result, the return address stored in the stack area 32 is reconstructed.

FIG. 2 is a diagram showing a data structure constructed in the stack area by the microprocessor of the first embodiment.

Data is stacked on the stack area 32 from the upper side to the lower side in the figure. Also, stack area 3
2 stores a parameter D10 used at the branch destination before the return address is stored by the microprocessor 10 shown in FIG.

FIG. 2A shows a data structure constructed when a return address is stacked by the old branch instruction execution circuit 15 shown in FIG. 1. A parameter D10 is followed by a return address. Eight bits D20 from the eighth bit to the fifteenth bit are stacked, and then D30 of eight bits from the 0th bit to the seventh bit of the return address are stored.
Is piled up.

FIG. 2B shows a data structure constructed when the return address is re-stacked by the stack construction instruction execution circuit 17 shown in FIG. 1. The parameter D10 is followed by the return address. , 16-th to 23-th bits, D40, are stacked, and then the return address, 8-bit to 15-th bits, D50, are stacked. Eight bits D60 from the 0th bit to the 7th bit are stacked.

These data structures are ultimately selected by the microprocessor depending on whether or not a stack construction instruction exists at the branch destination, but the program is branched by the old branch instruction. The branch destination is a position in the program that is predetermined by the programmer regardless of the position where the branch occurs. Therefore, the programmer can cause the microprocessor to stack the 24-bit return address by writing the stack construction instruction at the branch destination that is scheduled when an interrupt occurs or the like. Regardless, the normal progress of the program is guaranteed.

In the first embodiment, 24 bits are stored in the register.
A bit return address is stored, but the microprocessor of the present invention stores only a portion of a relatively long word length return address that exceeds a relatively short word length return address. Is also good.

Hereinafter, other embodiments of the microprocessor of the present invention will be described. Circuits and the like similar to those shown in FIG. 1 are denoted by the same reference numerals, and redundant description will be omitted.

FIG. 3 is a diagram showing a second embodiment of the microprocessor of the present invention.

The microprocessor 50 is provided with an old branch instruction for stacking a return address in the stack area 32 and branching to a branch destination, and a stack construction instruction as a kind of indicator.

The microprocessor 50 includes:
A prefetch circuit 51 is provided. During execution of an instruction decoded by the fetch / decode circuit 13 by the prefetch circuit 51, an instruction executed next to the instruction is:
Based on the count value of the program counter 14, the instruction fetched via the bus 40 and the bus control circuit 11 and when the execution of the instruction being executed is completed, the instruction fetched by the prefetch circuit 51 is transmitted to the fetch / decode circuit 13. Can be

The fetch / decode circuit 13 is provided with a judgment circuit 132. When the old branch instruction is decoded by the fetch / decode circuit 13, the judgment circuit 132 is taken into the prefetch circuit 51. , It is determined whether the next instruction to be executed is a stack construction instruction.

The microprocessor 50 is provided with an old branch instruction execution circuit 52. When the old branch instruction is decoded by the fetch / decode circuit 13, the old branch instruction execution circuit 52 The return address is recognized based on the count value. When the determination circuit 132 determines that the instruction fetched by the prefetch circuit 51 is a stack construction instruction, the old branch instruction execution circuit 52 outputs the stack area via the bus 40 and the bus control circuit 11 to the stack area. 32, a 24-bit return address is stacked, and if it is determined that the instruction is not a stack construction instruction, a 16-bit return address is stacked. After that, the old branch instruction execution circuit 52 updates the count value of the program counter 14 to a value indicating the branch destination address.

As a result of each operation described above, as in the first embodiment, a 24-bit return address or a 16-bit return address is used, depending on whether or not the instruction stored at the branch destination address is a stack construction instruction. The return address is stacked on the stack area 32, and normal progress of the program is guaranteed.

In the second embodiment, the decision circuit is provided in the fetch / decode circuit. However, the decision circuit according to the present invention may be a circuit independent of the fetch / decode circuit.

FIG. 4 is a diagram showing a third embodiment of the microprocessor of the present invention.

As in the microprocessor 10 shown in FIG. 1, the microprocessor 60 shown in FIG. 4 includes, in the stack area 32, an old branch instruction for stacking a 16-bit return address and branching to a branch address. A stack construction instruction for changing the stacked 16-bit return address to a 24-bit return address is provided. However, in this embodiment, the order of stacking the return address in the stack area 32 is the first order as described below.
The order is opposite to the order in the embodiment and the second embodiment.

The microprocessor 60 has a stack pointer 61, and the stack pointer 6
Reference numeral 1 denotes an address on the stack area 32 at which the last stacked data among the data stacked on the stack area 32 is stacked.
Are accessed via the bus 40 and the bus control circuit 11 on the basis of the address indicated by, and each time the access to the stack area 32 is performed, the address indicated by the stack pointer 61 is updated. You.

The microprocessor 60 includes:
An old branch instruction execution circuit 62 is provided. When the old branch instruction is decoded by the fetch / decode circuit 13, the old branch instruction execution circuit 62 recognizes a return address based on the count value of the program counter 14, The 24-bit return address is stored in the stack area 3 in order from the lower side, in the order of 8 bits, contrary to the first embodiment and the second embodiment.
Then, the address indicated by the stack pointer 61 is returned by one address. As a result, as shown in FIG. 5 described later, a 16-bit return address is substantially stacked in the stack area 32. Thereafter, the old branch instruction execution circuit 62 updates the count value of the program counter 14 to a value indicating the branch destination address.

The microprocessor 60 includes:
A stack construction instruction execution circuit 63 is provided. Upon receiving a result of determination by the determination circuit 131 that the instruction stored at the branch destination address is a stack construction instruction, the stack construction instruction execution circuit 63 The address indicated by 61 is advanced by one address. As a result, as shown in FIG. 5, which will be described later, the 16-bit return address stacked in the stack area 32 is substantially 2 bits.
This will be changed to a 4-bit return address.

FIG. 5 is a diagram showing a structure of data stacked in a stack area by the microprocessor according to the third embodiment.

As in the stack area shown in FIG. 2, data is stacked in the stack area 32 shown in FIG. 5 from the upper side to the lower side in the figure, and is stacked in the reverse order to the first and second embodiments. A parameter D10 is loaded before the address.

FIG. 5A shows the data structure after the return address is stacked by the old branch instruction execution circuit 62 shown in FIG. 8 bits D70 from the 0th bit to the 7th bit of the return address, 8 bits D80 from the 8th bit to the 15th bit of the return address, and 16th bit to the 23rd bit of the return address D90 is stacked for 8 bits of the
As shown by an arrow in (A), an address where eight bits D80 from the eighth bit to the fifteenth bit of the return address are stacked is shown. Therefore, the D90 of the return address, which is stacked at an address ahead of the address indicated by the stack pointer, for eight bits from the 16th bit to the 23rd bit is ignored, so to speak, and the stack area 32
Is in a state in which a 16-bit return address is loaded.

FIG. 5B shows a data structure after the stack construction instruction is executed by the stack construction instruction execution circuit 63 shown in FIG. As described above, since the stack construction instruction execution circuit 63 is a circuit that only operates the stack pointer, the data stored in the stack area 32 is the same as that in FIG. Further, the stack pointer indicates an address in which eight bits D90 from the 16th bit to the 23rd bit of the return address are stacked as indicated by an arrow in FIG. 5B. In other words, the address indicated by the stack pointer moves from the position indicated by the arrow in FIG. 5A to the position indicated by the arrow in FIG. 5B, and substantially returns 16 bits. The address will be changed to a 24-bit return address.

After all, similarly to the first and second embodiments, in the third embodiment as well, depending on whether or not the instruction stored in the branch destination address is a stack construction instruction, each of the 24-bit instructions is a stack construction instruction. The return address or the 16-bit return address is stacked in the stack area 32, and normal progress of the program is guaranteed.

In the first and third embodiments, the stack construction instruction execution circuit reconstructs the return address only when the stack construction instruction is stored in the branch destination address. In the stack construction instruction execution circuit according to the present invention, the return address may be reconstructed regardless of the storage location of the stack construction instruction.

In the above description, the embodiment in which one stack area and one program area are provided on the address space of the memory has been described. However, compatibility with the old microprocessor assuming a narrow address space is considered. When a new microprocessor that can handle a wide address space is developed, two stack areas and two program areas are often provided.
In other words, of the wide address space that can be handled by the new microprocessor, the address space corresponding to the narrow address space assumed by the old microprocessor (hereinafter, this address space is referred to as “conventional space”) A stack area and a program area are provided, and an address space portion excluding the conventional space portion of the wide address space that can be handled by the new microprocessor (hereinafter, this address space portion is referred to as an "extended space portion, The stack area and the program area are also provided in the section and the extension space section.

However, when the stack area is provided in each of the conventional space portion and the extended space portion, even if a stack construction instruction is prepared, the reconstruction of the return address and the like are not performed normally, so that the program can proceed. The above may occur.

Therefore, in the following, a stack region is provided in each of the conventional space portion and the extended space portion, and
An embodiment devised so that a normal progress of a program is guaranteed will be described.

FIG. 6 is a diagram showing a fourth embodiment of the microprocessor of the present invention.

Of the circuits and the like shown in FIG. 6, the same circuits and the like as the circuits and the like shown in FIG. 1 are denoted by the same reference numerals, and redundant description will be omitted.

FIG. 6 shows a memory 35 having a 24-bit address space. Of the address space of this memory 35, an address "000" in hexadecimal notation is shown.
000 ”to address“ 00FFFF ”is the conventional space portion 36, and the address“ 01000 ”in hexadecimal notation.
The area from “0” to the address “FFFFFF” is the extended space part 37. Further, both a stack area and a program area are provided in the conventional space portion 36 and the extended space portion 37, respectively.

The microprocessor 70 has a page in the address space (the upper 8 bits of the 24-bit address).
Is provided, and when an instruction involving access to the stack area is executed, the value of the page register 71 is set to the page in which the stack area provided in the extension space 37 is provided. Shall be shown.

When an instruction other than the old branch instruction among the conventional instructions involving access to the stack area is executed, the microprocessor 70 basically stores the address space to which the address storing the instruction belongs. Access to the stack area provided in the section. Further, the microprocessor 70 is provided with a new instruction that can access the stack area provided in the extended space portion 37 regardless of where the instruction is located.

When the old branch instruction is decoded by the fetch / decode circuit 13, the old branch instruction execution circuit 15 stores the old branch instruction in the stack area provided in the address space to which the address indicated by the value of the program counter 14 belongs. The bit return address is accumulated, the 24-bit return address is stored in the register 16, and the value of the program counter 14 is updated to a value indicating the branch destination address.

Further, the microprocessor 70 is provided with a space selection register 72, and the former branch instruction execution circuit 15 has an address space portion where a stack area in which a 16-bit return address is stacked is provided. In the case of the conventional space portion 36, the value of the space selection register 72 is set to the value “0”, and in the case of the extension space portion 37, the value of the space selection register 72 is set to the value “1”.

The bus control circuit 11 is provided with a selector 111. The selector 111 includes a hexadecimal value “00” indicating a page corresponding to the conventional space portion 36 and a value indicated by the page register 71. Is selected according to the value of the space selection register 72. The value selected by the selector 111 is stored in the stack construction instruction execution circuit 17.
When the 16-bit return address is extracted from the stack area, the bus control circuit 11 indicates the page (upper 8 bits of the address) in which the stack area on which the 16-bit return address is stacked is provided. Used as a thing.

As a result, the 16-bit return address is normally taken out from the stack area indicated by the value of the space selection register 72, and the return address is normally reconstructed, whereby the normal program progress is guaranteed. You.
In the present embodiment, the branch destination address at the time of occurrence of an interrupt always belongs to the conventional space portion 36, whereas the stack construction instruction execution circuit 17 provides a 24-bit return address in the extension space portion 37. Stack area. Then, when returning from the branch destination to the branch source, the new instruction is used and the stack area provided in the extended space portion 37 is accessed, so that the program proceeds normally.

FIG. 7 is a diagram showing a fifth embodiment of the microprocessor of the present invention.

Of the circuits and the like shown in FIG. 7, the same circuits and the like as the circuits and the like shown in FIGS. 3 and 6 are denoted by the same reference numerals, and redundant description will be omitted.

The microprocessor 80 shown in FIG. 7 is provided with a space judgment circuit 81. When the old branch instruction is decoded by the fetch / decode circuit 13, the space judgment circuit 81 indicates the program counter 14. It is determined whether the address space to which the return address belongs is a conventional space part or an extended space part. If it is determined that the address space part is a conventional space part, a value “0” is output from the space determination circuit 81, and If it is determined that it is a space portion, a value “1” is output. As described above, when the old branch instruction is decoded by the fetch / decode circuit 13, the determination circuit 1
Reference numeral 32 determines whether or not the next instruction to be executed, which is fetched by the prefetch circuit 51, is a stack construction instruction. When it is determined that the instruction is a stack construction instruction, the determination circuit 132 outputs a value “1”, and when it is determined that the instruction is not a stack construction instruction, a value “0” is output.

When the old branch instruction is decoded by the fetch / decode circuit 13, as described above, the old branch instruction execution circuit 52
As a result, the return address of the number of bits according to the determination result by the determination circuit 132 is stacked on the stack area. Also,
As described below, the stack area where the return address is stacked by the old branch instruction execution circuit 52 is selected from the two stack areas provided in the memory 35 by the bus control circuit 1.
Selected by 1.

The bus control circuit 11 includes a NOR gate 11
2 and a selector 113, and a NOR gate 1
The output of the determination circuit 132 and the output of the space determination circuit 81 are input to 12. Therefore, from the NOR gate 112,
The instruction to be executed next is not a stack construction instruction, and
The value “1” is output only when the address space to which the return address belongs is the conventional space, and otherwise the value “0” is output.

The output of the NOR gate 112 is supplied to the selector 113
To the conventional space portion 36 by the selector 113.
Is one of the hexadecimal value “00” indicating the page corresponding to
The selection is made according to the output of the OR gate 112. While the value selected by the selector 111 shown in FIG. 6 is used when extracting the return address from the stack area, the value selected by the selector 113 It is used by the bus control circuit 11 to select a stack area when the data is stacked on the stack area.

As described above, the return address having an appropriate number of bits is stacked on the appropriate stack area, thereby guaranteeing the normal progress of the program.

[0069]

As described above, according to the microprocessor of the present invention, even when an old branch instruction is executed at a position on the program which cannot be predicted by the programmer, the program can be normally executed. can do.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of a microprocessor of the present invention.

FIG. 2 is a diagram illustrating a data structure constructed in a stack area by a microprocessor according to the first embodiment.

FIG. 3 is a diagram showing a second embodiment of the microprocessor of the present invention.

FIG. 4 is a diagram showing a third embodiment of the microprocessor of the present invention.

FIG. 5 is a diagram illustrating a structure of data stacked in a stack area by a microprocessor according to a third embodiment.

FIG. 6 is a diagram showing a fourth embodiment of the microprocessor of the present invention.

FIG. 7 is a diagram showing a fifth embodiment of the microprocessor of the present invention.

[Explanation of symbols]

 10, 50, 60, 70, 80 Microprocessor 11 Bus control circuit 12 Interrupt acceptance circuit 14 Program counter 15, 52, 62 Old branch instruction execution circuit 16 Register 17, 63 Stack construction instruction execution circuit 20 Interrupt circuit 30, 35 Memory 31 Program area 32 Stack area 36 Conventional space part 37 Extended space part 40 Bus 51 Prefetch circuit 61 Stack pointer 71 Page register 72 Space selection register 81 Space determination circuit 111, 113 Selector 112 NOR gate 121 AND gate 131, 132 Determination circuit

Claims (5)

[Claims] 1. A microprocessor connected to a memory having a stack area in which data is stacked and a program area in which a plurality of instructions are stored, and sequentially fetching and executing the instructions. A branch instruction execution circuit that executes a branch instruction that branches to a branch destination address on the program area; and a determination circuit that determines whether the instruction stored at the branch destination address is a predetermined stack construction instruction. The branch instruction execution circuit, relative to the stack area, depending on whether or not the instruction stored at the branch destination address is a predetermined stack construction instruction by the determination circuit, A return address having a long word length or a return address having a relatively short word length. Sessa. 2. The memory according to claim 1, wherein the memory has an address space including two address space portions each provided with both the program area and the stack area, and the branch instruction execution circuit includes the determination circuit. According to whether or not the instruction stored at the branch destination address is determined to be a predetermined stack construction instruction, a return address having a relatively long word length is set to an address at which the stack construction instruction exists. 2. The method according to claim 1, wherein a return address having a relatively short word length is stored in a stack area provided in an address space where the branch instruction exists.
The microprocessor as described. 3. A microprocessor which is connected to a memory having a stack area for storing data and a program area for storing a plurality of instructions, and sequentially fetches and executes the instructions. A branch instruction execution circuit that executes a branch instruction that branches to a branch destination address; and a stack construction instruction execution circuit that executes a stack construction instruction that reconstructs a return address stacked in a stack area by the branch instruction execution circuit. The branch instruction execution circuit stores a return address having a relatively short word length in the stack area, and stores a return address having a relatively long word length. The return address stacked in the stack area and having a relatively short word length is converted by the branch instruction execution circuit. Microprocessor, wherein the presence has been relatively word length is to change the long return address. 4. The memory according to claim 1, wherein the memory has an address space including two address space portions each provided with both the program area and the stack area. A return address having a short word length is stacked on a stack area provided in the address space where the branch instruction exists, and space portion information for specifying the address space where the branch instruction exists from the two address space portions is stored. And a return address having a relatively long word length is stored. The stack construction instruction execution circuit is provided in an address space portion specified by the space portion information stored by the branch instruction execution circuit. The return address having a relatively short word length, which is stacked in the stack area, is read, and The microprocessor of claim 3, wherein a but the stack area provided in the address space portion existing, relatively word length stored by said branch instruction execution circuit is intended to gain long return address. 5. The microprocessor according to claim 1, further comprising an interrupt receiving circuit that receives the branch instruction and causes the branch instruction execution circuit to execute the received branch instruction preferentially.