JP3678330B2 - Microprocessor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a microprocessor that fetches and executes instructions.
[0002]
[Prior art]
With the recent development of LSI technology, the capacity of memory has been increased, and accordingly, a new type microprocessor capable of handling a wide address space has been developed. These new microprocessors must be compatible so that software that is a legacy asset developed for older microprocessors that can handle only a narrow address space can be used. Is desired. Of course, it is also desired to have a so-called extensibility so that a wide address space can be freely used.
[0003]
Under such a demand, the conventional new microprocessor is defined to correspond to the old instruction that is used in the software for the old microprocessor based on the narrow address space and the old instruction. In addition, new instructions are provided on the premise of a wide address space. Branch instructions such as call instructions and restart instructions that accumulate return addresses on the stack and branch to branch destination addresses are stored in a narrow address space on the stack. A corresponding old branch instruction in which a return address having a short word length is stacked and a new branch instruction in which a return address having a long word length corresponding to a wide address space is stacked are prepared on the stack.
[0004]
When such a branch by an old branch instruction is performed, when returning from the branch destination to the branch source after the branch, it is necessary to return to the branch source based on a return address having a short word length. For this reason, in order for the program to proceed normally after execution of the old branch instruction, the positional relationship between the branch destination and the branch source must satisfy a predetermined limiting condition. The program is designed so that the old branch instruction is executed at a position that satisfies the limiting condition.
[0005]
[Problems to be solved by the invention]
However, the old branch instruction is not only executed at the position planned by the programmer on the program, but the peripheral circuit designed on the assumption of the old branch instruction is used at a position on the program where the programmer cannot predict. May be executed.
[0006]
For example, when an old branch instruction is interrupted and executed preferentially by an interrupt circuit, or when an instruction on a program is rewritten to an old branch instruction by a debugging device, the location where the interrupt occurs or the instruction The position where the rewriting is performed cannot be predicted by the programmer. For this reason, there is a problem that normal progress of the program is not guaranteed.
[0007]
Moreover, it may be difficult or impossible to change the design of a peripheral circuit designed on the assumption of the old branch instruction on the basis of the new branch instruction.
[0008]
SUMMARY OF THE INVENTION In view of the above circumstances, the present invention provides a microprocessor that allows a program to proceed normally even when an old branch instruction is executed at a position on the program where the programmer cannot predict. Objective.
[0009]
[Means for Solving the Problems]
A first microprocessor of the present invention that achieves the above object is a microprocessor that is connected to a memory having a stack area in which data is stacked and a program area in which a plurality of instructions are stored, and sequentially fetches and executes instructions. ,
A branch instruction execution circuit that executes a branch instruction that branches to a branch destination address in the program area by accumulating a return address in the stack area;
A determination circuit that determines whether or not the instruction stored in the branch destination address is a predetermined stack construction instruction;
The branch instruction execution circuit returns a relatively long word length to the stack area depending on whether the determination circuit determines that the instruction stored at the branch destination address is a predetermined stack construction instruction. The address or the return address having a relatively short word length is stacked.
[0010]
In the first microprocessor of the present invention, the memory has an address space composed of two address space portions each provided with both the program area and the stack area.
A return address having a relatively long word length depending on whether the branch instruction execution circuit determines that the instruction stored in the branch destination address is a predetermined stack construction instruction by the determination circuit. Are stacked in the stack area provided in the address space portion where the stack construction instruction exists, or the return address having a relatively short word length is stacked in the stack area provided in the address space portion where the branch instruction exists. Is preferred.
[0011]
The second microprocessor of the present invention that achieves the above object is a microprocessor that is connected to a memory having a stack area in which data is stacked and a program area in which a plurality of instructions are stored, and sequentially fetches and executes instructions. ,
A branch instruction execution circuit that executes a branch instruction that loads a return address in the stack area and branches to a branch destination address;
A stack construction instruction execution circuit for executing a stack construction instruction for reconstructing the return address stacked in the stack area by the branch instruction execution circuit;
A branch instruction execution circuit accumulates a return address having a relatively short word length in the stack area, and stores a return address having a relatively long word length. A return address having a relatively short word length accumulated in the area is changed to a return address having a relatively long word length stored by the branch instruction execution circuit.
[0012]
Here, “save the return address having a relatively long word length” does not limit the storage location, and may be stored in the branch instruction execution circuit, and may be stored in a register in the microprocessor. May be stored in this register or the like, or may be stored in the stack area. Further, the entire return address having a relatively long word length may be stored, or only a portion exceeding the return address having a relatively short word length may be stored.
[0013]
In the second microprocessor of the present invention, the memory has an address space composed of two address space portions each provided with both the program area and the stack area.
The branch instruction execution circuit stacks a return address having a relatively short word length on a stack area provided in the address space part where the branch instruction exists, and converts the address space part where the branch instruction exists into two address space parts. In addition to storing the spatial part information specified from inside, the return address having a relatively long word length is stored,
The stack construction instruction execution circuit reads a return address having a relatively short word length loaded in a stack area provided in an address space portion specified by the space portion information stored by the branch instruction execution circuit, and It is preferable that the return area having a relatively long word length stored by the branch instruction execution circuit is stacked in the stack area provided in the address space portion where the stack construction instruction exists.
[0014]
It is desirable that the first and second microprocessors of the present invention include an interrupt acceptance circuit that accepts the branch instruction and causes the branch instruction execution circuit to preferentially execute the accepted branch instruction.
[0015]
This interrupt acceptance circuit may be a circuit provided with a circuit that prohibits acceptance of branch instructions until the return address is appropriately stacked in the stack area.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described.
[0017]
FIG. 1 is a diagram showing a first embodiment of a microprocessor of the present invention.
[0018]
The microprocessor 10 can handle a 24-bit address space, and is compatible with an old microprocessor based on a 16-bit address space. The microprocessor 10 is connected to the interrupt circuit 20 and the memory 30 via the bus 40. The memory 30 has a 24-bit address space, and a program is stored in the address space. It has a program area 31 and a stack area 32 where data is stacked.
[0019]
In this microprocessor 10, the stack area 32 is loaded with a 16-bit return address and branched to a branch address, and the 16-bit return address accumulated in the stack area 32 is converted into a 24-bit return address. A stack construction instruction to be changed is prepared, and the interrupt circuit 20 outputs an interrupt request signal of logic “1” to the microprocessor 10 as necessary, and also sends an old request to the microprocessor 10 via the bus 40. A branch instruction is output.
[0020]
The microprocessor 10 includes a bus control circuit 11 and an interrupt reception circuit 12, and data input / output via the bus 40 is controlled by the bus control circuit 11. An AND gate 121 is connected to the interrupt reception circuit 12, and an interrupt request signal from the interrupt circuit 20 is input to the AND gate 121. The interrupt reception circuit 12 receives a logic “1” signal from the AND gate 121 and receives data from the interrupt circuit 20 to the bus control circuit 11 by reading data from the memory. Is also given priority.
[0021]
Further, the microprocessor 10 is provided with a fetch / decryption circuit 13 and a program counter 14. The fetch / decode circuit 13 fetches an instruction from the program area 31 via the bus 40 and the bus control circuit 11. Alternatively, an instruction from the interrupt circuit 20 is fetched. Thereafter, the fetch / decode circuit 13 decodes the instruction and sends a signal instructing the operation of each part to each part of the microprocessor. When the old branch instruction is decoded, the fetch / decode circuit 13 outputs an interrupt disable signal of logic “0” to the AND gate 121 until the instruction stored in the branch destination address is fetched after the decoding. As a result, the output of the AND gate 121 becomes a logic “0” signal that is the logical sum of the interrupt request signal and the interrupt prohibition signal, and this output is input to the interrupt reception circuit 12 to prohibit the interrupt. Each time an instruction is fetched by the fetch / decryption circuit 13, the count value of the program counter 14 is updated to a value indicating the next address on the program area 31 where the fetched instruction is stored.
[0022]
The microprocessor 10 includes an old branch instruction execution circuit 15 and a register 16. When the old branch instruction is decoded by the fetch / decode circuit 13, the old branch instruction execution circuit 15 The return address is recognized based on the count value of 14, and a 16-bit return address is stacked in the stack area 32 via the bus 40 and the bus control circuit 11 as shown in FIG. A 24-bit return address is stored. Thereafter, the old branch instruction execution circuit 15 updates the count value of the program counter 14 to the count value indicating the branch destination address, and the fetch / decryption circuit 13 determines the bus 40 and the bus based on the count value of the program counter 14. An instruction is fetched from the branch destination address on the program area 31 via the control circuit 11.
[0023]
The fetch / decryption circuit 13 includes a determination circuit 131. The determination circuit 131 determines whether the instruction fetched after the old branch instruction by the fetch / decryption circuit 13 is a stack construction instruction. .
[0024]
Further, the microprocessor 10 is provided with a stack construction instruction execution circuit 17. The stack construction instruction execution circuit 17 is an instruction fetched by the determination circuit 131 after the old branch instruction by the fetch / decoding circuit 13. Is received from the stack area 32 through the bus 40 and the bus control circuit 11, and the 24-bit return address stored in the register 16 is obtained. Then, a 24-bit return address is loaded in the stack area 32 via the bus 40 and the bus control circuit 11. As a result, the return address stacked in the stack area 32 is reconstructed.
[0025]
FIG. 2 is a diagram illustrating a data structure constructed in the stack area by the microprocessor according to the first embodiment.
[0026]
Data is stacked in the stack area 32 from the top to the bottom of the figure. The stack area 32 is loaded with a parameter D10 used at a branch destination before the return address is loaded by the microprocessor 10 shown in FIG.
[0027]
FIG. 2A shows a data structure that is constructed when the return address is stacked by the old branch instruction execution circuit 15 shown in FIG. 1, and the eighth bit of the return address is next to the parameter D10. 8 bits D20 from the 15th bit to the 15th bit are stacked, and then, 8 bits D30 from the 0th bit to the 7th bit of the return address are stacked.
[0028]
FIG. 2B shows a data structure that is constructed when the return address is restacked by the stack construction instruction execution circuit 17 shown in FIG. 1, and the 16th of the return address is next to the parameter D10. 8 bits D40 from the bit to the 23rd bit are stacked, then 8 bits D50 from the 8th bit to the 15th bit of the return address are stacked, and then from the 0th bit of the return address D60 for 8 bits up to the 7th bit is stacked.
[0029]
These data structures are ultimately selected by the microprocessor depending on whether or not a stack construction instruction exists at the branch destination, but the branch destination where the program is branched by the old branch instruction is Regardless of the position where the branch occurs on the program, the position is predetermined by the programmer. Therefore, the programmer can stack the 24-bit return address in the microprocessor by writing the stack construction instruction to the branch destination that is scheduled when an interrupt occurs or the like. Regardless, the normal progress of the program is guaranteed.
[0030]
In the first embodiment, a 24-bit return address is stored in the register. However, the microprocessor of the present invention has a return address with a relatively short word length among return addresses with a relatively long word length. Only the part exceeding the limit may be stored.
[0031]
Hereinafter, other embodiments of the microprocessor of the present invention will be described. Circuits similar to those shown in FIG. 1 are denoted by the same reference numerals, and redundant description will be omitted.
[0032]
FIG. 3 is a diagram showing a second embodiment of the microprocessor of the present invention.
[0033]
The microprocessor 50 is provided with an old branch instruction that loads the return address into the stack area 32 and branches to a branch destination, and a stack construction instruction that is a kind of indicator.
[0034]
The microprocessor 50 is provided with a prefetch circuit 51. During execution of an instruction decoded by the fetch / decryption circuit 13 by the prefetch circuit 51, an instruction to be executed next to the instruction is a program. Based on the count value of the counter 14, the instruction fetched through the bus 40 and the bus control circuit 11 and the execution of the currently executed instruction is completed, and the instruction fetched into the prefetch circuit 51 is sent to the fetch / decryption circuit 13. .
[0035]
Further, the fetch / decryption circuit 13 is provided with a determination circuit 132. When the old branch instruction is decrypted by the fetch / decryption circuit 13, the determination circuit 132 is fetched into the prefetch circuit 51. It is determined whether the instruction to be executed is a stack construction instruction.
[0036]
Further, the microprocessor 50 is provided with an old branch instruction execution circuit 52. When the old branch instruction is decoded by the fetch / decryption circuit 13, the old branch instruction execution circuit 52 sets the count value of the program counter 14. Based on this, the return address is recognized. When the determination circuit 132 determines that the instruction fetched by the prefetch circuit 51 is a stack construction instruction, the old branch instruction execution circuit 52 passes through the stack area via the bus 40 and the bus control circuit 11. A 24-bit return address is stacked in 32, and if it is determined that the instruction is not a stack construction instruction, a 16-bit return address is stacked. Thereafter, the old branch instruction execution circuit 52 updates the count value of the program counter 14 to a value indicating the branch destination address.
[0037]
As a result of each operation described above, as in the first embodiment, a 24-bit return address or a 16-bit return address is obtained depending on whether the instruction stored in the branch destination address is a stack construction instruction, respectively. The program is stacked in the stack area 32, and the normal progress of the program is guaranteed.
[0038]
In the second embodiment, the determination circuit is provided in the fetch / decryption circuit. However, the determination circuit according to the present invention may be a circuit independent of the fetch / decryption circuit.
[0039]
FIG. 4 is a diagram showing a third embodiment of the microprocessor of the present invention.
[0040]
Similar to the microprocessor 10 shown in FIG. 1, the microprocessor 60 shown in FIG. 4 has the stack area 32 loaded with a 16-bit return address and branched to a branch address and the stack area 32. A stack construction instruction for changing a 16-bit return address to a 24-bit return address is prepared. However, the order in which the return addresses are stacked in the stack area 32 in the present embodiment is the reverse of the order in the first and second embodiments, as will be described below.
[0041]
The microprocessor 60 is provided with a stack pointer 61. The stack pointer 61 is obtained by stacking the last stacked data among the data stacked in the stack area 32 on the stack area 32. The stack area 32 is accessed via the bus 40 and the bus control circuit 11 on the basis of the address indicated by the stack pointer 61, and whenever the stack area 32 is accessed. The address indicated by the stack pointer 61 is updated.
[0042]
The microprocessor 60 includes an old branch instruction execution circuit 62. When the old branch instruction is decoded by the fetch / decryption circuit 13, the old branch instruction execution circuit 62 counts the count value of the program counter 14. The return address is recognized based on the above, and the 24-bit return address is stacked on the stack area 32 in order from the lower side, in the opposite direction to the first and second embodiments, and then the stack pointer 61 1 address is returned. As a result, as shown in FIG. 5 to be described later, a 16-bit return address is substantially stacked in the stack area 32. Thereafter, the old branch instruction execution circuit 62 updates the count value of the program counter 14 to a value indicating the branch destination address.
[0043]
Further, the microprocessor 60 is provided with a stack construction instruction execution circuit 63. Upon receiving a determination result by the determination circuit 131 that the instruction stored in the branch destination address is a stack construction instruction, the stack 60 The address indicated by the stack pointer 61 is advanced by one address by the construction instruction execution circuit 63. As a result, as shown in FIG. 5 to be described later, the 16-bit return address stacked in the stack area 32 is substantially changed to a 24-bit return address.
[0044]
FIG. 5 is a diagram showing the structure of data stacked in the stack area by the microprocessor of the third embodiment.
[0045]
Like the stack area shown in FIG. 2, the stack area 32 shown in FIG. 5 is loaded with data from the top to the bottom of the figure, and before the return address that is stacked in the reverse order of the first and second embodiments. Is loaded with a parameter D10.
[0046]
FIG. 5A shows the data structure after the return address is stacked by the old branch instruction execution circuit 62 shown in FIG. 4. The stack area 32 has the return address in order from the top of the figure. 8 bits D70 from the 0th bit to the 7th bit, 8 bits D80 from the 8th bit to the 15th bit of the return address, and 8 bits from the 16th bit to the 23rd bit of the return address As shown by the arrow in FIG. 5A, the stack pointer indicates an address where 8 bits D80 from the 8th bit to the 15th bit of the return address are stacked. For this reason, the 8-bit D90 from the 16th bit to the 23rd bit of the return address, which is stacked at the address earlier than the address indicated by the stack pointer, is ignored, so to speak, the stack area 32 is substantially In addition, a 16-bit return address is stacked.
[0047]
FIG. 5B shows a data structure after the stack construction instruction is executed by the stack construction instruction execution circuit 63 shown in FIG. As described above, since the stack construction instruction execution circuit 63 is a circuit that only operates the stack pointer, the data loaded in the stack area 32 is the same as that shown in FIG. Further, the stack pointer indicates an address in which D90 of 8 bits from the 16th bit to the 23rd bit of the return address is stacked, as indicated by an arrow in FIG. That is, the address indicated by the stack pointer moves from the position indicated by the arrow in FIG. 5A to the position indicated by the arrow in FIG. The address is changed to a 24-bit return address.
[0048]
Eventually, as in the first and second embodiments, in the third embodiment, a 24-bit return address or an instruction stored in the branch destination address depends on whether or not the instruction stored in the branch destination address is a stack construction instruction, respectively. A 16-bit return address is stacked in the stack area 32, and normal progress of the program is guaranteed.
[0049]
In the first and third embodiments, the stack construction instruction execution circuit reconstructs the return address only when the stack construction instruction is stored in the branch destination address. The stack construction instruction execution circuit may be one in which the return address is reconstructed regardless of the storage location of the stack construction instruction.
[0050]
In the above description, the embodiment in which one stack area and one program area are provided in the address space of the memory has been described. However, the embodiment has a wide compatibility with old microprocessors based on a narrow address space. When a new microprocessor capable of handling an address space is developed, two stack areas and two program areas are often provided. That is, of the wide address space that can be handled by the new microprocessor, the address space portion corresponding to the narrow address space assumed by the old microprocessor (hereinafter, this address space portion is referred to as the “conventional space portion”). A stack area and a program area are provided, and the address space portion excluding the conventional space portion of the wide address space that can be handled by the new microprocessor (hereinafter, this address space portion is referred to as the “extended space portion”). The stack area and the program area are also provided in the “address space portion”.
[0051]
However, when the stack area is provided in each of the conventional space portion and the extended space portion, even if the stack construction instruction is prepared, the return address is not reconstructed normally and the program progresses as described above. There is a case.
[0052]
Therefore, in the following, an embodiment will be described in which stack areas are provided in each of the conventional space portion and the extended space portion and the device is devised so as to ensure normal progress of the program.
[0053]
FIG. 6 is a diagram showing a fourth embodiment of the microprocessor of the present invention.
[0054]
Among the circuits shown in FIG. 6 and the like, the same circuits and the like as those shown in FIG.
[0055]
FIG. 6 shows a memory 35 having a 24-bit address space. Of the address space of this memory 35, addresses “000000” to “00FFFF” in hexadecimal notation are the conventional space portion 36. There is an extended space portion 37 from the address “010000” to the address “FFFFFF” in hexadecimal notation. Both the stack area and the program area are provided in the conventional space portion 36 and the extended space portion 37, respectively.
[0056]
The microprocessor 70 is provided with a page register 71 indicating a page of the address space (the upper 8 bits of the 24-bit address). When an instruction involving access to the stack area is executed, the page register A value of 71 indicates a page in which a stack area provided in the extended space portion 37 is provided.
[0057]
When an instruction other than the old branch instruction is executed among conventional instructions that accompany access to the stack area, the microprocessor 70 is provided in the address space portion to which the address storing the instruction belongs as a rule. Access the specified stack area. Further, the microprocessor 70 is provided with a new instruction that can access the stack area provided in the expansion space portion 37 regardless of the place where the instruction is arranged.
[0058]
When the old branch instruction is decoded by the fetch / decryption circuit 13, the old branch instruction execution circuit 15 returns 16 bits to the stack area provided in the address space portion to which the address indicated by the value of the program counter 14 belongs. The addresses are stacked, a 24-bit return address is stored in the register 16, and the value of the program counter 14 is updated to a value indicating the branch destination address.
[0059]
Further, the microprocessor 70 is provided with a space selection register 72, and the address space portion where the stack area where the 16-bit return address is stacked by the old branch instruction execution circuit 15 is provided is the conventional space portion. If it is 36, the value of the space selection register 72 is set to the value “0”, and if it is the extended space portion 37, the value of the space selection register 72 is set to the value “1”.
[0060]
The bus control circuit 11 is provided with a selector 111, which is one of a hexadecimal value “00” indicating a page corresponding to the conventional space portion 36 and a value indicated by the page register 71. Is selected according to the value of the space selection register 72. The value selected by the selector 111 is the stack area on which the 16-bit return address is stacked by the bus control circuit 11 when the stack construction instruction execution circuit 17 extracts the 16-bit return address from the stack area. Is used to indicate the page (the upper 8 bits of the address).
[0061]
As a result, a 16-bit return address is normally extracted from the stack area indicated by the value of the space selection register 72, and the return address is normally reconstructed, thereby ensuring normal program progress. In this embodiment, the branch destination address at the time of occurrence of an interrupt always belongs to the conventional space portion 36. On the other hand, the stack construction instruction execution circuit 17 is provided with a 24-bit return address in the extended space portion 37. Stack the stack area. Then, when returning from the branch destination to the branch source, a new instruction is used to access the stack area provided in the extended space portion 37, so that the program proceeds normally.
[0062]
FIG. 7 is a diagram showing a fifth embodiment of the microprocessor of the present invention.
[0063]
Among the circuits shown in FIG. 7 and the like, circuits and the like similar to those shown in FIGS. 3 and 6 are denoted by the same reference numerals, and redundant description is omitted.
[0064]
The microprocessor 80 shown in FIG. 7 includes a space determination circuit 81. When the old branch instruction is decoded by the fetch / decryption circuit 13, the space determination circuit 81 generates a return address indicated by the program counter 14. It is determined whether the address space portion to which it belongs is a conventional space portion or an extended space portion. If it is determined that the address space portion is a conventional space portion, the value “0” is output from the space determination circuit 81 and If it is determined that there is, the value “1” is output. Further, as described above, when the old branch instruction is decoded by the fetch / decryption circuit 13, the determination circuit 132 determines whether the instruction to be executed next, which is fetched by the prefetch circuit 51, is a stack construction instruction. Determine whether. When it is determined that the instruction is a stack construction instruction, the value “1” is output from the determination circuit 132, and when it is determined that the instruction is not a stack construction instruction, a value “0” is output.
[0065]
When the old branch instruction is decoded by the fetch / decryption circuit 13, as described above, the old branch instruction execution circuit 52 accumulates the return address of the number of bits corresponding to the determination result by the determination circuit 132 in the stack area. The stack area where the return address is stacked by the old branch instruction execution circuit 52 is selected by the bus control circuit 11 from two stack areas provided in the memory 35, as will be described below.
[0066]
The bus control circuit 11 includes a NOR gate 112 and a selector 113, and the output of the determination circuit 132 and the output of the space determination circuit 81 are input to the NOR gate 112. Therefore, the value “1” is output from the NOR gate 112 only when the next instruction to be executed is not a stack construction instruction and the address space part to which the return address belongs is the conventional space part, Otherwise, the value “0” is output.
[0067]
The output of the NOR gate 112 is input to the selector 113, and the selector 113 selects one of the hexadecimal value “00” indicating the page corresponding to the conventional space portion 36 and the value indicated by the page register 71. , Selected according to the output of the NOR gate 112. The value selected by the selector 111 shown in FIG. 6 is used when the return address is taken out from the stack area, whereas the value selected by the selector 113 has the return address set by the old branch instruction execution circuit 52. When stacked in the stack area, it is used for selection of the stack area by the bus control circuit 11.
[0068]
In this way, a return address having an appropriate number of bits is stacked in the appropriate stack area, thereby ensuring the normal progress of the program.
[0069]
【The invention's effect】
As described above, according to the microprocessor of the present invention, the program can proceed normally even when the old branch instruction is executed at a position on the program where the programmer cannot predict.
[Brief description of the drawings]
FIG. 1 is a diagram showing a first embodiment of a microprocessor according to the present invention.
FIG. 2 is a diagram showing a data structure constructed in a stack area by the microprocessor of the first embodiment.
FIG. 3 is a diagram showing a second embodiment of the microprocessor of the present invention.
FIG. 4 is a diagram showing a third embodiment of the microprocessor of the present invention.
FIG. 5 is a diagram illustrating a structure of data stacked in a stack area by the microprocessor according to the third embodiment.
FIG. 6 is a diagram showing a fourth embodiment of the microprocessor of the present invention.
FIG. 7 is a diagram showing a fifth embodiment of the microprocessor of the present invention.
[Explanation of symbols]
10, 50, 60, 70, 80 Microprocessor
11 Bus control circuit
12 Interrupt acceptance circuit
14 Program counter
15, 52, 62 Old branch instruction execution circuit
16 registers
17, 63 Stack construction instruction execution circuit
20 Interrupt circuit
30,35 memory
31 Program area
32 Stack area
36 Conventional space
37 Extended space
40 bus
51 Prefetch circuit
61 Stack pointer
71 page register
72 Space Select Register
81 Spatial determination circuit
111,113 selector
112 NOR gate
121 AND gate
131,132 judgment circuit

Claims (5)

In a microprocessor connected to a memory having a stack area where data is stacked and a program area where a plurality of instructions are stored, and sequentially fetching and executing instructions,
A branch instruction execution circuit that loads a return address in the stack area and executes a branch instruction that branches to a branch destination address on the program area;
A determination circuit for determining whether or not the instruction stored in the branch destination address is a predetermined stack construction instruction,
The branch instruction execution circuit is relatively worded in the stack area depending on whether or not the determination circuit determines that the instruction stored in the branch destination address is a predetermined stack construction instruction. A microprocessor characterized by accumulating return addresses having a long length or return addresses having a relatively short word length. The memory has an address space composed of two address space portions each provided with both the program area and the stack area;
The branch instruction execution circuit has a relatively long return address according to whether or not the determination circuit determines that the instruction stored in the branch destination address is a predetermined stack construction instruction. Are stacked in the stack area provided in the address space portion where the stack construction instruction exists, or the return address having a relatively short word length is stacked in the stack area provided in the address space portion where the branch instruction exists. 2. The microprocessor according to claim 1, wherein the microprocessor is a memory. In a microprocessor connected to a memory having a stack area where data is stacked and a program area where a plurality of instructions are stored, and sequentially fetching and executing instructions,
A branch instruction execution circuit for executing a branch instruction for branching to a branch destination address by accumulating a return address in the stack area;
A stack construction instruction execution circuit for executing a stack construction instruction for reconstructing a return address stacked in the stack area by the branch instruction execution circuit;
The branch instruction execution circuit accumulates a return address having a relatively short word length in the stack area, and stores a return address having a relatively long word length,
The stack construction instruction execution circuit changes a return address with a relatively short word length accumulated in the stack area to a return address with a relatively long word length stored by the branch instruction execution circuit. A microprocessor characterized by that. The memory has an address space composed of two address space portions each provided with both the program area and the stack area;
The branch instruction execution circuit stacks a return address having a relatively short word length in a stack area provided in an address space part where the branch instruction exists, and the address space part where the branch instruction exists exists in the two address space parts. In addition to storing the spatial part information specified from within, the return address having a relatively long word length is stored,
The stack construction instruction execution circuit reads a return address having a relatively short word length stacked in a stack area provided in an address space portion specified by the space portion information stored by the branch instruction execution circuit, 4. The micro of claim 3, wherein a stack area provided in an address space where the stack construction instruction exists is loaded with a return address having a relatively long word length stored by the branch instruction execution circuit. Processor. 4. The microprocessor according to claim 1, further comprising an interrupt acceptance circuit that accepts the branch instruction and causes the branch instruction execution circuit to preferentially execute the accepted branch instruction.

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