JPH11327869A - Operation terminal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an operation terminal by which a circuit configuration for outputting voice is simplified. SOLUTION: Prescribed monitor display is executed with a display device based on stored display information and also voice is outputted based on stored voice data in an operation terminal. The operation terminal is provided with a voice buffer memory 13 storing voice data respectively alternately in accordance with the number of output channels, a voice control means 14 reading voice data for every channel, which is stored in the voice buffer memory 13, and outputting it and a D/A converting circuit 15 for distributing voice data received from the voice control means 14 to the output channels and outputting voice.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an operation terminal for providing voice guidance using voice data.

[0002]

2. Description of the Related Art FIG. 8 is a block diagram showing an internal configuration of a conventional monitor device. In the figure, 101 is a monitor device as an operation terminal, 102 is a CPU that controls the entire monitor device 101, and 103 is a CPU 1
ROM that is connected to the bus 02 and stores programs.
04 is a RAM for temporarily storing the operation results during the program, etc. 105 is a normal ROM or flash ROM
A monitor data memory 106 in which the contents to be displayed on the display are stored in advance; 106 is a VRAM that can be accessed from both the CPU 102 and the display controller 107 via an address bus and a data bus. It has two systems of control signals such as a read enable signal and a write enable signal. A display controller 107 generates a signal for the display device 109. The display controller 107 has characteristics matching the type of the display device 109 to be used, and the characteristics are determined by the display timing of the display device 109 or the bus configuration. Reference numeral 108 denotes a signal actually required for the display device 109, for example, RG representing the configuration of each color of red, green, and blue
A display device interface circuit (hereinafter, referred to as a display I / F) 109 for generating a B signal or the like;
A display device 110 for displaying an image based on the signal output from the display device 8; a key input I / F 110 for notifying an event to the CPU 102 of the monitor device 101 when a key input is generated from the keyboard 111; A communication I / F 20 that communicates with the programmable controller 20 is a programmable controller connected to the monitor device 101.

FIG. 9 is a schematic diagram showing a configuration when monitor data as contents (display screen, monitor conditions, etc.) to be displayed in the monitor data memory 105 is stored. In the figure, reference numeral 30 denotes a tool for creating monitor data, which is usually a personal computer or the like. 31 is a drawing of a fixed portion of the screen to be displayed on the monitor device 101 on the personal computer 30, and a monitor condition of the display unit which is a variable portion;
S / W package for setting the device number of the sequencer storing the calculation result to be monitored, etc.
Reference numeral 2 denotes, for example, a ROM writer for copying monitor data created by the personal computer 30 and the S / W package 31 to the monitor data memory 105. The monitor data memory 105, in which the created monitor data is copied using the ROM writer 32, is attached to the monitor device 101. Alternatively, when the monitor data memory 105 is configured by a flash ROM, the monitor data is monitored using communication. By transferring the data, the monitor device 101 displays a monitor image on the display based on the contents of the monitor data memory 105.

FIG. 10 is a diagram showing the contents of monitor data stored in the monitor data memory 105. As shown in the figure, the monitor data includes a head address information header 50 for storing information relating to the configuration of the entire monitor data memory, canvas graphic information 51 for storing what graphic is to be displayed on the display device 109, and a programmable controller. 20, the monitor condition setting information 52 indicating which device to monitor, the text canvas setting information 53 which is information of characters displayed on each screen, and other auxiliary function information 54.

Here, the head address information header 50 is
The total size of the stored monitor data memory 105, the canvas screen data information header 51, the monitor condition setting information 52, and the text canvas setting information 5
3. It is composed of addresses and the like indicating the positions where the respective screen data such as the auxiliary function information 54 are stored.

The canvas graphic information 51 includes a canvas graphic information header 51a in which the total number of screens and the head address of the canvas graphic for each screen are stored. A part that indicates the type of figure such as a rectangle, a part that indicates the type of line such as a thin line, a thick line, or a dashed line, a part that indicates a color, and coordinates indicating where to place the figure on the screen. Stores canvas figure data 51b constituting a campus figure for one screen to be displayed by gathering. In the canvas graphic information 51, data for one screen is configured by collecting a plurality of graphic types, line types, colors, and coordinates.

The monitor condition setting information 52 includes a number of screens for which monitor conditions are set, and a head address storage 52 for storing monitor condition setting information 52b for each screen.
a, and thereafter, a portion indicating the type of monitor such as a numerical display, a character string display, and a component display for each screen, a display position, and a monitor timing portion indicating timing for referring to the device of the programmer controller. The monitor condition setting information 52b corresponding to each screen is stored. In the monitor condition setting information 52b, data for one screen is configured by collecting a plurality of monitor types, display positions, and monitor timings.

The text canvas setting information 53 includes a text canvas setting information header 53 which stores the number of screens on which the text canvas is set and the head address of the text canvas data 53b for each screen.
a, and thereafter, text canvas data 53b composed of the number of characters of the text, the display position, and the character string code
Is stored. Note that canvas text data 5
3b, data for one screen is configured by collecting a plurality of text characters, display positions, and character string codes.

The auxiliary function information 54 includes an auxiliary function information header 54a in which the set auxiliary function start addresses are stored, followed by report data 54b as conditions for operating the respective auxiliary functions, and announcement data. 54c is stored.

[0010] The monitor data shown in FIG.
The monitor data is created by operating the S / W package 31 for creating monitor data on the personal computer 30 or the like. The data to be set at this time is a basic graphic portion to be displayed on the display device 109 and a character to be displayed therein, or information of a device to be connected to the programmable controller and to monitor a device inside the programmable controller. Is displayed, or the contents of a device to be changed in response to a key input are set.

The data created as described above is transferred from the personal computer 30 or the like to the ROM writer 32 by a serial I / F such as RS232C as shown in FIG.
Writer 32 writes data to monitor data memory 105. Normally, the monitor data memory 105 is a ROM
And the like, and by writing data to the monitor data memory 105, the monitor data is stored in the ROM. By mounting the ROM on a monitor device, a device of the programmable controller can be monitored or a key can be input on a screen created by a user.

Next, the operation of the conventional operation terminal will be described with reference to FIG. The monitor device 1
01 is connected to the programmable controller 20;
The case of monitoring the programmable controller 20 will be described. In the monitor device 101, the CPU 1
02 executes calculation and display processing according to a microprogram stored in the ROM 103 in advance. At the time of display processing, the CPU 102 sequentially reads out the monitor data stored in the monitor data memory 5 and, based on the monitor data, collects data to be monitored based on the communication I / F 11.
And communicates with the programmable controller 20 via the CPU 2 to read out the contents of the device in which the calculation result in the programmable controller 20 is stored from the programmable controller 20 based on the monitor condition setting information 52 in the monitor data. Is stored in the work RAM 4.

Thereafter, the CPU 102 obtains a fixed display portion for one screen based on the canvas graphic information 51 and the text canvas setting information 53 stored in the monitor data, and reads the device from the work RAM 104 as a variable display portion. Of the VRAM 106
Write to. Then, the display controller 107
The U102 reads the data written on the VRAM 106 and outputs the data to the display I / F 108. Display I / F108
Converts the signal into an output suitable for the characteristics of the display device 109 and outputs the signal to the display device 109. For example, in the case of an LCD, a voltage and a current are converted to a level corresponding to the used LCD, and a display device 109 having an RGB input, such as a CRT, is converted into an RGB signal and output, thereby outputting a predetermined signal. Display result of monitor device 109
To be displayed.

When an interrupt is generated to the CPU 102 through the key input I / F 110 by a key input from the keyboard 111, the internal device information of the programmable controller 20 is determined based on the device number specified by the monitor data. To change.

Next, a description will be given of a monitor device capable of outputting sound. FIG. 11 is a block diagram of a display for enabling conventional two-channel audio output. In the figure, the same reference numerals as those in FIG. 8 indicate the same or corresponding components. An audio buffer memory 113 temporarily stores audio data, an audio buffer memory 114 generates an address of the memory of the audio buffer memory 113, extracts audio data from the audio buffer memory 114, and stores data read from the memory in a predetermined manner. An audio control circuit 115 converts the serial data output from the audio control circuit 114 into analog data one by one in synchronism with the clock of the analog signal. A reference numeral 116 denotes a sampling frequency included in the analog data. This is a filter circuit that cuts off the above frequency components. Note that FIG.
, The audio buffer memories 113a, 113b,
Voice control circuits 114a and 114b, D / A conversion circuit 11
5a, 115b and filter circuits 116a, 116b
Due to the 2ch audio output, two each are provided.

Next, the operation in the case where the conventional two-channel audio output is provided will be described. The CPU 2 writes the audio data stored in the monitor data memory 105 in advance into the audio buffer memory 113 and outputs a sounding start signal to the audio control circuit 114 when the conditions for the audio utterance are satisfied. The audio control circuit 114 counts the audio clock signal, sequentially reads out the audio clock signal from the audio buffer memory 113 in accordance with the timing, converts the serial clock into serial data, and outputs the serial data to the D / A conversion circuit 115.

The D / A conversion circuit 115 sequentially converts the input digital value into analog data, and outputs the analog data to the filter circuit 116. In the filter circuit 116, frequency components higher than a predetermined sampling frequency are cut,
Output to an output device such as a speaker. In order to realize 2-channel audio output, two audio control circuits 113a and two audio buffer memories 112 are prepared, and the same processing is performed in each circuit.

[0018]

The conventional operation terminal is configured as described above, and requires an audio buffer memory, an audio control circuit, and a D / A conversion circuit corresponding to an output channel. There are problems that the circuit configuration becomes complicated and that the manufacturing cost for each circuit increases. In addition, there has been a problem that the circuit mounting area increases with the complexity of the circuit configuration. Further, there is another problem that the amount of audio data stored in the audio buffer memory for outputting audio is enormous, a relatively large audio buffer memory is required, and the manufacturing cost is increased. .

The present invention has been made to solve such a problem, and a first object of the present invention is to provide an operation terminal for simplifying a circuit configuration for outputting audio. A second object is to reduce the amount of audio data stored in the audio buffer memory.

[0020]

According to the present invention, a predetermined monitor display is performed via a display device based on the stored display information, and the operation terminal outputs a sound based on the stored sound data. An audio buffer memory for alternately storing the audio data according to the number of channels, audio control means for reading and outputting audio data for each channel stored in the audio buffer memory, And a conversion circuit for distributing the received audio data to output channels and outputting audio.

The audio data stored in the audio buffer memory is stored in the stored buffer memory with a continuous address number.

Further, the audio control means, when generating an address for accessing the audio buffer memory,
The output range of the output bit in the counter is changed and output as an address, and the increment number of the counter is changed according to the number of output channels.

The data stored in the audio buffer memory is stored in a phonetic character string format.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 is a block diagram of an operation terminal according to the present invention.
In the figure, 1 is a monitor device, 2 is a CPU for controlling the whole monitor device 1, 3 is a ROM connected to a bus of the CPU 2 and stores a program, 4 is a RAM for temporarily storing an operation result in the middle of the program, Reference numeral 5 denotes a monitor data memory which is normally constituted by a ROM or a flash ROM and stores in advance contents to be displayed on a display unit.
A VRAM that can be accessed from both the display controller 7 and the address bus via an address bus and a data bus, and has two systems of control signals such as an address bus, a data bus, a read enable signal, and a write enable signal. Reference numeral 7 denotes a display controller that generates a signal for the display device 9. The display controller 7 has characteristics matching the type of the display device 9 to be used, and the characteristics are determined by the display timing of the display device 9 or the bus configuration. Reference numeral 8 denotes a display device interface circuit (hereinafter, referred to as a display I / F) that generates signals necessary for the display device 9, for example, RGB signals representing the configuration of each color of red, green, and blue. A display device 10 for displaying an image based on a signal output from the / F8, a key input I / F 10 for notifying an event to the CPU 2 of the monitor device 1 when a key input occurs from the keyboard 11, and a monitor 12 for the monitor device 1. A communication I / F 13 for communicating with the target programmable controller 20 is an audio buffer memory for temporarily storing audio data, and 14 is an arbitration of the access right of the audio buffer memory 13 and an address of the memory. The audio data is generated and taken out from the audio buffer memory 114, and the data read out from the memory is synchronized with the clock and the data is read out. Voice control circuit which converts to Al data output, 15 D / A converting circuit for converting the serial data successively to the analog data output from the audio control circuit 14,
Reference numeral 16 denotes a filter circuit that cuts off frequency components equal to or higher than the sampling frequency included in the analog data, and reference numeral 20 denotes a programmable controller that is connected to the monitor device 1 and that is to be monitored.

FIG. 2 is a block diagram showing a detailed configuration of the voice control circuit. In the figure, reference numeral 141 denotes a frequency dividing circuit for dividing the audio clock signal OSCLK to generate a clock signal (LRCLK) indicating 1ch and 2ch, and 142 a counter for counting the audio clock signal OSCLK in accordance with a predetermined sampling frequency. A circuit 143 is an address generation circuit for generating an address of the audio buffer memory 13 in accordance with the count value of the counter circuit, and 144 is a CPU-side address, a voice-side address generated by the address generation circuit, and a read-out circuit. An arbitration circuit that outputs a write signal to the audio buffer memory in accordance with the timing, 145 is a gate circuit that controls the direction of the data bus of the audio buffer memory 13, and 146 is an audio circuit that outputs data read from the audio buffer memory 13. 1 in synchronization with the operating clock signal OSCLK. A shift register circuit for sending as Tsu preparative increments the serial data.

FIG. 3 is a diagram showing the concept of creating an address (OADR) created inside the address generation circuit 143. FIG. 4 is a timing chart showing the timing of the audio control circuit.

FIG. 5 is a diagram showing the contents of monitor data stored in the monitor data memory. As shown in the figure, the monitor data is composed of a head address information header 5 for storing information relating to the configuration of the entire monitor data memory.
0, canvas graphic information 51 for storing what graphic is to be displayed on the display device 9, monitor condition setting information 52 for monitoring which device of the programmable controller 20 is to be monitored, and text as information of characters to be displayed on each screen Canvas setting information 53, other auxiliary function information 5
Divided into four.

Here, the head address information header 50 is
The total size of the stored monitor data memory 5, the canvas screen data information header 51, the monitor condition setting information 52, the text canvas setting information 53,
It is composed of addresses and the like indicating the positions where the respective screen data such as the auxiliary function information 54 are stored.

The canvas graphic information 51 includes a canvas graphic information header 51a in which the total number of screens and the starting address of the canvas graphic for each screen are stored. A part that indicates the type of figure such as a rectangle, a part that indicates the type of line such as a thin line, a thick line, or a dashed line, a part that indicates a color, and coordinates indicating where to place the figure on the screen. Stores canvas figure data 51b constituting a campus figure for one screen to be displayed by gathering. In the canvas graphic information 51, data for one screen is configured by collecting a plurality of graphic types, line types, colors, and coordinates.

The monitor condition setting information 52 includes the number of screens for which monitor conditions are set, and a head address storage 52 in which monitor condition setting information 52b for each screen is stored.
a, and thereafter, a portion indicating the type of monitor such as a numerical display, a character string display, and a component display for each screen, a display position, and a monitor timing portion indicating timing for referring to the device of the programmer controller. The monitor condition setting information 52b corresponding to each screen is stored. In the monitor condition setting information 52b, data for one screen is configured by collecting a plurality of monitor types, display positions, and monitor timings.

The text canvas setting information 53 includes a text canvas setting information header 53 in which the number of screens on which the text canvas is set and the head address of the text canvas data 53b for each screen are stored.
a, and thereafter, text canvas data 53b composed of the number of characters of the text, the display position, and the character string code
Is stored. Note that canvas text data 5
3b, data for one screen is configured by collecting a plurality of text characters, display positions, and character string codes.

The auxiliary function information 54 includes an auxiliary function information header 54a in which the set auxiliary function start addresses are stored, followed by report data 54b as conditions for operating the respective auxiliary functions, and announcement data. 54c and audio data 54d are stored.

The monitor data shown in FIG. 5 is usually created by operating an S / W package 31 for creating monitor data on a personal computer 30 or the like. The data to be set at this time includes a basic graphic portion to be displayed on the display device 9 and characters to be displayed therein, or information on a device to be connected to the programmable controller and to monitor a device inside the programmable controller. Is displayed, or the contents of a device to be changed in response to a key input are set.

The data created as described above is read from the personal computer 30 or the like by a serial I / F such as RS232C as shown in FIG.
Then, the data is written to the monitor data memory 5 by the ROM writer 32, or is written to the monitor data memory 5 configured as a flash ROM based on communication. Normally, monitor data memory 5
A memory such as a ROM is used, and monitor data is stored in the ROM by writing data to the monitor data memory 5. By mounting the ROM on a monitor device, a device of the programmable controller can be monitored or a key can be input on a screen created by a user.

FIG. 6 is a diagram showing the structure of data stored in the audio buffer memory. As shown in the figure, when the audio output is 1ch output, the audio data is sequentially arranged in a continuous address order, but the audio output is 2ch.
In the case of output, the audio data of 1ch and 2ch are arranged at addresses that are alternately and consecutively arranged in the order of ch1 data and ch2 data.

FIG. 7 shows a phonetic character string.

Next, the operation of the operation terminal 1 will be described with reference to the drawings. Note that the monitor device 1
A case in which the programmable controller 20 is connected to and monitors the programmable controller 20 will be described.

In the monitor device 1, the CPU 2 previously sets R
Calculation and display processing are performed according to a microprogram stored in OM3. At the time of display processing, CPU 2
Communicates with the programmable controller 20 via the communication I / F 12 in order to sequentially read out the monitor data stored in the monitor data memory 5 and collect data to be monitored based on the monitor data. Based on the monitor condition setting information 52, the contents of the device in which the calculation result in the programmable controller 20 is stored are read from the programmable controller 20, and the contents of the device are stored in the work RAM 4.
Thereafter, the CPU 2 obtains a fixed display portion for one screen based on the canvas graphic information 51 and the text canvas setting information 53 stored in the monitor data, and reads the contents of the device which is the variable display portion read from the work RAM 4. Are combined and written to the VRAM 6. Then, the display controller 7 reads the data written on the VRAM 6 by the CPU 2 and outputs the data to the display I / F 8. Display I / F
8 converts the signal into an output suitable for the characteristics of the display device 9 and outputs the signal to the display device 9. For example, in the case of an LCD, a voltage and a current are converted into a level corresponding to the used LCD, and a display device 9 having an RGB input, such as a CRT, is converted into an RGB signal and output, thereby obtaining a predetermined signal. Is displayed on the display device 9.

When an interrupt is generated to the CPU 2 via the key input I / F 10 by a key input from the keyboard 11, the internal device information of the programmable controller 20 is determined based on the device number specified by the monitor data. To change.

On the other hand, the CPU 2 writes the voice data stored in advance in the monitor data memory 5 into the voice buffer memory 13 and outputs a sounding start signal to the voice control circuit 14 when the voice utterance conditions are satisfied. I do. The audio control circuit 14 counts the audio clock signal and sequentially stores the audio buffer memory 1 according to the timing.
3 and converted into serial data and output to the D / A conversion circuit 15. Then, the D / A conversion circuit 15
The input digital values are sequentially converted to analog data,
Output to the filter circuit 16. In the filter circuit 16,
A frequency component equal to or higher than a predetermined sampling frequency is cut and output to an output device such as a speaker.

The audio data stored in advance in the audio buffer memory 13 includes a CPU address bus and a CP.
An address to be stored in the audio buffer memory 13 is specified by the U write signal, and is written at a predetermined timing to the audio buffer memory 13 via the CPU data bus (the bus connection is switched by the gate circuit 145). I have.

Next, a description will be given of the operation of the voice control circuit from reading out the digitized voice data from the voice buffer memory 13 and converting it into voice. In general, analog data such as audio often has, as digital values, instantaneous values sampled at a sampling frequency twice or more the data frequency to be reproduced, and treats the digital values as data on a computer. At this time,
The resolution of the data is determined by how many bits of the digital value are converted. Then, the digital value is converted into analog data again, and the original analog data is reproduced to obtain audio.

In FIG. 2, an audio clock signal OSCLK is always input to the counter circuit 142 as a reference clock of the audio control circuit 14. This reference clock only needs to be changed 16 times or more because it is sufficient that the resolution of the digital value (the number of bits of the digital value) can be transmitted as serial data within the period of the sampling frequency. In the present embodiment, for example, a sampling frequency of 11 kHz
z, the reference clock (OSCLK) is 500 kHz, and the resolution of the digital value is 16 bits.

A sound generation start signal OSTART from the CPU 2
Is enabled at "H", the counter circuit 142 loads "22" which is an initial value into COUNTREG. At the same time, the shift register enable signal (ODENAB) = "H", that is, a disabled state, and audio data is read from address 0 of the audio buffer memory 13. Here, the shift register enable signal (ODENAB) is a signal for enabling output of serial data during the period of “L”. The sound buffer memory 13 transfers the sound data 54d in the monitor data memory 5 as monitor data when the sound generation condition is satisfied, and stores the data at a predetermined address in advance.

Thereafter, the counter value (COUNTRE) is synchronized with the fall of the audio clock signal OSCLK.
G) is decremented. Counter value (COUNTRE
When the value of G) becomes “16”, the shift register enable signal (ODENAB) = “L”, that is, the shift register is enabled. Further, the counter is decremented, and the value of the counter value (COUNTREG) becomes “15”.
Then, the audio data read from the audio buffer memory 13 is converted into serial data by the shift register 146 and output in synchronization with the fall of the audio clock signal OSCLK.

When the count value (COUNTREG) becomes “0”, the counter circuit 142 inverts the LRCLK signal frequency-divided by the frequency dividing circuit 141 and outputs the inverted LRCLK signal to the D / A conversion circuit 15 and at the same time shift register The enable signal (ODENAB) is set to “H”. D /
Since the A conversion circuit 15 has a resolution of 16 bits, LR
When the CLK signal is inverted, only the 16-bit serial data is determined to be a digital input and converted to analog data. Usually, one cycle of the LRCLK signal coincides with the sampling cycle of audio output (11 kHz in the case of the present embodiment).

When the value of the count value (COUNTREG) becomes "0", the address (OADR) for reading the audio data from the audio buffer memory 13 is incremented at the same time as the inversion timing of the LRCLK signal. The voice data at the address is read and transferred to the shift register 146. Together with the count value (COU
The value of (NTREG) is “22” which is the initial value.

Here, regarding the address (OADR),
More specifically, the cycle in which the LRCLK signal is inverted and then inverted again is defined as one cycle, and the address generation circuit 143 increments the address (OADR) every half cycle.

Address (O) every half cycle of LRCLK signal
The generation of ADR) will be described with reference to FIG. 3. In the address generation circuit 143, the address bus of the audio buffer memory 13 is connected from the A1 bit. That is, the value of the address connected to the audio buffer memory 13 is 0, 1, 2, 3, 4, 5,
The output (OADR) after the A1 bit changes to 0, 0, 1, 1, 2, 2,. Here, if the audio output is 1ch, the address of the counter is incremented by "1", and if the audio output is 2ch, the counter address is preset to be incremented by "2". Therefore, the audio output is 1ch.
In this case, the counter is incremented by one, and the output (OADR) after the A1 bit is 0 (for counter 0), 0 (for counter 1), 1 (for counter 2),
1 (corresponding to counter 3), 2 (corresponding to counter 4),... On the other hand, if the audio output is 2 ch, the counter is incremented by 2 and the output (OADR) after the A1 bit is 0 (corresponding to counter 0), 1
(Corresponding to counter 2), 2 (corresponding to counter 4), 3 (corresponding to counter 6),. Therefore, the address input to the audio buffer memory 12 is 0, 0, 1, 1, 2, 2, 2, every half cycle of the LRCLK signal when 1 channel is output.
..., and the same address is accessed twice. In addition, at the time of 2ch output, it becomes 0, 1, 2, 3,..., And accesses a continuous address once every half cycle of the LRCLK signal.

Thereafter, similarly, the counter value (COUNTRE)
G) is decremented, and when the counter value becomes “16”, the shift register enable signal (ODENAB) =
The shift register 146 is set to “L”.
The shift register enable signal (O
When DENAB) = “L” is received, the audio data is converted into serial data and output in synchronization with the audio clock signal OSCLK. Such an operation is repeated,
The audio data is read from the audio buffer memory 13,
The D / A conversion circuit 15 outputs analog data. The D / A conversion circuit 15 determines, based on the LRCLK signal transmitted from the audio control circuit 14, whether the data is audio data to be output from either ch1 or ch2, and transmits the transmitted serial data to a predetermined filter circuit. Then, the sound is output by transmitting the sound to the audio signal 16. This determination is made, for example, by LRC
It can be determined by the rise and fall of LK.

Next, a case where the audio data 54d in the monitor data in FIG. 5 is converted into a phonetic character string and stored will be described. This is created in advance in the S / W package 31 and stored in the main body monitor data memory 5 when the monitor data is downloaded. Specifically, as shown in FIG. 6, for example, the message 40 “Today is fine weather” has a waveform represented by waveform data 41. In order to handle the waveform data 41 as a digital value, sampling is performed at a predetermined time, and a voltage value for each time is stored as a digital value corresponding to the resolution. In this case, if the above-mentioned message is a one-second message, 11 kHz
When sampling at a resolution of z and 16 bits, the required memory size is 11000 × 16 bits. Therefore, the above-mentioned message “Today is fine weather” 40 is once converted into a phonetic character string 42. When converted to this phonetic character string, the actual sound to be pronounced is a normal character string 1 byte, accent / intonation 1
It consists of a total of 2 bytes. Therefore, when the above message is converted into a phonetic character string, “the number of characters × 2”
This is the data length in bytes. This phonetic character string is stored in the monitor data memory 5, and if necessary, the phonetic character string is converted into audio data by S / W and written into the audio buffer memory, thereby reducing the data amount of the audio data. it can.

According to the present embodiment, the address to which the audio control circuit accesses the audio buffer memory in which the audio data is stored alternately with ch1 and ch2 according to the address order is controlled, and the D / A By outputting the serial data and the LRCLK signal to the conversion circuit, the D / A conversion circuit can output audio according to ch1 and ch2, and the audio control circuit, the D / A conversion circuit, Since each of the audio buffer memories can be implemented by one configuration, the circuit configuration can be greatly simplified, and the mounting area, the number of components, and the cost can be reduced. In the present embodiment, the audio buffer memory has been described as having a single configuration, but a plurality of audio buffer memories may be provided since the address of the accelerator can be changed according to the channel in the audio control circuit.

[0053]

Since the present invention is configured as described above, it has the following effects.

In the operation terminal for performing a predetermined monitor display via the display device based on the stored display information according to the present invention and outputting a sound based on the stored sound data, a channel for outputting the sound data The audio buffer memory for alternately storing the audio data, the audio data for each channel stored in the audio buffer memory for reading and outputting the audio data, and the audio data received from the audio control means. And a conversion circuit for distributing the signals to the output channels and outputting the audio, so that the circuit configuration for outputting the audio can be simplified.

The audio data stored in the audio buffer memory is stored in the buffer memory in which the audio data is stored with consecutive address numbers.
Storage in the audio buffer memory is facilitated.

Further, the audio control means, when generating an address for accessing the audio buffer memory,
Since the output range of the output bit in the counter is changed and output as an address, and the number of increments of the counter is changed according to the number of output channels, an address for access can be easily created,
The circuit configuration can be simplified.

Since the data stored in the audio buffer memory is stored in a phonetic character string format, the amount of audio data, that is, the memory capacity can be reduced, and the cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an operation terminal according to the present invention.

FIG. 2 is a block diagram showing details of an audio control circuit.

FIG. 3 is a diagram showing a concept when an address created inside an address generation circuit is created.

FIG. 4 is a timing chart showing the timing of an audio control circuit.

FIG. 5 is a diagram showing the contents of a monitor data memory.

FIG. 6 is a diagram showing the contents of an audio buffer memory.

FIG. 7 is a diagram showing a phonetic character string.

FIG. 8 is a block diagram showing a configuration of a conventional operation terminal.

FIG. 9 is a configuration diagram for storing display contents in a monitor data memory.

FIG. 10 is a diagram showing the contents of a monitor data memory.

FIG. 11 is a block diagram showing a configuration of an operation terminal having an audio output function.

[Explanation of symbols]

1 monitor device, 2 CPU, 3 ROM, 4 RA
M, 5 monitor data memory, 6 VRAM, 7 display controller, 8 display I / F, 9 display device, 1
0 key input I / F, 11 keyboard, 12 communication I
/ F, 13 audio buffer memory, 14 audio control circuit, 15 D / A conversion circuit, 16 filter circuit, 20
Programmable controller, 141 divider circuit, 1
42 counter circuit, 143 address generation circuit, 14
4 Arbitration circuit, 145 gate circuit, 146 shift register.

Claims (4)

[Claims] An operation terminal for performing a predetermined monitor display via a display device based on the stored display information and outputting a sound based on the stored sound data; An audio buffer memory for alternately storing data, an audio control unit for reading and outputting audio data for each channel stored in the audio buffer memory, and an audio data received from the audio control unit. An operation terminal, comprising: a conversion circuit that distributes audio to channels and outputs audio. 2. The operation according to claim 1, wherein the audio data stored in the audio buffer memory is stored in the stored buffer memory with a continuous address number. Terminal. 3. An audio control unit, when generating an address for accessing the audio buffer memory, changes an output range of an output bit in a counter and outputs it as an address, and in accordance with the number of output channels, The operation terminal according to claim 2, wherein the number of increments of the counter is changed. 4. The operation terminal according to claim 1, wherein the data stored in the voice buffer memory is stored in a phonetic character string format.