JPH09212214A - Unit debugging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable the debugging of a sequence program using a unit even when a unit for a specific purpose or external equipment connected to the unit is not available by running software where dummy data on the unit are set from peripheral equipment. SOLUTION: On condition that the buffer memory allocation of a unit to be debugged is reflected on a buffer memory 15 of a debugging unit 1 as it is and reading from and writing to the buffer memory 15 of the debugging unit 1 from S/W running on the peripheral equipment 11 are possible, it is considered that a CP 6 operates as if the debugging unit 1 could substitute for a unit (A/D conversion unit, high-speed counter, etc.). Consequently, the sequence program in the PC 6 can be debugged even when the unit to be debugged or external equipment, etc., used for the unit is available when the debugging unit 1 is available.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for assisting in debugging a sequence program using a unit in a programmable controller.

[0002]

2. Description of the Related Art FIG. 14 shows a configuration example of a conventional programmable controller (hereinafter referred to as a PC as appropriate) (hereinafter appropriately referred to as PC).
It is a figure showing the system). 5 is a power supply unit, 6 is a PC, 7 is an input unit, 8 is an output unit,
Reference numeral 9 is a base, and 31 is a unit for supplementing a function that the PC 6 does not have, for example, an auxiliary unit. The PC 6 and each unit are mounted on the base 9. This conventional example is for the following description, and the unit configuration is arbitrary. Also,
The unit used here will be described below using an analog / digital conversion unit (hereinafter referred to as an A / D conversion unit) 31 as an example of the unit, but the type of the unit cannot be specified in the debug device of the present invention. Absent. The A / D conversion unit 31 is a unit for converting an input analog value (voltage or current) into a digital value. Conventionally, in the PC system as shown in FIG. 14, when the A / D conversion unit 31 of the sequence program inside the PC 6 is debugged, the A / D conversion unit 31 is actually attached to the base 9. And FIG.
5 is a functional block diagram of the A / D conversion unit.
The / D conversion unit 31 is supplied with an actual input (voltage or current) from the external device 35 to the voltage / current input terminal section 34 of FIG. 15, so that the actual input (voltage or current-> A /
The A / D converter 32 converts the analog value into a digital value from the analog value). After that, since the control circuit 33 operates to write the digital value in the buffer memory 15, the PC 6 uses the buffer memory read command 14 to read the digital value written in the buffer memory 15 by the above operation, and to read the value. Based on the above, the A / D conversion unit 31 is debugged. This debugging method is the same for other units. FIG. 16 is a functional block diagram of a high-speed counter unit, for example, regarding a unit called a high-speed counter unit. First, a buffer memory write command 13 is used from the PC 6 and necessary data (pulse input mode type and (Counter function type, etc.), and the pulse voltage is applied to the pulse voltage input terminal 62 from the external device 64, and the control circuit 63 counts from the applied pulse voltage and the data written in the buffer memory 15 by the above. do. Since the control circuit 63 operates to write the count value in the buffer memory 15, the PC 6 uses the buffer memory read instruction 14 to read the count value written in the buffer memory 15 by the above operation, Debugging work of the high-speed counter unit based on.

Details of the conventional debugging work are shown below.
FIG. 15 is a functional block diagram showing the A / D conversion unit 31 selected as an example of the unit. 1
Reference numeral 3 denotes a buffer memory write command for writing the data of the PC 6 into the buffer memory 15, and the direction of the arrow indicates the direction in which the command is issued. 14 is a buffer memory 15
Means a buffer memory read command for reading the data in the memory to the PC 6, and the direction of the arrow indicates the direction in which the command is issued. Reference numeral 15 is a buffer memory, and 16 is a PC interface. As shown in FIG. 17, in the buffer memory 15, the actual input (voltage or current) to the A / D conversion unit 31 is applied to determine the channel to be used, the use channel designation area 45 and the time / number of times. Averaging process designated area 46 for setting which average is to be taken and actual averaging time / number of times CH1 to CH8 averaging time /
There are a number-of-times area 47 and a CH1 to CH8 digital output value area 48 in which a value obtained by digitally converting an actual input (voltage or current) is included, and is divided into respective areas. PC6
Uses the buffer memory write instruction 13 and the buffer memory read instruction 14 via the PC interface 16 to the buffer memory 15 in the A / D conversion unit 31, and outputs data necessary for debugging such as a digital output value. Read and write. Reference numeral 34 denotes a voltage / current input terminal portion, which is a portion where an actual input (voltage or current) is actually input from the external device 35 to the A / D conversion unit. When an actual input (voltage or current) is applied to the voltage / current input terminal unit 34 from the external device 35, the actual input (voltage or current) is A /
It is treated as an analog value by the D conversion unit and converted into a digital value by the A / D converter 32. Then, by the control circuit 33, CH1 to C in the buffer memory 15
The converted digital value is written in the H8 digital output value area 48. The A / D conversion unit 31 selected as an example of the unit is debugged by a value obtained by digitally converting the input actual input (voltage or current).
The reason why the actual input (voltage or current) must be input from the voltage / current input terminal section 34 is that the buffer memory 1
Since the CH1 to CH8 digital output value areas 48 in 5 are normally read-only (that is, unwritable), it is not possible to directly write the digital values in the digital output value area 48 for debugging. Analog input (actual input) by adding actual input (voltage or current) to
CH1 in the buffer memory 15 digitally converted from
The value in the CH8 digital output value area 48 is read using the buffer memory read instruction 14, and the sequence program in the PC 6 is debugged based on the read data.

[0004]

The functional block diagram of the A / D conversion unit and the high speed counter unit described as an example of the unit is the same as the buffer memory 15 in the H / W. The memory allocation of the buffer memory 15 (specific data area held by each unit) is different. (For example, A / in FIG.
Buffer memory allocation of the D conversion unit and buffer memory allocation of the high-speed counter unit of FIG. 18) Therefore, for example, when debugging the A / D conversion unit, the A / D conversion unit is always required, and
External devices that actually apply voltage or current to the D conversion unit must also use external devices that can apply actual input (voltage or current) that can be used for the A / D conversion unit. Therefore, when debugging the A / D conversion unit, it is not possible to use a separate unit as a substitute for the A / D conversion unit, and an external device dedicated to the unit to be debugged is also required. There was a problem.

In view of the above-mentioned problems, the present invention makes it possible to debug a sequence program using a unit without using, for example, a unit for a specific purpose or an external device connected to the unit. The purpose is to provide a unit for use.

[0006]

A unit debug device according to the present invention uses a unit for supplementing a function which a programmable controller does not have, and when a sequence program in the programmable controller is debugged, By operating the software in which the pseudo data is set from the peripheral device, the sequence program in the programmable controller using the above unit is debugged.

[0007]

BEST MODE FOR CARRYING OUT THE INVENTION

First Embodiment of the Invention A debugging method of a PC system using a unit according to the present invention will be described in detail below with reference to the accompanying drawings, with reference to preferred embodiments by taking a relationship with a device for carrying out the debugging method.

FIG. 1 is a schematic view of a debugging unit according to an embodiment of the present invention. Reference numeral 1 is a debugging unit, 2 is a display for displaying the model name of the unit currently being simulated, 3 is a peripheral device interface for communicating with peripheral devices, and 4 is an external switch. Select the model of the unit to be simulated. FIG. 2 is a diagram showing a PC system including a debug unit according to an embodiment of the present invention. The power supply unit 5, the PC 6, the input unit 7, the output unit 8 and the base 9 are exactly the same as the conventional device shown in FIG. The debugging unit 1 shown in FIG. 2 is exactly the same as that shown in FIG. Reference numeral 10 in FIG. 2 denotes a cable connected to the peripheral device interface 3 for connecting to the peripheral device 11. Here, the peripheral device 11 operates the S / W that causes the debug unit 1 to be regarded as a pseudo A / D conversion unit. Hereinafter, the debug unit 1 and the peripheral device 11
The S / W executed in step 1 will be described.

The debug unit 1 will be described.
In FIG. 3, reference numeral 1 is a debugging unit. The display 2 and the peripheral device interface 3 are the same as those in FIG. The PC 6, the buffer memory 15, and the PC interface 16 are exactly the same as the conventional ones shown in FIG.
(However, the memory allocation of the buffer memory 15 is different.) 12 is the control circuit of the debugging unit,
It operates in response to a command from a computer or a command from a peripheral device. The processing contents of the control circuit will be described below. FIG. 4 is a processing flow of the debugging unit 1, which is processed by the control circuit 12. The description will be given below with reference to FIGS. 3 and 4. In step 4-1, a process of opening a communication line for communication with the PC interface 16 and the peripheral device interface 13 is performed as an initial process. In step 4-3, the model name of the unit designated by the external switch 4 is displayed on the display unit 2. In step 4-6, the buffer memory allocation data of the unit designated by the external switch 4 is held as fixed data inside the control circuit of the debugging unit, and the memory allocation data is reflected in the buffer memory 15. That is, the buffer memory allocation of the A / D conversion unit of FIG. 18 exists as fixed data in the control circuit 33, and it is reflected as it is in the position of the variable buffer memory allocation area 49 of the debugging unit of FIG. By this operation, the debug unit 1 can neutralize the buffer memory allocation of any unit. In step 4-4, the buffer memory 15 is read from the PC 6 (buffer memory read command 1
4) or when a command for writing to the buffer memory 15 (buffer memory write command 13) is issued, the control circuit 12 in FIG. 3 performs command processing in accordance with the command. Step 4-
5, when a command for reading the buffer memory from the peripheral device 11 or a command for writing the buffer memory is generated (the control circuit reads and writes the contents of the buffer memory 15 via the peripheral device interface 3), the command is adjusted to the command. The control circuit 12 of FIG. 3 performs command processing.

Thereafter, steps 4-4 and 4-5 are repeated. By repeating this, reading of the buffer memory 15 of FIG. 3 from the PC 6 and the peripheral device 11, or
Even if a write command is received, it can always be dealt with. When debugging a high-speed counter unit shown in FIG. 17 with a unit other than the above units, the A / D conversion unit 3 described above is used.
4 is different from 1 (the model name of the high-speed counter unit is, for example, "AD61"), and the buffer memory allocation data in 4-6 of FIG. 4 is changed. Then (because the buffer memory allocation in FIG. 19 is directly reflected in the position of the variable buffer memory allocation area 49 of the debugging unit in FIG. 5), the same operation is performed thereafter.

Next, a case where the A / D conversion unit 31 is simulated by the S / W operating on the peripheral device 11 will be described as an example. FIG. 6 shows a screen output to the S / W peripheral device 11, and FIG. 7 shows the S / W processing. As a configuration, a unit type selection screen 57, an analog input voltage / current selection screen 17, a used channel / averaging process designation screen 51, a voltage input / output conversion characteristic setting screen 18, a current input / output conversion characteristic setting screen 19, a voltage value input screen 20, There is a current value input screen 21, and the operation method is shown below.

When the S / W is started on the peripheral device 11, the unit type selection screen 57 of FIG. 6 is displayed, and the type of the unit to be debugged is selected there. (5 in FIG. 7
6. Here, "1.A68AD" is selected as an example.) After selecting the unit type, the analog input selection screen 17 is displayed on the peripheral device 11 and the analog input value (corresponding to the actual input) of the A / D conversion unit 31 is displayed. Selection is made by voltage or current (36 in FIG. 7). Next, the used channel / average processing designation screen 51 is displayed on the peripheral device 11, and both the used channel and the average processing designation are set. (55 in FIG. 7) 52 in FIG. 8 (CH1, CH
, ..., CH8) are set in hexadecimal notation so that the bit at the position of the channel to be used turns ON. The averaging process execution channel designated by the averaging process is located at the position 53 (CH1, CH2, ..., CH8 from the right end) in FIG. 9 so that the bit is turned on for the averaging process and the bit is turned off for the sampling process. Set in decimal notation. The time / count of averaging processing is 54 in FIG.
At the positions (CH1, CH2, ..., CH8 from the right end), the bit is turned on for time average, and the bit is turned off for number average, in hexadecimal notation. Next, when voltage is selected on the analog input selection screen 17 (when the 1 key is pressed), input / output characteristic setting (voltage)
The screen 18 is displayed on the peripheral device 11, and when the current is selected (when the 2 key is pressed), the input / output characteristic setting (current) screen 19 is displayed on the peripheral device 11. An offset value 22 and a gain value 23 are set respectively. (37 and 38 in FIG. 7) The offset value 22 is the maximum analog input value (voltage or current) of the digital output, and the gain value 23 is the minimum analog input value (voltage or current) of the digital output. .

Next, when the voltage is selected on the analog input selection screen 17 to set the analog input value, the input voltage setting screen 20 is displayed and the analog input selection screen 17 is displayed.
When the current is selected in, the input current setting screen 21 is displayed, and F1 which is the function key of the peripheral device 11 is displayed.
To F8 key to specify the analog input value channel (this A
The / D conversion unit 31 is assumed to be capable of analog input of up to 8 channels) (39 and 40 in FIG. 7),
The analog input value (voltage or current) is set on the selected channel designation destination, and the averaging time or the average number of times is set on the setting. (41 and 42 in FIG. 7) Next, the analog input value set above is converted from the offset value 22 and the gain value 23 into a digital value. As shown in the input / output conversion characteristic graph of FIG. 10, the conversion method is such that the offset value 22 becomes the point of the analog input value when the digital value becomes 1000, and the gain value 23 becomes the analog input value when the digital value becomes 0. It becomes a point. The straight line graph connecting these two points becomes the input / output characteristic, and the analog input value (voltage or current) set above is converted into the digital value of the value shown in this graph. However, as a limitation of the A / D conversion unit 31, the maximum digital value is 2047 and the minimum digital value is -2048. As the S / W processing,
If it is an input / output characteristic setting (voltage), gain x is used from the offset value and gain value set on the voltage input / output conversion characteristic setting screen 18 and the value (analog value) of the actual input (voltage) added to the channel to be used. Digitally converted by the actual input value + offset value applied to the channel. Further, if the input / output characteristic setting (current), the gain x is obtained from the offset value and the gain value set on the current input / output conversion characteristic setting screen 19 and the actual input (current) value (analog value) added to the channel to be used. Digitally converted by the actual input value + offset value added to the channel to be used. (43 and 44 in FIG. 7) Then, the digitally converted value is written in the CH1 to CH8 digital output value area 48 of the buffer memory 15 of the debugging unit 1. From the above, from the perspective of the PC 6, the C of the buffer memory 15 of the debugging unit 1
H1-CH8 digital output value area 48 is a normal A /
Since the position is the same as the area containing the digital output value of the D conversion unit, the debugging unit 1 operates as if it were the A / D conversion unit 31 (the actual A / D conversion unit is not (Necessary), and debugging without the need for external equipment is possible.

As another example, in the case of a high speed counter unit, the AD61 (high speed counter unit) is selected at 57 in FIG. 11, and the following is the same idea as the S / W of the above A / D conversion unit. Then, set the data required to operate the high-speed counter unit. This sets the data in the buffer memory in FIG. 18 according to the setting screens 57 to 61 in FIG. In the pulse input mode selection screen 58, one-phase pulse input (one input point of pulse voltage) or two-phase pulse input (two input points of pulse voltage are input).
Location) and use the latch counter function (when the pulse voltage is input to the pulse voltage input terminal unit 62, the current value of the counter is held in the counter function selection count value area 66) on the counter function selection screen 59. Select a condition to store in the counter function selection count value area 66 such as
Reset value when resetting the value of (preset value)
And so on. Then, on the final CH limit switch output data setting screen 61, the number of multi-dogs (pointing to the peak of the pulse waveform) for each CH is set. Then, the set value is sent from the peripheral device to CH1 of the buffer memory 15.
~ If you write in the CH8 limit switch output data setting area, the debugging unit 1 will operate as if it were a high-speed counter unit for the same reason as the A / D conversion unit 31 (the actual high-speed counter unit It is not necessary), and the external device 64 for applying the pulse voltage to the pulse voltage input terminal portion 62 of FIG. 17 is not necessary. Next, in the communication method between the peripheral device 11 and the debug unit, in the case of writing the value digitally converted by the peripheral device 11 into the CH1 to CH8 digital output value area 48 of the buffer memory 15 of the actual debug unit 1, Describe the communication procedure. The communication between the peripheral device 11 and the debugging unit 1 is performed by transmitting and receiving a message in a predetermined form. As a procedure, a request command (a request instruction of information that the self wants to obtain) is issued from the peripheral device 11. And the result is returned from the debugging unit 1 to the peripheral device 11 (FIG. 12). An example of a communication method at the time of writing to the buffer memory 15 will be given below.

The peripheral device transmission data 24 in FIG. 13 is a request command transmitted from the peripheral device 11 at the time of writing, and the peripheral device transmission data 26 requests the peripheral device 11 to write to the debugging unit 1. This is the place to set, and by setting 1 here, the debug unit 1 can determine that the write request has been sent from the peripheral device 11, and then the debug unit 1 is set inside the debug unit 1. The recognition is changed to be a write request to the buffer memory 15. Peripheral device transmission data 2
Reference numeral 7 is a place for setting a writing position in the buffer memory 15, and if 3 is set here, it means to write the data sent from the peripheral device 11 from the third position from the beginning of the buffer memory 15. The peripheral device transmission data 28 designates how many data is written to the buffer memory 15 from the area designated by the peripheral device transmission data 27. When 2 is set here, the data from the head of the buffer memory 15 is 3rd to 2nd. This indicates writing of data for the number of pieces (from the third to fourth positions of the buffer memory 15). As the peripheral device transmission data 29, the data to be written (the value to be actually written (pseudo digital conversion value) → for example 100 and 200) is set in the third to fourth positions of the buffer memory. This data is required by the number specified by the peripheral device data 26. When the peripheral device transmission data 24 from the peripheral device 11 including the above contents is transmitted from the peripheral device 11 to the debugging unit 1, the value written in the peripheral device transmission data 29 in the buffer memory 15 of the debugging unit 1 (for example, 100 and 200) in the buffer memory 15 of the debugging unit 1. After that, the debugging unit 1 transmits a completion flag 30 (write completion signal → 1) to the peripheral device 11 by using the debug unit transmission data 25 of FIG. Communication is completed. The above procedure is the same for a unit (for example, a high-speed counter unit)

From the above description, the buffer memory allocation of the unit to be debugged is directly reflected in the buffer memory 15 of the debugging unit 1, and the buffer memory of the debugging unit 1 is changed from the S / W operating on the peripheral device 11. If it is possible to read / write to 15, the debugging unit 1 can be replaced by the PC 6 as if it were a debugged unit (A / D conversion unit, high-speed counter unit, etc.).
Debugging of the internal sequence program is possible even if there is no unit to be debugged, or there is no external device or the like to be inserted into the unit, as long as it has the debugging unit 1 of the present invention.

[0017]

According to the present invention, even if the unit to be debugged is not present at the time of debugging, the unit to be debugged can be substituted by the debug device of the present invention. In addition, the unit debug device of the present invention, when debugging the A / D conversion unit, for example, when the data corresponding to the actual input from the S / W of the peripheral device is set in the debug device, the debug device is as if the external device. Input the actual input into the A / D conversion unit from
Since the A / D conversion unit can output a value as if it had been digitally converted, debugging work can be performed by the unit alone without the external device which was conventionally required.

[Brief description of drawings]

FIG. 1 is a schematic view of a debugging unit of a unit debugging device of the present invention.

FIG. 2 is a configuration diagram of a PC system including a unit debug device of the present invention.

FIG. 3 is a functional block diagram in which a debugging unit of the unit debugging apparatus of the present invention and peripheral devices are connected.

FIG. 4 is a processing flow diagram of a debugging unit of the unit debugging device of the present invention.

FIG. 5 is a diagram showing allocation of a buffer memory according to the present invention.

FIG. 6 is a screen configuration diagram when an A / D conversion unit is selected by software operating on a peripheral device of the unit debug device of the present invention.

FIG. 7 is a diagram showing a flow in an A / D conversion unit which is an example of internal processing of S / W.

FIG. 8 is a diagram showing detailed allocation of a used channel designation area of a buffer memory of an A / D conversion unit which is an example of a unit.

FIG. 9 is a diagram showing detailed allocation of an average processing designated area of a buffer memory of an A / D conversion unit which is an example of a unit.

FIG. 10 is an input / output conversion characteristic graph for converting analog values of voltage and current into digital values.

FIG. 11 is a screen configuration diagram when a high-speed counter unit is selected by software operating on a peripheral device of the unit debug device of the present invention.

FIG. 12 is a diagram showing a simple message flow when a debugging unit of the unit debugging apparatus of the present invention and a peripheral device are connected.

FIG. 13 is a diagram showing an example of data transmitted by the unit debug device of the present invention and peripheral devices.

FIG. 14 is a configuration diagram of a PC system including an A / D conversion unit which is an example of the unit.

FIG. 15 is a functional block diagram of an A / D conversion unit that is an example of a unit.

FIG. 16 is a functional block diagram of a high-speed counter unit that is an example of a unit.

FIG. 17 is a diagram showing allocation of a buffer memory of an A / D conversion unit which is an example of a unit.

FIG. 18 is a diagram showing allocation of a buffer memory of a high speed counter unit which is an example of a unit.

[Explanation of symbols]

1 debug unit, 2 display unit, 3 peripheral device interface, 4 external switch, 5 power supply unit,
6 PC, 7 input unit, 8 output unit, 9
Base, 10 cables, 11 peripheral devices, 12 debug unit control circuit, 13 buffer memory write command, 14 buffer memory read command, 15 buffer memory, 16 PC interface, 24 data sent from peripheral device to debug unit , 25 Data to be sent from the debug unit to peripheral devices, 26
Write request code, 27 Specify buffer memory area,
28 data size to write, 29 data size to write, 30
Completion flag, 36 Analog input value type selection process,
37 Offset value / gain value setting processing when input / output characteristic setting (voltage), 38 Offset value / gain value setting processing when input / output characteristic setting (current), 39 Channel selection processing when analog input is voltage, 40 analog input Is a channel selection process when current is applied, 41 Voltage setting process applied to selected channel, 42 Current setting process applied to selected channel, 43 Digital conversion process when analog input is voltage, 44 Digital conversion when analog input is current Processing, 49 Variable buffer memory allocation area of debug unit, 51 used channel / average processing specification screen, 52 A / D conversion unit used channel setting location, 53 A / D conversion unit average processing channel specification location, 54 A / Time of D conversion unit /
Designated number of times, 55 used channel and setting process of averaging process designation, 56 unit type selection process, 57
Unit type selection screen, 58 pulse input mode selection screen, 59 counter function selection screen, 60 other setting screen, 61 CH limit switch output data setting screen.

Front page continuation (72) Inventor Nobuyuki Murase 5107, Kamio, Sone-cho, Higashiodasone, Kita-ku, Nagoya City Mitsubishi Electric Mechatronics Software Co., Ltd. (72) Yoshiaki Goto 1071, Kamie-cho, Higashiodasone, Kita-ku, Nagoya Address Mitsubishi Electric Mechatronics Software Co., Ltd. (72) Inventor Yoshimi Tanaka, 5107-1071, Kamie, Sone-cho, Higashi-Osone, Kita-ku, Nagoya City Mitsubishi Electric Mechatronics Software Co., Ltd.

Claims (1)

[Claims] 1. When a unit for compensating for a function which a programmable controller does not have is used and a sequence program in the programmable controller is debugged, software in which pseudo data of the unit is set is operated from a peripheral device. By doing so, the unit debug device is characterized in that the sequence program inside the programmable controller using the above unit is debugged.