JPH11327511A - Liquid crystal display control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To miniaturize a device and to reduce the cost of the device by outputting data transfer clocks to respective liquid crystal displays. SOLUTION: Display data of the first scanning line of a liquid crystal display 4A are transferred from a VRAM 2 to the segment driver 6 of the display 4A and a data transfer clock selecting and outputting circuit 3 outputs the number of data transfer clocks equivalent to one scanning line to the driver 6 as a data transfer clock 1 (CP1). Next, display data of the first scanning line of a liquid crystal display 4B are transferred from the VRAM 2 to the segment driver 6 of the display 4B and the data transfer clock selecting and outputting circuit 3 outputs the data transfer clock to be outputted from a liquid crystal control LSI 1 to the driver 6 of the display 4B as a CP2. When the transfer of display data of the first scanning line of a liquid crystal display 4C is completed, the liquid crystal control LSI 1 outputs a display data latch pulse and a frame synchronizing signal to input them to the liquid crystal displays 4A to 4C and segments of respective first scanning lines are driven.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control circuit for a liquid crystal display.

[0002]

2. Description of the Related Art As shown in Japanese Patent Application Laid-Open No. Hei 6-318059, the prior art controls a display in one liquid crystal display by dividing it into a plurality of screen areas. In such a system, a liquid crystal data transfer control circuit composed of a VRAM and a general LSI is required for each liquid crystal display. Therefore, in a device requiring a plurality of liquid crystal displays, the number of VRAMs and liquid crystal data transfer control circuits increases,
The size and cost of the device could not be reduced.

[0003]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems and control a plurality of liquid crystal displays with a set of VRAM and liquid crystal data transfer control circuits to reduce the size and cost of the device. It is to plan.

[0004]

In order to solve the above problems, a data transfer clock selection output circuit for sequentially selecting and outputting a data transfer clock for transferring data to a liquid crystal display to a plurality of liquid crystal displays is provided. .

[0005]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described with reference to FIGS.

First, a method of displaying one liquid crystal display 4 will be described.

The liquid crystal display 4 comprises a liquid crystal display 5 composed of the pixels shown in FIG. 3, a segment driver 6 for driving segments arranged in the X-axis direction, and a common driver 7 for driving scan lines in the Y-axis direction. Consists of The display on the liquid crystal display 4 is performed in the following procedure. First, the liquid crystal control LSI 1 is connected to segment 1 of the first scan line.
To 8 are read from the VRAM 2 and display data (D
0 to D7). At this time, the display data (D0 to D
The data transfer clock (CP) is output in synchronization with 7). The segment driver 6 uses a data transfer clock (C
P), the display data (D0 to D7) output from the liquid crystal control LSI 1 is fetched. Thereafter, the display data of the first scan line is sequentially transferred to the segment driver 6. When the transfer to the display data of the last segment is completed, the LCD control L
SI1 outputs a display data latch pulse (LP).
At this time, a frame synchronization signal (FLM) indicating the first scan line is output at the same time. The common driver 7 and the segment driver 6 of the liquid crystal display 4 drive the segment of the first scan line by the display data latch pulse (LP) and the frame synchronization signal (FLM). Hereinafter, similarly, display data is transferred from the second scanning line to the last scanning line to perform display. When the display is completed up to the last scan line, the display returns to the first scan line and the same display is repeated.

Next, three liquid crystal displays 4A, 4B and 4C are connected to one set of a liquid crystal control LSI 1 and a VRAM
The method of displaying the information in 2 will be described. First, display data of the first scanning line of the liquid crystal display 4A is transferred from the VRAM 2 to the segment driver 6 of the liquid crystal display 4A. At this time, the data transfer clock (C) output from the liquid crystal control LSI 1
P) is input to the data transfer clock selection output circuit 3. The data transfer clock selection output circuit 3 counts the number of data transfer clocks for one scanning line, and outputs it to the segment driver 6 of the liquid crystal display 4A as a data transfer clock 1 (CP1).

When the transfer of the display data of the first scan line of the liquid crystal display 4A is completed, the display data of the first scan line of the liquid crystal display 4B is transferred from the VRAM 2 to the segment driver 6 of the liquid crystal display 4B. At this time, the data transfer clock selection output circuit 3 outputs the data transfer clock (CP) output from the liquid crystal control LSI 1 to the data transfer clock 2.
It outputs to the segment driver 6 of the liquid crystal display 4B as (CP2). When the transfer of the display data of the first scanning line of the liquid crystal display 4B is completed, the display data of the first scanning line of the liquid crystal display 4C is transferred in the same manner. Liquid crystal display 4C
When the display data transfer of the first scan line is completed, the liquid crystal control LSI 1 outputs a display data latch pulse (LP). At this time, a frame synchronization signal (FLM) indicating the first scan line is output at the same time. The display data latch pulse (LP) and the frame synchronization signal (FLM) are simultaneously input to the three liquid crystal displays 4A, 4B, 4C, and the segments of the first scanning line of the liquid crystal displays 4A, 4B, 4C are driven. Hereinafter, similarly, display data from the second scanning line to the last scanning line is displayed on three liquid crystal displays 4A, 4B, and 4C.
And display it. When the display is completed up to the last scan line, the display returns to the first scan line and the same display is repeated. When displaying the three liquid crystal displays 4A, 4B and 4C, the arrangement of the liquid crystal display data of the VRAM 2 is such that the data of the three liquid crystal displays are alternately arranged for each scanning line as shown in FIG. Keep it. As a result, the liquid crystal control LSI 1 becomes 3
The data can be transferred to three liquid crystal displays as if the data were transferred to one liquid crystal display without being aware of switching between the liquid crystal displays 4A, 4B, and 4C.

In this embodiment, an example in which three liquid crystal displays are controlled has been described, but more liquid crystal displays can be controlled by increasing the frequency of the data transfer clock.

[0011]

According to the present invention, a liquid crystal control LSI and a VRAM, which are several minutes required for a conventional liquid crystal display, can be controlled by a set of a liquid crystal control LSI and a VRAM. Cost reduction can be achieved.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a liquid crystal display control circuit showing one embodiment of the present invention.

FIG. 2 is a display data transfer time chart.

FIG. 3 is a pixel configuration of a liquid crystal display.

FIG. 4 is a liquid crystal display data array of a VRAM.

[Explanation of symbols]

1 ... Liquid crystal control LSI, 2 ... VRAM,
3 data transfer clock selection output circuit, 4 liquid crystal display, 5 liquid crystal display, 6 segment driver, 7 common driver.

Claims (1)

[Claims] 1. A liquid crystal display comprising a liquid crystal panel, a segment driver for driving liquid crystal segments arranged in the X axis direction of the liquid crystal panel, and a common driver for driving scanning lines arranged in the Y axis direction of the liquid crystal panel. A VRAM storing data to be displayed on the liquid crystal display, and a liquid crystal data transfer control circuit reading data from the VRAM and transferring data to the liquid crystal display. A liquid crystal display is controlled by a set of VRAMs and a liquid crystal data transfer control circuit, and a data transfer clock selection output circuit for sequentially selecting and outputting a data transfer clock for transferring data to the liquid crystal display to a plurality of liquid crystal displays is provided. A liquid crystal display control circuit characterized in that: